TWI860141B - Automatic test equipment architecture providing odd sector size support and method of accessing memory of one or more devices under test - Google Patents

Abstract

Automatic test equipment (ATE) configured to test devices under test (DUTs) can include a host device tester, one or more load boards, and one or more host bus adapters (HBAs). The host device tester does not support odd sector sizes and/or non-standard sector sizes. The one or more load boards can be communicatively coupled to the host device. The one or more HBAs can be communicatively coupled between respective load boards and one or more respective devices under test (DUTs). The one or more load boards can be configured to communicate with respective HBAs using one or more first communication protocol interfaces. The one or more HBAs can be configured to communicate with the respective DUTs using one or more second communication protocol interfaces. The HBAs can be configured to translate commands and data between the host device tester and the one or more DUTs that support odd sector size or non-standard sector size.

Description

An automatic test equipment architecture providing odd sector size support and a method for accessing the memory of one or more devices under test Cross-reference to related applications

This application claims the benefit of U.S. Provisional Patent Application No. 63/429,065 filed on November 30, 2022, and U.S. Provisional Patent Application No. 63/439,861 filed on January 19, 2023, the entire contents of which are incorporated herein.

This disclosure relates to an automated test equipment architecture that provides odd sector size support.

Automated test equipment (ATE) is equipment used to test devices under test (DUT), such as, but not limited to, electronic systems and components. ATE may include a number of instruments capable of automated testing, characterizing performance, diagnosing faults, and similar activities.

ATE may include a host device tester (also referred to as a controller), one or more sources and acquisition instruments, which are coupled to one or more DUTs via one or more carrier boards (also referred to as interface boards). The host device tester may be a computer, which typically synchronizes the one or more sources and acquisition instruments. Sometimes, the device used to implement ATE does not support the functions implemented in the DUT. Therefore, there is a continuing need for improved ATE devices and methods.

The present technology may be best understood by reference to the following description and accompanying drawings, which illustrate embodiments of the present technology for automated testing of devices with odd sector sizes and/or non-standard sector sizes.

In one embodiment, an automatic test equipment (ATE) device may include a host device tester, one or more carrier boards, and one or more host bus adapters (HBAs). The one or more carrier boards may be communicatively coupled to the host device tester. The one or more HBAs may be coupled between corresponding carrier boards and DUTs. The carrier boards may be configured to communicate with corresponding HBAs using a first communication protocol interface. The HBAs may be configured to communicate with corresponding DUTs using a second communication protocol interface. The HBAs may be further configured to convert commands and data between the first communication protocol interface and the second communication protocol interface to support odd sector sizes and/or non-standard sector sizes of memories of the DUTs.

In another embodiment, an HBA is coupled to a carrier board between a host device tester and one or more DUTs. The one or more DUTs support one or more odd sector sizes and/or non-standard sector sizes. However, the host device tester executes an operating system that does not support the one or more odd sector sizes and/or non-standard sector sizes. The HBA can be configured to convert memory accesses to odd sector size memory accesses or non-standard sector size memory accesses.

In yet another embodiment, a method for accessing memory of one or more DUTs may include receiving, by a carrier board, a memory access from a host device tester over a first communication protocol interface. An operating system (OS) of the host device tester does not support an odd sector size or a non-standard sector size. The carrier board may pass the memory access from the host device tester to one or more HBAs. The HBA may convert the memory access into an odd sector size or non-standard sector size memory access. The HBA may then send the odd sector size or non-standard sector size memory access to one or more DUTs over a second communication protocol interface, wherein the one or more DUTs support the odd sector size or the non-standard sector size memory access.

This [invention content] is provided to introduce a concept selection in a simplified form that is further described in the [implementation method] below. This [invention content] is not intended to identify the key features or important features of the claimed subject matter, nor is it intended to be used to limit the scope of the claimed subject matter.

110: Tester

120: Loading board

130-1,130-m: Host Bus Adapter (HBA)

140-1,140-2,140-n:DUT

150: Processor

160: Operating system

170: User Space Tester Application

205,210,215,220,225,230,235,240,245,250,255,260:Process

Embodiments of the present technology are illustrated by way of example and not limitation in the accompanying drawings, wherein like reference symbols refer to similar elements, and wherein: FIG. 1 illustrates an automatic test equipment (ATE) architecture for providing odd or non-standard sector size access to a memory of a device under test (DUT) in accordance with aspects of the present technology.

Figures 2A and 2B illustrate a method for supporting odd or non-standard sector size access to the memory of a DUT according to the present technology.

Reference will now be made in detail to embodiments of the present technology, examples of which are illustrated in the accompanying figures. Although the present technology will be described in conjunction with these embodiments, it will be understood that these embodiments are not intended to limit the disclosure of the present technology to these embodiments. On the contrary, the present invention is intended to cover alternatives, modifications, and equivalents that may be included within the scope of the present invention as defined by the scope of the accompanying patent application. Furthermore, in the following detailed description of the present technology, many specific details are presented in order to thoroughly understand the present technology. However, it is understood that the present technology can be practiced without these specific details. In other examples, in order to avoid unnecessary confusion of the state of the present technology, well-known methods, procedures, components, and circuits are not described in detail.

Some embodiments of the present technology are presented below in terms of routines, modules, logic blocks, and other symbolic representations of operations on data within one or more electronic devices. Such descriptions and representations are the means by which one of ordinary skill in the art most effectively communicates the content of one's work to other persons of ordinary skill in the art. A routine, module, logic block, and/or the like is herein and generally considered to be a self-consistent sequence of processes or instructions leading to a desired result. Such processes are those that include physical manipulations of physical quantities. These physical manipulations take the form of electrical or magnetic signals that are typically, but not necessarily, capable of being stored, transferred, compared, and otherwise manipulated in an electronic device. For convenience and in accordance with common usage, please refer to the embodiments of the present technology, where these signals are referred to as data, bits, values, elements, symbols, characters, terms, numbers, strings, and/or the like.

However, it should be remembered that these terms should be interpreted as referring to physical manipulations and quantities and are merely convenient labels and should be further interpreted in light of the terms commonly used in the art. Unless otherwise apparent from the following discussion, it is understood that throughout the discussion of the present technology, discussions utilizing terms such as "receiving" and the like refer to the actions and processes of an electronic device, such as an electronic computing device, manipulating and transforming data. Data is represented as physical (e.g., electronic) quantities within the logic circuits, registers, memory, and/or the like of an electronic device and is transformed into other data that is similarly represented as physical quantities within the electronic device.

In the present application, the use of antonymous conjunctions is intended to include conjunctions. The use of definite or indefinite articles is not intended to indicate cardinality. In particular, a reference to "the" object or "an" object is also intended to indicate one of a possible plurality of such objects. The use of the words "comprise" and/or its variations, "include" and/or its variations and the like specifies the existence of the described elements, but does not exclude the existence or addition of one or more other elements and/or groups thereof. It is also to be understood that although the terms first, second, etc. may be used herein to describe various elements, such elements should not be limited to these terms. These terms are used herein to distinguish one element from another. For example, a first element may be referred to as a second element, and similarly, a second element may be referred to as a first element, but will not depart from the scope of the embodiments. It is also understood that when an element is referred to as being "coupled" to another element, the element may be directly or indirectly connected to the other element, or there may be an intervening element. In contrast, when an element is referred to as being "directly connected" to another element, there is no intervening element. It is also understood that the term "and/or" includes any and all combinations of one or more of the associated elements. It is also understood that the words and terminology used herein are for illustrative purposes and should not be considered limiting.

Aspects of the present technology are used to provide odd sector size and/or non-standard sector size support for memory testing in a device under test (DUT) by automated test equipment (ATE). In an ATE architecture, according to aspects of the present technology, a host bus adapter (HBA) is located between a carrier board and a DUT. The DUT supports odd sector size and/or non-standard sector size access, while the host device of the tester does not support odd sector size or non-standard sector size access. Odd sector size and/or non-standard sector size, as used herein, means a sector size that is not a power of two. The HBA is adapted to perform conversions between a communication interface of the host device of the tester and a communication interface of the DUT to support odd sector size and/or non-standard sector size access to the media of the DUT.

Referring now to FIG. 1 , an ATE architecture is shown according to aspects of the present technology. The ATE architecture includes a tester 110 coupled to one or more carrier boards 120. The carrier board 120 is also referred to as an interface board that includes additional hardware (e.g., FPGA and HBA). The ATE architecture may also include one or more HBAs 130-1, 103-m coupled between one or more DUTs 140-1, 140-2, 140-n and the one or more carrier boards 120. The tester 110 may be implemented by a host device. The host device of the tester 110 does not support odd sector size or non-standard sector size memory access. In one implementation, the host device may be implemented by one or more computers running a Linux or Windows operating system (OS), or other computing device and operating system combination, which does not support odd sector size or non-standard sector size memory access. One or more DUTs 140-1, 140-2, 140-n may support odd sector sizes. DUTs 140-1, 140-2, 140-n may allocate one or more sectors for access by a user. Sectors of the storage media of DUTs 140-1, 140-2, 140-n may be configured to include protection information, or may be configured to have no protection information.

The host device of the tester 110 can be communicatively coupled to one or more mounting boards 120 via a first communication protocol interface, such as a peripheral component express (PCIe). One or more DUTs 140-1, 140-2, 140-n can be communicatively coupled to one or more mounting boards 120 via a second communication protocol interface, such as a serial attached small computer system interface (SAS). In one implementation, the second communication protocol interface that communicatively couples one or more DUTs 140-1, 140-2, 140-n to one or more mounting boards 120 can be one or more SAS4 interfaces.

In one implementation, a test application in a user space 170 generates memory accesses including one or more commands and optionally accompanying data. The operating system 160 of the host device of the tester 100, such as Linux and Windows, does not support odd sector sizes or non-standard sector sizes because it does not provide services for memory buffers that are exact multiples of the sector size. However, the user space tester application 170 can be configured to increase the size of the memory buffer used in block device accesses based on the odd sector size or non-standard sector size configuration of one or more DUTs 140-1, 140-2, 140-2, 140-n. For accesses to odd or non-standard sector sizes, the operating system will use a memory buffer of increased size.

The one or more carrier boards 120 may also provide one or more functions for testing of the DUTs 140-1, 140-2, 140-n. The carrier boards 120 may be used, for example, to input test patterns to the corresponding DUTs 140-1, 140-2, 140-n, comparator functions, and the like. The use of the one or more carrier boards 120 reduces the load on the processor(s) 150 of the host device of the tester 110. For example, one or more processors 150 of the host device tester may transfer commands and test patterns to the one or more carrier boards 120. The one or more carrier boards 120 may apply the test patterns to the corresponding DUTs 140-1, 140-2, 140-n according to the commands. The one or more carrier boards 120 may also generate metadata, protection information, or the like based on the data access test patterns and corresponding commands. Instead of returning all data to the processor 150 of the host device of the tester 110, the one or more carrier boards 120 may only return data related to the faults detected in response to the test patterns applied to the corresponding DUT 140-1, 140-2, 140-n. In one implementation, the functions of the one or more carrier boards 120 may be implemented by one or more field programmable gate arrays (FPGAs), application specific integrated circuits (ASICs), and/or the like. In one implementation, the one or more carrier boards 120 may be PCIe boards. In one implementation, the HBA 130-1, 130-m may be a commercial third-party HBA. Third-party as used herein refers to one or more manufacturing entities that are different from one or more manufacturing entities of the tester 110 and/or the carrier board 120. One or more DUTs 140-1, 140-2, 140-n may support odd sector sizes and/or non-standard sector sizes, such as sector sizes of 512+8, 4096+8, 520+0, 528+0, 4104+0, and 4224+0 bytes per sector. In one implementation, one or more DUTs 140-1, 140-2, 140-n may be, but are not limited to, solid state drives (SSDs) that support odd sector sizes and/or non-standard sector sizes for storing data and metadata, protection information (PI), or the like. In one implementation, odd sector sizes may be associated with protection information, and non-standard sector sizes may have no protection information. DUTs 140-1, 140-2, 140-n may be operable to allocate an entire sector for a user space.

One or more carrier boards 120 may be configured to generate repeatable test patterns sized for each of a plurality of odd sector sizes and/or non-standard sector sizes. For example, the SSD DUTs 140-1, 140-2, 140-n may support a number of different odd sector sizes and/or non-standard sector sizes. The SSD DUTs 140-1, 140-2, 140-n may, for example, support a standard sector size of 512+0 bytes, an odd sector size of 512+8 bytes, and a non-standard sector size of 528+0 bytes. The one or more carrier boards 120 may repeatedly cycle through the various sector sizes and protection modes and test the SSD DUTs 140-1, 140-2, 140-n for each of the sector sizes. For example, the carrier board may first test the SSD using a 512-byte sector size. The carrier board may then reformat the SSD for a 512+8-byte sector size and test the reformatted SSD with the data and the resulting protection information. The carrier board may then reformat the SSD again for a 528+0 sector size. In this manner, embodiments of the present technology may test the DUTs 140-1, 140-2, 140-n for all supported sector sizes. In other implementations, one or more carrier boards 120 may be configured for selected sector sizes and protection modes and the SSD DUTs 140-1, 140-2, 140-n may be tested for the selected sector sizes.

In one implementation, the host device of the tester 110 may communicate with one or more mounting boards 120 using the PCIe communication protocol, and vice versa, and the one or more mounting boards 120 may communicate with one or more HBAs 130-1, 130-m using the PCIe communication protocol, and vice versa. The HBAs 130-1, 130-m may communicate with one or more DUTs 140-1, 140-2, 140-n using the SAS communication protocol, and vice versa. The one or more DUTs 140-1, 140-2, 140-n may provide support for odd sector sizes and/or non-standard sector sizes, but the host device of the tester 110 does not provide support for odd sector sizes or non-standard sector sizes. Therefore, HBA 130-1, 130-m can provide conversion between PCIe communication protocol and SAS communication protocol, and vice versa. Therefore, the host device of tester 110 does not need to be aware of odd sector size or non-standard sector size. In particular, the Linux operating system of the host device does not need to be aware of odd sector size or non-standard sector size, or any support thereof. Instead, the Linux operating system of the host device of tester 110 can communicate with the mounting board 120 using PCIe communication protocol.

In one implementation, the first and second communication protocol interfaces, along with the conversion between the first and second communication protocol interfaces, can be planned into one or more HBAs 130-1, 130-m. Therefore, one or more HBAs 130-1, 130-m can be reconfigured to support a number of different first and second communication protocol interfaces. In another implementation, one or more HBAs 130-1, 130-m can implement a specific set of first and second communication protocol interfaces, along with the conversion between the first and second communication protocol interfaces. If a different set of communication protocol interfaces and the conversion between them is required, then for different HBAs implementing the different set of communication protocol interfaces and the conversion between them, HBAs implementing the first and second communication protocol interfaces and the conversion between them can be replaced.

The tester 110 may include additional modules, components, subsystems, and the like, but these are not described herein because they are not necessary for understanding aspects of the present technology. Similarly, the ATE architecture may also include additional modules, components, subsystems, and the like, but these are not described herein because they are not necessary for understanding aspects of the present technology.

Referring now to FIGS. 2A and 2B , a method for accessing a memory of a DUT is shown according to aspects of the present technology. The method supports odd sector size or non-standard sector size access to the memory of the DUT when an operating system of a host device tester does not support odd sector size and/or non-standard sector size. At 205 , the method may include generating a memory access having an increased memory size based on an odd sector size or non-standard sector size. In one implementation aspect, an application, engine, module, or the like in a user space for a host device tester may generate a memory access that includes one or more memory access commands with a memory buffer for accompanying data. For example, a memory access may include a write command and data to be written to memory in one or more DUTs. When the DUT supports an odd sector size or non-standard sector size, a memory access size used by the write command may be increased based on the odd sector size or non-standard sector size configuration of the DUT. For example, if the write command is for 100 sectors of an attached 52000 byte memory, each sector having a sector size of 520 bytes (bps), the memory buffer size may be increased to 52224 bytes, or 102 512-byte sectors.

At 210, memory accesses may be sent to one or more loading boards by an operating system of a host device tester over a first communication protocol interface. The operating system of the host device of the tester, such as Linux and Windows, does not support odd sector sizes or non-standard sector sizes, and therefore will not service memory access commands for odd sector sizes and/or non-standard sector sizes. However, the operating system will instead send memory accesses with an increased memory access size. In one implementation, the operating system may use a PCIe protocol interface to send memory accesses to the loading boards.

At 215, each of the one or more carrier boards may receive a memory access from the host device tester on a first communication protocol interface. At 220, the one or more carrier boards may communicate the memory access to one or more HBAs coupled to the corresponding one or more carrier boards. At 225, the one or more HBAs may convert the memory access to an odd sector size or non-standard sector size memory access based on a configuration of one or more DUTs coupled to the corresponding one or more HBAs. In one implementation, the one or more HBAs may convert a memory access received on a first communication protocol interface to an odd sector size or non-standard sector size memory access for transmission on a second communication protocol interface. For example, one or more HBAs may convert a memory access received on a PCIe protocol interface into an odd sector size or non-standard sector size memory access for transmission on one or more SAS protocol interfaces. In one implementation, the HBA may be a third-party commodity HBA. A third-party HBA, as used herein, means an HBA manufactured by one or more entities different from one or more entities that manufacture the host device tester and/or the carrier board. At 230, one or more HBAs may send an odd sector size or non-standard sector size memory access to a corresponding DUT using a second communication protocol interface.

At 235, one or more DUTs may receive odd sector size or non-standard sector size memory access from a corresponding HBA. The odd sector size or non-standard sector size memory access may be received by the DUT from the corresponding HBA over a corresponding second communication protocol interface. At 240, the corresponding DUT may perform odd sector size or non-standard sector size memory access. For example, the DUT may write data to a memory configured with an odd sector size or non-standard sector size. For example, the DUT may write 100 sectors of data, each sector being 520 bytes.

At 245, the method may further include sending a memory access result from the DUT back to the corresponding HBA using a second communication protocol interface. For example, the memory access may also include a read command to read back data written to the memory of the DUT. In another example, data writing and reading back may be handled in a single memory access. At 250, the memory access result may be received from the corresponding DUT through the corresponding HBA on the second communication protocol interface. At 255, the corresponding HBA may transmit the memory access result to the corresponding loading board. At 260, the loading board may perform test analysis based on the memory access result and the corresponding memory access. For example, the board can compare the readback data from a memory access result with the corresponding data from the corresponding memory access write to determine any read and/or write errors to the memory of the corresponding DUT.

For a DUT, such as an SSD, where the device access memory buffer can be configured for a plurality of different sector sizes, the process of 205 to 225 can be repeated to test the media of the DUT for each of the configurable sector sizes.

Aspects of the present technology advantageously eliminate the need to develop custom protocols or protocol handling for the mounting board. The operating system of the host device tester advantageously does not need to be aware of or provide any support for odd or non-standard sector sizes.

For purposes of illustration and description, the foregoing description of specific embodiments of the present technology has been introduced. It is not intended to completely encompass or limit the present technology to the precise form disclosed, and in view of the above teachings, many modifications and variations are obviously possible. The embodiments are selected and described in order to best explain the principles of the present technology and its practical application, so that those with ordinary knowledge in the relevant technical field can make the best use of the present technology and various embodiments through various modifications and suitable for the specific purpose contemplated. The scope of the present invention is intended to be defined by the scope of the accompanying patent application and its equivalents.

110: Tester

120: Loading board

130-1,130-m: Host Bus Adapter (HBA)

140-1,140-2,140-n:DUT

150: Processor

160: Operating system

170: User Space Tester Application

Claims (20)

An automatic test equipment (ATE) device comprising: a host device tester; a carrier board communicatively coupled to the host device tester; a host bus adapter communicatively coupled between the carrier board and a device under test; and wherein the carrier board is configured to communicate with the host bus adapter using a first communication protocol interface, the host bus adapter is configured to communicate with the device under test using a second communication protocol interface size, and the host bus adapter is configured to convert commands and data between the first communication protocol interface and the second communication protocol interface to support an odd sector size or a non-standard sector size. The ATE device of claim 1, wherein: the first communication protocol comprises a peripheral component interconnect express (PCIe) protocol; and the second communication protocol comprises a serial attached small computer system interface (SAS) protocol. As claimed in claim 1, the ATE device, wherein the carrier board includes a field programmable gate array (FPGA). ATE apparatus as claimed in claim 1, wherein the device under test is operable to store data using a sector size selected from the group consisting of 520 bytes per sector (BPS), 528 BPS, 4104 BPS, and 4224 BPS. An ATE device as claimed in claim 1, wherein the device under test is operable to allocate an entire sector for a user space application. The ATE device of claim 5, wherein the entire sector has no protection information. An automatic test equipment (ATE) device, comprising: a host bus adapter coupled to a carrier board between a host device tester and one or more devices under test, wherein: the one or more devices under test support an odd sector size or a non-standard sector size; the host device tester executes an operating system that does not support the odd sector size or the non-standard sector size; and the host bus adapter is configured to convert memory accesses from the host device tester into odd sector size or non-standard sector size memory accesses to the one or more devices under test. The ATE device of claim 7, wherein: the host bus adapter is coupled to the host device tester via a first communication protocol interface; and the host bus adapter is coupled to the one or more devices under test via a second communication protocol interface. The ATE device of claim 7, wherein: the first communication protocol interface comprises a peripheral component interconnect express (PCIe) protocol interface; and the second communication protocol interface comprises a serial attached small computer system interface (SAS) protocol interface. The ATE device of claim 8, wherein the host bus adapter is further configured to perform the following actions: receiving the memory accesses from the mounting board on the first communication protocol interface; and sending the odd sector size or non-standard sector size memory accesses on the second communication protocol interface to the one or more devices under test. The ATE device of claim 10, wherein the host bus adapter is further configured to perform the following actions: receiving memory access results from the one or more devices under test on the second communication protocol interface; and transmitting the memory access results to the loading board. As claimed in claim 10, the ATE device, wherein the carrier board includes one or more field programmable gate arrays (FPGAs). As claimed in claim 10, the ATE device, wherein the host bus adapter includes a third-party host bus adapter. A method for accessing memory of one or more devices under test comprises: receiving a memory access from a host device tester on a first communication protocol interface via a loading board, wherein an operating system of the host device tester does not support an odd sector size or a non-standard sector size; transmitting the memory access from the host device tester to a host bus adapter via the loading board ; converting the memory access into an odd sector size or non-standard sector size memory access by the host bus adapter; and sending the odd sector size or non-standard sector size memory access to one or more devices under test on a second communication protocol interface by the host bus adapter, wherein the one or more devices under test support the odd sector size or the non-standard sector size memory access. The method of claim 14 further comprises: generating, by a user space application of the host device test, the memory access having a memory buffer of an increased size based on the odd sector size or the non-standard sector size; and sending, by the operating system of the host device tester, the memory access having the memory buffer of an increased size to the loading board on the first communication protocol interface. The method of claim 14 further comprises: receiving the odd sector size or non-standard sector size memory access request from the host bus adapter on the second communication protocol interface by the one or more devices under test; and performing the odd sector size or non-standard sector size memory access by the one or more devices under test. The method of claim 16 further comprises: sending a memory access result to the host bus adapter on the second communication protocol interface by the one or more devices under test; receiving the memory access result from the one or more devices under test on the second communication protocol interface by the host bus adapter; transmitting the memory access result to the mounting board by the host bus adapter; and performing a test analysis based on a corresponding memory access and the memory access result by the mounting board. The method of claim 14, wherein the first communication protocol interface comprises a peripheral component interconnect express (PCIe) interface. The method of claim 14, wherein the second communication protocol interface comprises a Serial Attached Small Computer System Interface (SAS) protocol interface. The method of claim 10, wherein the odd sector size or non-standard sector size comprises a sector size selected from the group consisting of 520 bytes per sector (BPS), 528 BPS, 4104 BPS, and 4224 BPS.