TWI774645B - Planarization device for TSV structure - Google Patents

Planarization device for TSV structure Download PDF

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TWI774645B
TWI774645B TW105133926A TW105133926A TWI774645B TW I774645 B TWI774645 B TW I774645B TW 105133926 A TW105133926 A TW 105133926A TW 105133926 A TW105133926 A TW 105133926A TW I774645 B TWI774645 B TW I774645B
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wafer
metal layer
layer
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tsv structure
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TW201737417A (en
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金一諾
代迎偉
楊貴璞
王堅
王暉
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大陸商盛美半導體設備（上海）股份有限公司
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    • H—ELECTRICITY
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    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/32115—Planarisation
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    • H01L23/53204—Conductive materials
    • H01L23/53209—Conductive materials based on metals, e.g. alloys, metal silicides
    • H01L23/53228—Conductive materials based on metals, e.g. alloys, metal silicides the principal metal being copper
    • H01L23/53238—Additional layers associated with copper layers, e.g. adhesion, barrier, cladding layers

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Abstract

The present invention discloses a TSV structure planarization process and apparatus. The TSV structure includes a substrate, vias formed in the substrate, an oxide layer formed on the substrate, a barrier layer formed on the oxide layer, bottom and sidewall of the vias, a metal layer formed in the vias and on the barrier layer. In an embodiment, a TSV structure planarization process comprises: removing all metal layer formed on a non-recessed area of the substrate by a stress-free polishing process; and removing metal layer residual and the barrier layer on the non-recessed area by a chemical wet etch process.

Description

TSV結構的平坦化裝置 Planarization device of TSV structure

本發明關於半導體器件製造，尤其關於TSV(矽通孔)結構的平坦化製程和裝置。 The present invention relates to semiconductor device fabrication, and more particularly, to a planarization process and apparatus for TSV (through silicon via) structures.

隨著電子工業的快速發展，對電子產品提出微型、低功耗、高可靠性的要求是必然。基於摩爾定律，積體電路特徵尺寸的減小接近瓶頸。近年來，晶圓級的垂直小型化3D矽通孔(TSV)和2.5D插件封裝集成成為可選擇的解決方案，透過降低設計、製程和成本等突破摩爾定律的瓶頸。相應的，由於銅的高導電性、更好的抗電遷移能力，當製造TSV或插件時，銅被廣泛用於填充通孔。 With the rapid development of the electronic industry, it is inevitable to put forward the requirements of miniature, low power consumption and high reliability for electronic products. Based on Moore's Law, the reduction in feature size of integrated circuits is approaching a bottleneck. In recent years, wafer-level vertical miniaturization of 3D through-silicon vias (TSVs) and 2.5D plug-in package integration has become an alternative solution, breaking through the bottleneck of Moore's Law by reducing design, process and cost. Accordingly, copper is widely used to fill vias when manufacturing TSVs or interposers due to its high conductivity and better resistance to electromigration.

通常，銅金屬層的沈積和平坦化製程包括以下步驟：PVD(物理氣相沈積)、ECP(電鍍)、退火、CMP(化學機械平坦化)。TSV或插件中的通孔通常具有高深寬比，為了無空隙的填充深通孔，厚的銅覆蓋層將透過電鍍製程沈積在晶圓表面。因此，大量的銅層需要透過CMP去除，從而使CMP製程在3D TSV和2.5D插件封裝集成中所占成本最高。例如，在中間通孔製程中，CMP製程佔據了總成本的35%。另一方面，Cu和Si之間CTE(熱膨脹 係數)的不匹配產生應力，表現為晶圓級翹曲。應力進一步誘發矽層的微裂紋、載體的移動變化和器件缺陷。經證實，退火溫度越高、銅覆蓋層越厚將導致晶圓級翹曲越高。在CMP製程中，晶圓將被CMP的研磨頭的下壓力壓平，外部的機械壓力將與晶圓的內部應力衝突，從而導致晶圓裂化或產生缺陷。儘管優化了傳統製程流程並且在退火前銅覆蓋層的厚度達到最小，可以在CMP製程之前成功的消除應力並最小化晶圓翹曲，然而，3D TSV或2.5D插件是否可以快速產業化取決於能否解決降低成本和應力的問題。 Typically, the deposition and planarization process of the copper metal layer includes the following steps: PVD (physical vapor deposition), ECP (electroplating), annealing, CMP (chemical mechanical planarization). Vias in TSVs or interposers typically have high aspect ratios. To fill deep vias without voids, a thick copper capping layer will be deposited on the wafer surface through an electroplating process. Therefore, a large amount of copper layer needs to be removed by CMP, making the CMP process the most expensive in 3D TSV and 2.5D package integration. For example, in the via-in-the-middle process, the CMP process accounts for 35% of the total cost. On the other hand, the CTE (thermal expansion) between Cu and Si A mismatch in coefficients) creates stress that manifests as wafer-level warpage. The stress further induces microcracks in the silicon layer, movement changes of the carrier and device defects. Higher annealing temperatures and thicker copper overlays have been shown to result in higher wafer-level warpage. In the CMP process, the wafer will be flattened by the downward pressure of the CMP grinding head, and the external mechanical pressure will conflict with the internal stress of the wafer, resulting in wafer cracking or defects. Although optimizing the traditional process flow and minimizing the thickness of the copper capping layer before annealing can successfully relieve stress and minimize wafer warpage before the CMP process, however, whether 3D TSV or 2.5D inserts can be rapidly industrialized depends on Can it solve the problem of reducing cost and stress.

在一種具體實施方式中，本發明提出一種TSV結構的平坦化製程。TSV結構包括晶圓、晶圓上的通孔、晶圓上的氧化層、氧化層上及通孔的底部和側壁上的阻擋層、通孔內及阻擋層上的金屬層。TSV結構的平坦化製程包括：採用無應力抛光製程去除晶圓的非凹進區域上的全部金屬層；採用化學濕法蝕刻製程去除非凹進區域上的金屬層殘餘以及阻擋層。 In a specific embodiment, the present invention provides a planarization process for a TSV structure. The TSV structure includes a wafer, a through hole on the wafer, an oxide layer on the wafer, a barrier layer on the oxide layer and on the bottom and sidewalls of the through hole, and a metal layer in the through hole and on the barrier layer. The planarization process of the TSV structure includes: using a stress-free polishing process to remove all metal layers on the non-recessed areas of the wafer; using a chemical wet etching process to remove the metal layer residues and barrier layers on the non-recessed areas.

在另一種具體實施方式中，本發明提出一種TSV結構的平坦化製程。TSV結構包括晶圓、晶圓上的通孔、晶圓上的氧化層、氧化層上及通孔的底部和側壁上的阻擋層、通孔內及阻擋層上的金屬層。TSV結構的平坦化製程包括：採用無應力抛光製程去除晶圓的非凹進區域上 的大部分金屬層，並在非凹進區域上保留一定厚度的金屬層；採用金屬層化學濕法蝕刻製程去除非凹進區域上餘留的金屬層；採用阻擋層化學濕法蝕刻製程去除非凹進區域上的金屬層殘餘和阻擋層。 In another specific embodiment, the present invention provides a planarization process for a TSV structure. The TSV structure includes a wafer, a through hole on the wafer, an oxide layer on the wafer, a barrier layer on the oxide layer and on the bottom and sidewalls of the through hole, and a metal layer in the through hole and on the barrier layer. The planarization process of the TSV structure includes: using a stress-free polishing process to remove the non-recessed areas of the wafer Most of the metal layer, and retain a certain thickness of metal layer on the non-recessed area; use the metal layer chemical wet etching process to remove the remaining metal layer on the non-recessed area; use the barrier layer chemical wet etching process to remove the non-recessed metal layer Metal layer residues and barrier layers on recessed areas.

在另一種具體實施方式中，本發明提出一種TSV結構的平坦化製程。TSV結構包括晶圓、晶圓上的通孔、晶圓上的氧化層、氧化層上及通孔的底部和側壁上的阻擋層、通孔內及阻擋層上的金屬層。TSV結構的平坦化製程包括：採用無應力抛光製程去除晶圓的非凹進區域上的全部金屬層；採用化學機械平坦化製程去除非凹進區域上的金屬層殘餘；採用阻擋層化學濕法蝕刻製程去除非凹進區域上的阻擋層。 In another specific embodiment, the present invention provides a planarization process for a TSV structure. The TSV structure includes a wafer, a through hole on the wafer, an oxide layer on the wafer, a barrier layer on the oxide layer and on the bottom and sidewalls of the through hole, and a metal layer in the through hole and on the barrier layer. The planarization process of the TSV structure includes: using a stress-free polishing process to remove all metal layers on the non-recessed areas of the wafer; using a chemical mechanical planarization process to remove the metal layer residues on the non-recessed areas; using a barrier layer chemical wet method The etching process removes the barrier layer on the non-recessed areas.

在另一種具體實施方式中，本發明提出一種TSV結構的平坦化製程。TSV結構包括晶圓、晶圓上的通孔、晶圓上的氧化層、氧化層上及通孔的底部和側壁上的阻擋層、通孔內及阻擋層上的金屬層。TSV結構的平坦化製程包括：去除晶圓的非凹進區域上的大部分金屬層，並在非凹進區域上保留一定厚度的金屬層；採用化學機械平坦化製程去除非凹進區域上餘留的金屬層；採用阻擋層化學濕法蝕刻製程去除非凹進區域上的金屬層殘餘和阻擋層。 In another specific embodiment, the present invention provides a planarization process for a TSV structure. The TSV structure includes a wafer, a through hole on the wafer, an oxide layer on the wafer, a barrier layer on the oxide layer and on the bottom and sidewalls of the through hole, and a metal layer in the through hole and on the barrier layer. The planarization process of the TSV structure includes: removing most of the metal layer on the non-recessed area of the wafer, and leaving a certain thickness of the metal layer on the non-recessed area; using a chemical mechanical planarization process to remove the remaining metal layer on the non-recessed area The remaining metal layer; the barrier layer chemical wet etching process is used to remove the metal layer residue and the barrier layer on the non-recessed area.

在一種具體實施方式中，本發明提出一種TSV結構的平坦化裝置。TSV結構包括晶圓、晶圓上的通孔、晶圓上的氧化層、氧化層上及通孔的底部和側壁上的阻擋 層、通孔內及阻擋層上的金屬層。TSV結構的平坦化裝置包括至少一個SFP模組、CMP模組和濕法蝕刻模組。SFP模組用於對晶圓進行無應力抛光製程以去除晶圓的非凹進區域上的金屬層。CMP模組用於對晶圓進行化學機械平坦化製程以去除非凹進區域上的金屬層。濕法蝕刻模組用於對晶圓進行化學濕法蝕刻製程以去除非凹進區域上的金屬層和/或阻擋層。 In a specific embodiment, the present invention provides a planarization device of a TSV structure. The TSV structure includes the wafer, vias on the wafer, oxide on the wafer, barriers on the oxide and the bottom and sidewalls of the vias layers, metal layers in vias, and on barrier layers. The planarization device of the TSV structure includes at least one SFP module, a CMP module and a wet etching module. SFP modules are used to perform a stress-free polishing process on wafers to remove metal layers on non-recessed areas of the wafer. The CMP module is used to perform a chemical mechanical planarization process on the wafer to remove the metal layer on the non-recessed areas. The wet etch module is used to perform a chemical wet etch process on wafers to remove metal layers and/or barrier layers on non-recessed areas.

與傳統的使用CMP製程去除非凹進區域上的金屬層和阻擋層的TSV結構的平坦化製程相比，本發明利用無應力抛光製程和化學濕法蝕刻製程實現無應力的去除非凹進區域上的金屬層和阻擋層，只保留通孔內的金屬層和阻擋層，改善了金屬層凹陷的均勻性，減少了平坦化過程中的應力，使晶圓微裂紋的可能性降至最低，並縮短了CMP製程的持續時間，最終降低了平坦化製程的成本以及減少了化學廢液的排放。 Compared with the conventional planarization process of the TSV structure using the CMP process to remove the metal layer and the barrier layer on the non-recessed area, the present invention utilizes the stress-free polishing process and the chemical wet etching process to achieve stress-free removal of the non-recessed area. The metal layer and barrier layer on the top of the plate, only the metal layer and barrier layer in the through hole are retained, which improves the uniformity of the metal layer depression, reduces the stress during the planarization process, and minimizes the possibility of wafer microcracks. And shorten the duration of the CMP process, ultimately reducing the cost of the planarization process and reducing the discharge of chemical waste.

101:晶圓 101: Wafers

102:通孔 102: Through hole

103:氧化層 103: oxide layer

104:阻擋層 104: Barrier

105:金屬層(銅層) 105: Metal layer (copper layer)

1001:EFEM(設備前端模組) 1001: EFEM (Equipment Front End Module)

1003:緩衝位 1003: buffer bit

1005:機械手 1005: Robot

1007:SFP模組 1007:SFP module

1009:CMP模組 1009: CMP Module

1011:量測模組 1011: Measurement module

1013:刷子清洗模組 1013: Brush Cleaning Module

1015:濕法蝕刻模組 1015: Wet Etching Module

1017:清洗模組 1017: Cleaning Module

圖1是TSV結構在實施平坦化製程前的截面圖；圖2是已經平坦化的TSV結構的截面圖；圖3是本發明一種具體實施方式的TSV結構的平坦化製程的流程圖；圖4是本發明另一種具體實施方式的TSV結構的平坦化製程的流程圖； 圖5是本發明另一種具體實施方式的TSV結構的平坦化製程的流程圖；圖6是本發明另一種具體實施方式的TSV結構的平坦化製程的流程圖；圖7是本發明另一種具體實施方式的TSV結構的平坦化製程的流程圖；圖8是本發明另一種具體實施方式的TSV結構的平坦化製程的流程圖；圖9是濕法蝕刻脈衝模式處方的一種具體實施方式；圖10是本發明的TSV結構的平坦化裝置的方塊圖；圖11是一種晶圓傳輸順序的方塊圖；圖12是另一種晶圓傳輸順序的方塊圖。 1 is a cross-sectional view of a TSV structure before a planarization process is implemented; FIG. 2 is a cross-sectional view of a planarized TSV structure; FIG. 3 is a flow chart of the planarization process of the TSV structure according to a specific embodiment of the present invention; FIG. 4 is a flow chart of the planarization process of the TSV structure according to another specific embodiment of the present invention; FIG. 5 is a flow chart of a planarization process of a TSV structure according to another specific embodiment of the present invention; FIG. 6 is a flow chart of a planarization process of a TSV structure according to another specific embodiment of the present invention; FIG. 7 is another specific embodiment of the present invention. The flow chart of the planarization process of the TSV structure according to the embodiment; FIG. 8 is the flow chart of the planarization process of the TSV structure according to another specific embodiment of the present invention; FIG. 9 is a specific embodiment of the wet etching pulse mode prescription; FIG. 10 is a block diagram of the planarization apparatus of the TSV structure of the present invention; FIG. 11 is a block diagram of a wafer transfer sequence; FIG. 12 is a block diagram of another wafer transfer sequence.

形成TSV結構的製程步驟通常包括以下步驟：採用蝕刻在晶圓101上形成通孔102，其中，晶圓101的材料可以選用矽；採用等離子體增強化學氣相沈積(PECVD)在晶圓101上沈積氧化層103，其中，氧化層103的材料可以選用二氧化矽(SiO2)；採用物理氣相沈積(PVD)在氧化層103上及通孔102的底部和側壁沈積阻擋層104，其中，阻擋層104的材料可以選用鈦(Ti)；採用電鍍法在通孔102內沈積金屬層105，其中，金屬層105的材料可以選用銅。 The process steps of forming the TSV structure generally include the following steps: forming through holes 102 on the wafer 101 by etching, wherein the material of the wafer 101 can be selected from silicon; using plasma enhanced chemical vapor deposition (PECVD) on the wafer 101 depositing an oxide layer 103, wherein the material of the oxide layer 103 can be selected from silicon dioxide (SiO 2 ); using physical vapor deposition (PVD) to deposit a barrier layer 104 on the oxide layer 103 and the bottom and sidewalls of the through hole 102, wherein, The material of the barrier layer 104 can be selected from titanium (Ti); the metal layer 105 is deposited in the through hole 102 by an electroplating method, wherein the material of the metal layer 105 can be selected from copper.

由於TSV結構的通孔102通常具有高深寬 比，因此，為了在通孔102內無空隙的沈積金屬層105，採用電鍍法在阻擋層104上沈積厚的金屬覆蓋層105。如圖1所示是在實施平坦化製程前的TSV結構的一種具體實施方式，沈積在非凹進區域上的金屬層105的厚度為2μm-4μm，在通孔102內和非凹進區域上沈積金屬層105後，接下來的步驟是去除沈積在非凹進區域上的金屬層105和阻擋層104。 Due to the TSV structure, the via 102 usually has a high depth and width Therefore, in order to deposit the metal layer 105 without voids in the through hole 102, a thick metal capping layer 105 is deposited on the barrier layer 104 by electroplating. As shown in FIG. 1 , a specific embodiment of the TSV structure before the planarization process is performed, the thickness of the metal layer 105 deposited on the non-recessed area is 2 μm-4 μm, and the thickness of the metal layer 105 in the through hole 102 and on the non-recessed area is 2 μm-4 μm. After depositing the metal layer 105, the next step is to remove the metal layer 105 and barrier layer 104 deposited on the non-recessed areas.

參考圖3所示，圖3是本發明一種具體實施方式的TSV結構的平坦化製程的流程圖，用於去除非凹進區域上的金屬層105和阻擋層104。該TSV結構的平坦化製程包括以下步驟： Referring to FIG. 3 , FIG. 3 is a flow chart of a planarization process of a TSV structure according to an embodiment of the present invention, which is used to remove the metal layer 105 and the barrier layer 104 on the non-recessed area. The planarization process of the TSV structure includes the following steps:

步驟301：採用無應力抛光製程(SFP)去除非凹進區域上的全部金屬層105。採用SFP過抛光控制通孔102內的金屬層凹陷。SFP製程為電化學製程，晶圓101上的金屬層105作為陽極，電解液噴頭作為陰極。當陽極和陰極之間施加正電壓時，金屬層105被接觸的電解液溶解、抛光。SFP製程更詳細的描述參見美國專利申請號10/590,460，標題為“Controlling removal rate uniformity of an electropolishing process in integrated circuit fabrication”的專利，申請日為2005年2月23日，這件專利的全部內容都被引用到這裏。 Step 301 : Use a stress-free polishing process (SFP) to remove all the metal layers 105 on the non-recessed areas. SFP over-polishing is used to control the recess of the metal layer in the through hole 102 . The SFP process is an electrochemical process, the metal layer 105 on the wafer 101 is used as the anode, and the electrolyte nozzle is used as the cathode. When a positive voltage is applied between the anode and the cathode, the metal layer 105 is dissolved and polished by the contacting electrolyte. A more detailed description of the SFP process can be found in U.S. Patent Application No. 10/590,460, entitled "Controlling removal rate uniformity of an electropolishing process in integrated circuit fabrication", filed on February 23, 2005, the entire content of this patent are all cited here.

步驟303：採用金屬層化學濕法蝕刻製程去除非凹進區域上的金屬層殘餘。SFP製程完成後，非凹進區域上的阻擋層104上可能殘留一些金屬層，為了去除非凹 進區域上的阻擋層104上殘留的金屬層，使用金屬層化學濕法蝕刻製程去除金屬層殘餘。金屬層105的材料較佳者為銅，相應的，用於去除銅殘餘的蝕刻劑主要包括雙氧水(H2O2)、添加劑和氫氟酸，氫氟酸的濃度在2%-10%。在濕法蝕刻製程中，蝕刻劑在脈衝模式下被噴到晶圓表面，如圖9所示。一個脈衝模式步驟包括一步蝕刻劑步驟和一步DIW步驟，例如，首先對晶圓進行10秒鐘的化學濕法蝕刻，然後，對晶圓進行5秒鐘的去離子水處理。多個周期性的步驟形成濕法蝕刻製程處方。周期性的濕法蝕刻製程優化了凹進區域的銅凹陷，DIW將會填滿凹進區域並降低該區域的蝕刻速率。晶圓固定在卡盤上並與卡盤一起轉動，有利於濕法蝕刻製程的晶圓轉速為200RPM-600RPM。不同半徑上蝕刻率與轉速有關，轉速越高導致晶圓邊緣去除率越高、晶圓中心去除率越低，相反的，轉速越低導致晶圓邊緣去除率越低、晶圓中心去除率越高。此外，蝕刻劑噴頭在製程過程中是可移動的，蝕刻率受噴頭的掃描速度和掃描區域位置的影響，最佳的掃描速度為40mm/sec-100mm/sec。 Step 303: Use a metal layer chemical wet etching process to remove the metal layer residue on the non-recessed area. After the SFP process is completed, some metal layer may remain on the barrier layer 104 on the non-recessed area. In order to remove the metal layer remaining on the barrier layer 104 on the non-recessed area, the metal layer chemical wet etching process is used to remove the metal layer residue. . The material of the metal layer 105 is preferably copper. Correspondingly, the etchant for removing copper residues mainly includes hydrogen peroxide (H 2 O 2 ), additives and hydrofluoric acid, and the concentration of hydrofluoric acid is 2%-10%. In the wet etch process, the etchant is sprayed onto the wafer surface in a pulsed mode, as shown in Figure 9. A pulsed mode step consists of an etchant step and a DIW step, eg, a 10-second chemical wet etch on the wafer, followed by a 5-second deionized water treatment on the wafer. A number of periodic steps form the wet etch process recipe. The periodic wet etch process optimizes the copper recess in the recessed area, DIW will fill the recessed area and reduce the etch rate in this area. The wafer is fixed on the chuck and rotates together with the chuck, and the wafer rotation speed for the wet etching process is 200RPM-600RPM. The etching rate on different radii is related to the rotation speed. The higher the rotation speed, the higher the wafer edge removal rate and the lower the wafer center removal rate. On the contrary, the lower the rotation speed, the lower the wafer edge removal rate and the lower the wafer center removal rate. high. In addition, the etchant nozzle is movable during the process, and the etching rate is affected by the scanning speed of the nozzle and the position of the scanning area. The optimal scanning speed is 40mm/sec-100mm/sec.

步驟305：採用阻擋層化學濕法蝕刻製程去除非凹進區域上的阻擋層104。非凹進區域上的阻擋層104的厚度為0.2μm-0.5μm，非凹進區域上的阻擋層104的厚度取決於製程需求。阻擋層104的材料包含鈦，相應的，用於阻擋層化學濕法蝕刻製程的化學液主要包括氫氟酸(HF)和添加劑，氫氟酸的濃度為0.1%-1%。與銅濕法蝕 刻製程相似，在阻擋層濕法蝕刻製程中，蝕刻劑在脈衝模式下被噴到晶圓表面，如圖9所示。一個脈衝模式步驟包括一步蝕刻劑步驟和一步DIW步驟，例如，首先對晶圓進行10秒鐘的化學濕法蝕刻，然後，對晶圓進行5秒鐘的去離子水處理。多個周期性的步驟形成濕法蝕刻製程處方。周期性的濕法蝕刻製程優化了凹進區域側壁上的阻擋層過刻。DIW將會填滿凹進區域並降低該區域的蝕刻速率。晶圓固定在卡盤上並與卡盤一起轉動，有利於濕法蝕刻製程的晶圓轉速為200RPM-600RPM。不同半徑上蝕刻率與轉速有關，轉速越高導致晶圓邊緣去除率越高、晶圓中心去除率越低，相反的，轉速越低導致晶圓邊緣去除率越低、晶圓中心去除率越高。此外，蝕刻劑噴頭在製程過程中是可移動的，蝕刻率受噴頭的掃描速度和掃描區域位置的影響，最佳的掃描速度為40mm/sec-100mm/sec。 Step 305 : remove the barrier layer 104 on the non-recessed area by using a barrier layer chemical wet etching process. The thickness of the barrier layer 104 on the non-recessed area is 0.2 μm -0.5 μm , and the thickness of the barrier layer 104 on the non-recessed area depends on process requirements. The material of the barrier layer 104 includes titanium. Correspondingly, the chemical solution used for the chemical wet etching process of the barrier layer mainly includes hydrofluoric acid (HF) and additives, and the concentration of the hydrofluoric acid is 0.1%-1%. Similar to the copper wet etch process, in the barrier wet etch process, the etchant is sprayed onto the wafer surface in a pulsed mode, as shown in Figure 9. A pulsed mode step consists of an etchant step and a DIW step, eg, a 10-second chemical wet etch on the wafer, followed by a 5-second deionized water treatment on the wafer. A number of periodic steps form the wet etch process recipe. The periodic wet etch process optimizes barrier overetching on the sidewalls of the recessed regions. DIW will fill up the recessed area and reduce the etch rate in that area. The wafer is fixed on the chuck and rotates together with the chuck, and the wafer rotation speed for the wet etching process is 200RPM-600RPM. The etching rate on different radii is related to the rotation speed. The higher the rotation speed, the higher the wafer edge removal rate and the lower the wafer center removal rate. On the contrary, the lower the rotation speed, the lower the wafer edge removal rate and the lower the wafer center removal rate. high. In addition, the etchant nozzle is movable during the process, and the etching rate is affected by the scanning speed of the nozzle and the position of the scanning area. The optimal scanning speed is 40mm/sec-100mm/sec.

採用阻擋層化學濕法蝕刻製程去除非凹進區域上的阻擋層104後，阻擋層104下方的氧化層103暴露出來，氧化層103的材料為SiO2，氧化層103的厚度大約為2μm。為了得到平坦的上表面，應用CMP製程去除一部分的氧化層103。通常，去除的氧化層103厚度為0.2μm。CMP製程在氧化層103和銅層105之間具有高選擇比，比如100：1。CMP製程可以修復通孔102內銅層105的粗糙度。 After the barrier layer 104 on the non-recessed area is removed by the barrier layer chemical wet etching process, the oxide layer 103 under the barrier layer 104 is exposed. The material of the oxide layer 103 is SiO2, and the thickness of the oxide layer 103 is about 2 μm . In order to obtain a flat upper surface, a part of the oxide layer 103 is removed by a CMP process. Typically, the thickness of the removed oxide layer 103 is 0.2 μm . The CMP process has a high selectivity ratio between oxide layer 103 and copper layer 105, such as 100:1. The CMP process can repair the roughness of the copper layer 105 in the via hole 102 .

參考圖4所示，圖4是本發明另一種具體實施方式的TSV結構的平坦化製程的流程圖，用於去除非凹進 區域上的金屬層105和阻擋層104。該TSV結構的平坦化製程包括以下步驟： Referring to FIG. 4, FIG. 4 is a flow chart of a planarization process of a TSV structure according to another specific embodiment of the present invention, for removing non-recesses Metal layer 105 and barrier layer 104 on the area. The planarization process of the TSV structure includes the following steps:

步驟401：採用無應力抛光製程(SFP)去除非凹進區域上的全部金屬層105。採用SFP過抛光控制通孔102內的金屬層凹陷。SFP製程為電化學製程，晶圓101上的金屬層105作為陽極，電解液噴頭作為陰極。當陽極和陰極之間施加正電壓時，金屬層105被接觸的電解液溶解、抛光。SFP製程更詳細的描述參見美國專利申請號10/590,460，標題為“Controlling removal rate uniformity of an electropolishing process in integrated circuit fabrication”的專利，申請日為2005年2月23日，這件專利的全部內容都被引用到這裏。 Step 401 : Use a stress-free polishing process (SFP) to remove all the metal layers 105 on the non-recessed areas. SFP over-polishing is used to control the recess of the metal layer in the through hole 102 . The SFP process is an electrochemical process, the metal layer 105 on the wafer 101 is used as the anode, and the electrolyte nozzle is used as the cathode. When a positive voltage is applied between the anode and the cathode, the metal layer 105 is dissolved and polished by the contacting electrolyte. A more detailed description of the SFP process can be found in U.S. Patent Application No. 10/590,460, entitled "Controlling removal rate uniformity of an electropolishing process in integrated circuit fabrication", filed on February 23, 2005, the entire content of this patent are all cited here.

步驟403：採用阻擋層化學濕法蝕刻製程去除非凹進區域上的金屬層殘餘和阻擋層104。在一種具體實施方式中，金屬層105的材料是銅，阻擋層104的材料包括鈦。用於阻擋層化學濕法蝕刻製程的化學品主要包括氫氟酸(HF)和添加劑，氫氟酸的濃度為0.1%-1%。在阻擋層濕法蝕刻製程中，蝕刻劑在脈衝模式下被噴到晶圓表面，如圖9所示。一個脈衝模式步驟包括一步蝕刻劑步驟和一步DIW步驟，例如，首先對晶圓進行10秒鐘的化學濕法蝕刻，然後，對晶圓進行5秒鐘的去離子水處理。多個周期性的步驟形成濕法蝕刻製程處方。周期性的濕法蝕刻製程優化了凹進區域側壁上的阻擋層過刻。DIW將會填滿凹進區域並降低該區域的蝕刻速率。晶圓固定在卡盤上 並與卡盤一起轉動，有利於濕法蝕刻製程的晶圓轉速為200RPM-600RPM。不同半徑上蝕刻率與轉速有關，轉速越高導致晶圓邊緣去除率越高、晶圓中心去除率越低，相反的，轉速越低導致晶圓邊緣去除率越低、晶圓中心去除率越高。此外，蝕刻劑噴頭在製程過程中是可移動的，蝕刻率受噴頭的掃描速度和掃描區域位置的影響，最佳的掃描速度為40mm/sec-100mm/sec。 Step 403 : Remove the metal layer residue and the barrier layer 104 on the non-recessed regions by using a barrier layer chemical wet etching process. In a specific embodiment, the material of the metal layer 105 is copper, and the material of the barrier layer 104 includes titanium. The chemicals used in the chemical wet etching process of the barrier layer mainly include hydrofluoric acid (HF) and additives, and the concentration of hydrofluoric acid is 0.1%-1%. In the barrier wet etch process, the etchant is sprayed onto the wafer surface in a pulsed mode, as shown in Figure 9. A pulsed mode step consists of an etchant step and a DIW step, eg, a 10-second chemical wet etch on the wafer, followed by a 5-second deionized water treatment on the wafer. A number of periodic steps form the wet etch process recipe. The periodic wet etch process optimizes barrier overetching on the sidewalls of the recessed regions. DIW will fill up the recessed area and reduce the etch rate in that area. Wafer is fixed on the chuck And rotate together with the chuck, the wafer speed that is conducive to the wet etching process is 200RPM-600RPM. The etching rate on different radii is related to the rotation speed. The higher the rotation speed, the higher the wafer edge removal rate and the lower the wafer center removal rate. On the contrary, the lower the rotation speed, the lower the wafer edge removal rate and the lower the wafer center removal rate. high. In addition, the etchant nozzle is movable during the process, and the etching rate is affected by the scanning speed of the nozzle and the position of the scanning area. The optimal scanning speed is 40mm/sec-100mm/sec.

採用阻擋層化學濕法蝕刻製程去除非凹進區域上的金屬層殘餘和阻擋層104後，阻擋層104下方的氧化層103暴露出來，氧化層103的材料為SiO2，氧化層103的厚度大約為2μm。為了得到平坦的上表面，應用CMP製程去除一部分的氧化層103。通常，去除的氧化層103厚度為0.2μm。CMP製程在氧化層103和銅層105之間具有高選擇比，比如100：1。CMP製程可以修復通孔102內銅層105的粗糙度。 After the metal layer residue on the non-recessed area and the barrier layer 104 are removed by the chemical wet etching process of the barrier layer, the oxide layer 103 under the barrier layer 104 is exposed. The material of the oxide layer 103 is SiO 2 , and the thickness of the oxide layer 103 is about is 2 μm . In order to obtain a flat upper surface, a part of the oxide layer 103 is removed by a CMP process. Typically, the thickness of the removed oxide layer 103 is 0.2 μm . The CMP process has a high selectivity ratio between oxide layer 103 and copper layer 105, such as 100:1. The CMP process can repair the roughness of the copper layer 105 in the via hole 102 .

參考圖5所示，圖5是本發明另一種具體實施方式的TSV結構的平坦化製程的流程圖，用於去除非凹進區域上的金屬層105和阻擋層104。該TSV結構的平坦化製程包括以下步驟： Referring to FIG. 5 , FIG. 5 is a flowchart of a planarization process of a TSV structure according to another embodiment of the present invention, which is used to remove the metal layer 105 and the barrier layer 104 on the non-recessed regions. The planarization process of the TSV structure includes the following steps:

步驟501：採用無應力抛光製程去除非凹進區域上的大部分金屬層105，並在非凹進區域上餘留大約0.2μm-0.5μm的金屬層105。SFP製程為電化學製程，晶圓101上的金屬層105作為陽極，電解液噴頭作為陰極。當陽極和陰極之間施加正電壓時，金屬層105被接觸的電解 液溶解、抛光。SFP製程更詳細的描述參見美國專利申請號10/590,460，標題為“Controlling removal rate uniformity of an electropolishing process in integrated circuit fabrication”的專利，申請日為2005年2月23日，這件專利的全部內容都被引用到這裏。 Step 501 : use a stress-free polishing process to remove most of the metal layer 105 on the non-recessed area, and leave the metal layer 105 on the non-recessed area with a thickness of about 0.2 μm -0.5 μm . The SFP process is an electrochemical process, the metal layer 105 on the wafer 101 is used as the anode, and the electrolyte nozzle is used as the cathode. When a positive voltage is applied between the anode and the cathode, the metal layer 105 is dissolved and polished by the contacting electrolyte. A more detailed description of the SFP process can be found in U.S. Patent Application No. 10/590,460, entitled "Controlling removal rate uniformity of an electropolishing process in integrated circuit fabrication", filed on February 23, 2005, the entire content of this patent are all cited here.

步驟503：採用金屬層化學濕法蝕刻製程去除非凹進區域上餘留的金屬層105。透過金屬層化學濕法蝕刻製程的過刻時間長度控制通孔102內的金屬層凹陷。金屬層105的材料為銅，用於銅金屬層化學濕法蝕刻製程的化學品主要包括雙氧水(H2O2)、添加劑和氫氟酸，氫氟酸的濃度在2%-10%。在濕法蝕刻製程中，蝕刻劑在脈衝模式下被噴到晶圓表面，如圖9所示。一個脈衝模式步驟包括一步蝕刻劑步驟和一步DIW步驟，例如，首先對晶圓進行10秒鐘的化學濕法蝕刻，然後，對晶圓進行5秒鐘的去離子水處理。多個周期性的步驟形成濕法蝕刻製程處方。周期性的濕法蝕刻製程優化了凹進區域內的銅凹陷。DIW將會填滿凹進區域並降低該區域的蝕刻速率。晶圓固定在卡盤上並與卡盤一起轉動，有利於濕法蝕刻製程的晶圓轉速為200RPM-600RPM。不同半徑上蝕刻率與轉速有關，轉速越高導致晶圓邊緣去除率越高、晶圓中心去除率越低，相反的，轉速越低導致晶圓邊緣去除率越低、晶圓中心去除率越高。此外，蝕刻劑噴頭在製程過程中是可移動的，蝕刻率受噴頭的掃描速度和掃描區域位置的影響，最佳的掃描速度為40mm/sec-100mm/sec。 Step 503: Use a metal layer chemical wet etching process to remove the metal layer 105 remaining on the non-recessed area. The metal layer recess in the through hole 102 is controlled by the length of the overetching time of the metal layer chemical wet etching process. The material of the metal layer 105 is copper, and the chemicals used in the chemical wet etching process of the copper metal layer mainly include hydrogen peroxide (H 2 O 2 ), additives and hydrofluoric acid, and the concentration of hydrofluoric acid is 2%-10%. In the wet etch process, the etchant is sprayed onto the wafer surface in a pulsed mode, as shown in Figure 9. A pulsed mode step consists of an etchant step and a DIW step, eg, a 10-second chemical wet etch on the wafer, followed by a 5-second deionized water treatment on the wafer. A number of periodic steps form the wet etch process recipe. The periodic wet etch process optimizes the copper recess in the recessed area. DIW will fill up the recessed area and reduce the etch rate in that area. The wafer is fixed on the chuck and rotates together with the chuck, and the wafer rotation speed for the wet etching process is 200RPM-600RPM. The etching rate on different radii is related to the rotation speed. The higher the rotation speed, the higher the wafer edge removal rate and the lower the wafer center removal rate. On the contrary, the lower the rotation speed, the lower the wafer edge removal rate and the lower the wafer center removal rate. high. In addition, the etchant nozzle is movable during the process, and the etching rate is affected by the scanning speed of the nozzle and the position of the scanning area. The optimal scanning speed is 40mm/sec-100mm/sec.

步驟505：採用阻擋層化學濕法蝕刻製程去除非凹進區域上的金屬層殘餘和阻擋層104。阻擋層104的材料包括鈦，用於阻擋層化學濕法蝕刻製程的化學品主要包括氫氟酸(HF)和添加劑，氫氟酸的濃度為0.1%-1%。在阻擋層濕法蝕刻製程中，蝕刻劑在脈衝模式下被噴到晶圓表面，如圖9所示。一個脈衝模式步驟包括一步蝕刻劑步驟和一步DIW步驟，例如，首先對晶圓進行10秒鐘的化學濕法蝕刻，然後，對晶圓進行5秒鐘的去離子水處理。多個周期性的步驟形成濕法蝕刻製程處方。周期性的濕法蝕刻製程優化了凹進區域側壁上的阻擋層過刻。DIW將會填滿凹進區域並降低該區域的蝕刻速率。晶圓固定在卡盤上並與卡盤一起轉動，有利於濕法蝕刻製程的晶圓轉速為200RPM-600RPM。不同半徑上蝕刻率與轉速有關，轉速越高導致晶圓邊緣去除率越高、晶圓中心去除率越低，相反的，轉速越低導致晶圓邊緣去除率越低、晶圓中心去除率越高。此外，蝕刻劑噴頭在製程過程中是可移動的，蝕刻率受噴頭的掃描速度和掃描區域位置的影響，最佳的掃描速度為40mm/sec-100mm/sec。 Step 505 : Remove the metal layer residue and the barrier layer 104 on the non-recessed regions by using a barrier layer chemical wet etching process. The material of the barrier layer 104 includes titanium, and the chemicals used in the chemical wet etching process of the barrier layer mainly include hydrofluoric acid (HF) and additives, and the concentration of the hydrofluoric acid is 0.1%-1%. In the barrier wet etch process, the etchant is sprayed onto the wafer surface in a pulsed mode, as shown in Figure 9. A pulsed mode step consists of an etchant step and a DIW step, eg, a 10-second chemical wet etch on the wafer, followed by a 5-second deionized water treatment on the wafer. A number of periodic steps form the wet etch process recipe. The periodic wet etch process optimizes barrier overetching on the sidewalls of the recessed regions. DIW will fill up the recessed area and reduce the etch rate in that area. The wafer is fixed on the chuck and rotates together with the chuck, and the wafer rotation speed for the wet etching process is 200RPM-600RPM. The etching rate on different radii is related to the rotation speed. The higher the rotation speed, the higher the wafer edge removal rate and the lower the wafer center removal rate. On the contrary, the lower the rotation speed, the lower the wafer edge removal rate and the lower the wafer center removal rate. high. In addition, the etchant nozzle is movable during the process, and the etching rate is affected by the scanning speed of the nozzle and the position of the scanning area. The optimal scanning speed is 40mm/sec-100mm/sec.

採用阻擋層化學濕法蝕刻製程去除非凹進區域上的金屬層殘餘和阻擋層104後，阻擋層104下方的氧化層103暴露出來，氧化層103的材料為SiO2，氧化層103的厚度大約為2μm。為了得到平坦的上表面，較佳的，應用CMP製程去除一部分的氧化層103。通常，去除的氧化層103厚度為0.2μm。CMP製程在氧化層103和銅層 105之間具有高選擇比，比如100：1。CMP製程可以修復通孔102內銅層105的粗糙度。 After the metal layer residue on the non-recessed area and the barrier layer 104 are removed by the chemical wet etching process of the barrier layer, the oxide layer 103 under the barrier layer 104 is exposed. The material of the oxide layer 103 is SiO 2 , and the thickness of the oxide layer 103 is about is 2 μm . In order to obtain a flat upper surface, preferably, a CMP process is used to remove a part of the oxide layer 103 . Typically, the thickness of the removed oxide layer 103 is 0.2 μm . The CMP process has a high selectivity ratio between oxide layer 103 and copper layer 105, such as 100:1. The CMP process can repair the roughness of the copper layer 105 in the via hole 102 .

參考圖6所示，圖6是本發明另一種具體實施方式的TSV結構的平坦化製程的流程圖，用於去除非凹進區域上的金屬層105和阻擋層104。該TSV結構的平坦化製程包括以下步驟： Referring to FIG. 6 , FIG. 6 is a flowchart of a planarization process of a TSV structure according to another embodiment of the present invention, which is used to remove the metal layer 105 and the barrier layer 104 on the non-recessed regions. The planarization process of the TSV structure includes the following steps:

步驟601：採用無應力抛光製程(SFP)去除非凹進區域上的全部金屬層105。採用SFP過抛光控制通孔102內的金屬層凹陷。SFP製程為電化學製程，晶圓101上的金屬層105作為陽極，電解液噴頭作為陰極。當陽極和陰極之間施加正電壓時，金屬層105被接觸的電解液溶解、抛光。SFP製程更詳細的描述參見美國專利申請號10/590,460，標題為“Controlling removal rate uniformity of an electropolishing process in integrated circuit fabrication”的專利，申請日為2005年2月23日，這件專利的全部內容都被引用到這裏。 Step 601 : Use a stress-free polishing process (SFP) to remove all the metal layers 105 on the non-recessed areas. SFP over-polishing is used to control the recess of the metal layer in the through hole 102 . The SFP process is an electrochemical process, the metal layer 105 on the wafer 101 is used as the anode, and the electrolyte nozzle is used as the cathode. When a positive voltage is applied between the anode and the cathode, the metal layer 105 is dissolved and polished by the contacting electrolyte. A more detailed description of the SFP process can be found in U.S. Patent Application No. 10/590,460, entitled "Controlling removal rate uniformity of an electropolishing process in integrated circuit fabrication", filed on February 23, 2005, the entire content of this patent are all cited here.

步驟603：採用化學機械平坦化(CMP)製程去除非凹進區域上的金屬層殘餘。SFP製程完成後，非凹進區域上的阻擋層104上可能還殘留了一些金屬層。為了去除金屬層殘餘，向晶圓101應用化學機械平坦化製程去除金屬層殘餘。由於採用SFP製程幾乎去除了非凹進區域上全部的金屬層，因此CMP製程的製程時間非常短，節約了成本的同時避免了對晶圓的損傷。 Step 603: Use a chemical mechanical planarization (CMP) process to remove metal layer residues on the non-recessed regions. After the SFP process is completed, some metal layers may remain on the barrier layer 104 on the non-recessed area. To remove the metal layer residues, a chemical mechanical planarization process is applied to the wafer 101 to remove the metal layer residues. Since the SFP process is used to remove almost all the metal layers on the non-recessed areas, the process time of the CMP process is very short, which saves costs and avoids damage to the wafer.

步驟605：採用阻擋層化學濕法蝕刻製程去除 非凹進區域上的阻擋層104。非凹進區域上的阻擋層104的厚度為0.2μm-0.5μm，非凹進區域上的阻擋層104的厚度取決於製程需求。阻擋層104的材料包含鈦，相應的，用於阻擋層化學濕法蝕刻製程的化學品主要包括氫氟酸(HF)和添加劑，氫氟酸的濃度為0.1%-1%。在阻擋層濕法蝕刻製程中，蝕刻劑在脈衝模式下被噴到晶圓表面，如圖9所示。一個脈衝模式步驟包括一步蝕刻劑步驟和一步DIW步驟，例如，首先對晶圓進行10秒鐘的化學濕法蝕刻，然後，對晶圓進行5秒鐘的去離子水處理。多個周期性的步驟形成濕法蝕刻製程處方。周期性的濕法蝕刻製程優化了凹進區域側壁上的阻擋層過刻。DIW將會填滿凹進區域並降低該區域的蝕刻速率。晶圓固定在卡盤上並與卡盤一起轉動，有利於濕法蝕刻製程的晶圓轉速為200RPM-600RPM。不同半徑上蝕刻率與轉速有關，轉速越高導致晶圓邊緣去除率越高、晶圓中心去除率越低，相反的，轉速越低導致晶圓邊緣去除率越低、晶圓中心去除率越高。此外，蝕刻劑噴頭在製程過程中是可移動的，蝕刻率受噴頭的掃描速度和掃描區域位置的影響，最佳的掃描速度為40mm/sec-100mm/sec。 Step 605 : Remove the barrier layer 104 on the non-recessed area by using a barrier layer chemical wet etching process. The thickness of the barrier layer 104 on the non-recessed area is 0.2 μm -0.5 μm , and the thickness of the barrier layer 104 on the non-recessed area depends on process requirements. The material of the barrier layer 104 includes titanium. Correspondingly, the chemicals used in the chemical wet etching process of the barrier layer mainly include hydrofluoric acid (HF) and additives, and the concentration of the hydrofluoric acid is 0.1%-1%. In the barrier wet etch process, the etchant is sprayed onto the wafer surface in a pulsed mode, as shown in Figure 9. A pulsed mode step consists of an etchant step and a DIW step, eg, a 10-second chemical wet etch on the wafer, followed by a 5-second deionized water treatment on the wafer. A number of periodic steps form the wet etch process recipe. The periodic wet etch process optimizes barrier overetching on the sidewalls of the recessed regions. DIW will fill up the recessed area and reduce the etch rate in that area. The wafer is fixed on the chuck and rotates together with the chuck, and the wafer rotation speed for the wet etching process is 200RPM-600RPM. The etching rate on different radii is related to the rotation speed. The higher the rotation speed, the higher the wafer edge removal rate and the lower the wafer center removal rate. On the contrary, the lower the rotation speed, the lower the wafer edge removal rate and the lower the wafer center removal rate. high. In addition, the etchant nozzle is movable during the process, and the etching rate is affected by the scanning speed of the nozzle and the position of the scanning area. The optimal scanning speed is 40mm/sec-100mm/sec.

採用阻擋層化學濕法蝕刻製程去除非凹進區域上的阻擋層104後，阻擋層104下方的氧化層103暴露出來，氧化層103的材料為SiO2，氧化層103的厚度大約為2μm。為了得到平坦的上表面，較佳的，應用CMP製程去除一部分的氧化層103。通常，去除的氧化層103厚 度為0.2μm。CMP製程在氧化層103和銅層105之間具有高選擇比，比如100：1。CMP製程可以修復通孔102內銅層105的粗糙度。 After the barrier layer 104 on the non-recessed area is removed by the barrier layer chemical wet etching process, the oxide layer 103 under the barrier layer 104 is exposed. The material of the oxide layer 103 is SiO 2 , and the thickness of the oxide layer 103 is about 2 μm . . In order to obtain a flat upper surface, preferably, a CMP process is used to remove a part of the oxide layer 103 . Typically, the thickness of the removed oxide layer 103 is 0.2 μm . The CMP process has a high selectivity ratio between oxide layer 103 and copper layer 105, such as 100:1. The CMP process can repair the roughness of the copper layer 105 in the via hole 102 .

參考圖7所示，圖7是本發明另一種具體實施方式的TSV結構的平坦化製程的流程圖，用於去除非凹進區域上的金屬層105和阻擋層104。該TSV結構的平坦化製程包括以下步驟： Referring to FIG. 7 , FIG. 7 is a flow chart of a planarization process of a TSV structure according to another embodiment of the present invention, which is used to remove the metal layer 105 and the barrier layer 104 on the non-recessed regions. The planarization process of the TSV structure includes the following steps:

步驟701：採用無應力抛光製程去除非凹進區域上的大部分金屬層105，並在非凹進區域上餘留大約0.2μm-0.5μm的金屬層105。SFP製程為電化學製程，晶圓101上的金屬層105作為陽極，電解液噴頭作為陰極。當陽極和陰極之間施加正電壓時，金屬層105被接觸的電解液溶解、抛光。SFP製程更詳細的描述參見美國專利申請號10/590,460，標題為“Controlling removal rate uniformity of an electropolishing process in integrated circuit fabrication”的專利，申請日為2005年2月23日，這件專利的全部內容都被引用到這裏。 Step 701 : use a stress-free polishing process to remove most of the metal layer 105 on the non-recessed area, and leave the metal layer 105 on the non-recessed area with a thickness of about 0.2 μm -0.5 μm . The SFP process is an electrochemical process, the metal layer 105 on the wafer 101 is used as the anode, and the electrolyte nozzle is used as the cathode. When a positive voltage is applied between the anode and the cathode, the metal layer 105 is dissolved and polished by the contacting electrolyte. A more detailed description of the SFP process can be found in U.S. Patent Application No. 10/590,460, entitled "Controlling removal rate uniformity of an electropolishing process in integrated circuit fabrication", filed on February 23, 2005, the entire content of this patent are all cited here.

步驟703：採用化學機械平坦化製程去除非凹進區域上餘留的金屬層105。透過化學機械平坦化製程的過刻時間長度控制通孔102內的金屬層凹陷。金屬層105的材料為銅。 Step 703: Use a chemical mechanical planarization process to remove the remaining metal layer 105 on the non-recessed areas. The metal layer recess in the via 102 is controlled by the length of the overetching time of the chemical mechanical planarization process. The material of the metal layer 105 is copper.

步驟705：採用阻擋層化學濕法蝕刻製程去除非凹進區域上的金屬層殘餘和阻擋層104。阻擋層104的材料包括鈦，用於阻擋層化學濕法蝕刻製程的化學品主要 包括氫氟酸(HF)和添加劑，氫氟酸的濃度為0.1%-1%。在阻擋層濕法蝕刻製程中，蝕刻劑在脈衝模式下被噴到晶圓表面，如圖9所示。一個脈衝模式步驟包括一步蝕刻劑步驟和一步DIW步驟，例如，首先對晶圓進行10秒鐘的化學濕法蝕刻，然後，對晶圓進行5秒鐘的去離子水處理。多個周期性的步驟形成濕法蝕刻製程處方。周期性的濕法蝕刻製程優化了凹進區域側壁上的阻擋層過刻。DIW將會填滿凹進區域並降低該區域的蝕刻速率。晶圓固定在卡盤上並與卡盤一起轉動，有利於濕法蝕刻製程的晶圓轉速為200RPM-600RPM。不同半徑上蝕刻率與轉速有關，轉速越高導致晶圓邊緣去除率越高、晶圓中心去除率越低，相反的，轉速越低導致晶圓邊緣去除率越低、晶圓中心去除率越高。此外，蝕刻劑噴頭在製程過程中是可移動的，蝕刻率受噴頭的掃描速度和掃描區域位置的影響，最佳的掃描速度為40mm/sec-100mm/sec。 Step 705 : Remove the metal layer residue and the barrier layer 104 on the non-recessed regions by using a barrier layer chemical wet etching process. The material of the barrier layer 104 includes titanium, and the chemical used in the chemical wet etching process of the barrier layer is mainly Including hydrofluoric acid (HF) and additives, the concentration of hydrofluoric acid is 0.1%-1%. In the barrier wet etch process, the etchant is sprayed onto the wafer surface in a pulsed mode, as shown in Figure 9. A pulsed mode step consists of an etchant step and a DIW step, eg, a 10-second chemical wet etch on the wafer, followed by a 5-second deionized water treatment on the wafer. A number of periodic steps form the wet etch process recipe. The periodic wet etch process optimizes barrier overetching on the sidewalls of the recessed regions. DIW will fill up the recessed area and reduce the etch rate in that area. The wafer is fixed on the chuck and rotates together with the chuck, and the wafer rotation speed for the wet etching process is 200RPM-600RPM. The etching rate on different radii is related to the rotation speed. The higher the rotation speed, the higher the wafer edge removal rate and the lower the wafer center removal rate. On the contrary, the lower the rotation speed, the lower the wafer edge removal rate and the lower the wafer center removal rate. high. In addition, the etchant nozzle is movable during the process, and the etching rate is affected by the scanning speed of the nozzle and the position of the scanning area. The optimal scanning speed is 40mm/sec-100mm/sec.

採用阻擋層化學濕法蝕刻製程去除非凹進區域上的金屬層殘餘和阻擋層104後，阻擋層104下方的氧化層103暴露出來，氧化層103的材料為SiO2，氧化層103的厚度大約為2μm。為了得到平坦的上表面，較佳的，應用CMP製程去除一部分的氧化層103。通常，去除的氧化層103厚度為0.2μm。CMP製程在氧化層103和銅層105之間具有高選擇比，比如100：1。CMP製程可以修復通孔102內銅層105的粗糙度。 After the metal layer residue on the non-recessed area and the barrier layer 104 are removed by the chemical wet etching process of the barrier layer, the oxide layer 103 under the barrier layer 104 is exposed. The material of the oxide layer 103 is SiO 2 , and the thickness of the oxide layer 103 is about is 2 μm . In order to obtain a flat upper surface, preferably, a CMP process is used to remove a part of the oxide layer 103 . Typically, the thickness of the removed oxide layer 103 is 0.2 μm . The CMP process has a high selectivity ratio between oxide layer 103 and copper layer 105, such as 100:1. The CMP process can repair the roughness of the copper layer 105 in the via hole 102 .

參考圖8所示，圖8是本發明另一種具體實施 方式的TSV結構的平坦化製程的流程圖，用於去除非凹進區域上的金屬層105和阻擋層104。該TSV結構的平坦化製程包括以下步驟： Referring to FIG. 8, FIG. 8 is another specific implementation of the present invention A flow chart of a planarization process of a TSV structure in a manner to remove the metal layer 105 and the barrier layer 104 on the non-recessed regions. The planarization process of the TSV structure includes the following steps:

步驟801：採用金屬層化學濕法蝕刻製程去除非凹進區域上的大部分金屬層105，並在非凹進區域上保留大約0.2μm-0.5μm的金屬層。金屬層105的材料較佳者為銅，相應的，用於銅化學濕法蝕刻製程的化學液主要包括雙氧水(H2O2)、添加劑和氫氟酸，氫氟酸的濃度在2%-10%。 Step 801 : use a metal layer chemical wet etching process to remove most of the metal layer 105 on the non-recessed area, and leave a metal layer of about 0.2 μm -0.5 μm on the non-recessed area. The material of the metal layer 105 is preferably copper. Correspondingly, the chemical solution used for the copper chemical wet etching process mainly includes hydrogen peroxide (H 2 O 2 ), additives and hydrofluoric acid, and the concentration of hydrofluoric acid is 2%- 10%.

步驟803：採用化學機械平坦化製程去除非凹進區域上餘留的金屬層105。透過化學機械平坦化製程的過刻時間長度控制通孔102內的金屬層凹陷。 Step 803 : Use a chemical mechanical planarization process to remove the remaining metal layer 105 on the non-recessed regions. The metal layer recess in the via 102 is controlled by the length of the overetching time of the chemical mechanical planarization process.

步驟805：採用阻擋層化學濕法蝕刻製程去除非凹進區域上的金屬層殘餘和阻擋層104。阻擋層104的材料包括鈦，用於阻擋層化學濕法蝕刻製程的化學液主要包括氫氟酸(HF)和添加劑，氫氟酸的濃度為0.1%-1%。 Step 805 : Remove the metal layer residue and the barrier layer 104 on the non-recessed regions by using a barrier layer chemical wet etching process. The material of the barrier layer 104 includes titanium, and the chemical solution used for the chemical wet etching process of the barrier layer mainly includes hydrofluoric acid (HF) and additives, and the concentration of the hydrofluoric acid is 0.1%-1%.

採用阻擋層化學濕法蝕刻製程去除非凹進區域上的金屬層殘餘和阻擋層104後，阻擋層104下方的氧化層103暴露出來，氧化層103的材料為SiO2，氧化層103的厚度大約為2μm。為了得到平坦的上表面，較佳的，應用CMP製程去除一部分的氧化層103。通常，去除的氧化層103厚度為0.2μm。CMP製程在氧化層103和銅層105之間具有高選擇比，比如100：1。CMP製程可以修復通孔102內銅層105的粗糙度。 After the metal layer residue on the non-recessed area and the barrier layer 104 are removed by the chemical wet etching process of the barrier layer, the oxide layer 103 under the barrier layer 104 is exposed. The material of the oxide layer 103 is SiO 2 , and the thickness of the oxide layer 103 is about is 2 μm . In order to obtain a flat upper surface, preferably, a CMP process is used to remove a part of the oxide layer 103 . Typically, the thickness of the removed oxide layer 103 is 0.2 μm . The CMP process has a high selectivity ratio between oxide layer 103 and copper layer 105, such as 100:1. The CMP process can repair the roughness of the copper layer 105 in the via hole 102 .

參考圖10所示，圖10是本發明的TSV結構的平坦化裝置的方塊圖。裝置包括EFEM(設備前端模組)1001、緩衝位元1003、製程機械手1005、疊放的兩個SFP模組1007、CMP模組1009、測量模組1011、刷子清洗模組1013、濕法蝕刻模組1015和清洗模組1017。測量模組1011和刷子清洗模組1013疊放在一起，濕法蝕刻模組1015和清洗模組1017疊放在一起。該裝置還包括電模組、氣模組和管道模組。SFP模組1007用於對晶圓進行無應力抛光製程去除晶圓的非凹進區域上的金屬層。CMP模組1009用於對晶圓進行化學機械平坦化製程去除非凹進區域上的金屬層。濕法蝕刻模組1015用於對晶圓進行化學濕法蝕刻製程去除非凹進區域上的金屬層和/或阻擋層。化學濕法蝕刻製程包括金屬層化學濕法蝕刻製程和/或阻擋層化學濕法蝕刻製程。濕法蝕刻製程採取脈衝模式，每個脈衝模式步驟包括一步蝕刻劑步驟和一步DIW步驟。 Referring to FIG. 10 , FIG. 10 is a block diagram of the planarization apparatus of the TSV structure of the present invention. The device includes EFEM (Equipment Front End Module) 1001, buffer bit 1003, process robot 1005, two stacked SFP modules 1007, CMP module 1009, measurement module 1011, brush cleaning module 1013, wet etching Module 1015 and cleaning module 1017. The measurement module 1011 and the brush cleaning module 1013 are stacked together, and the wet etching module 1015 and the cleaning module 1017 are stacked together. The device also includes an electrical module, a gas module and a pipeline module. The SFP module 1007 is used to perform a stress-free polishing process on the wafer to remove the metal layer on the non-recessed area of the wafer. The CMP module 1009 is used to perform a chemical mechanical planarization process on the wafer to remove the metal layer on the non-recessed areas. The wet etching module 1015 is used to perform a chemical wet etching process on the wafer to remove the metal layer and/or the barrier layer on the non-recessed areas. The chemical wet etching process includes a metal layer chemical wet etching process and/or a barrier layer chemical wet etching process. The wet etching process adopts a pulsed mode, and each pulsed mode step includes an etchant step and a DIW step.

參考圖11，圖11所示為一種晶圓傳輸順序的方塊圖。設備前端模組機械手從裝載端取走一片未加工的晶圓並將晶圓傳輸到緩衝位1003，製程機械手1005從緩衝位1003取走晶圓並傳輸到測量模組1011以測量金屬層的厚度。測量模組1011測量完金屬層厚度後，製程機械手1005從測量模組1011取走晶圓並傳輸到其中一個SFP模組1007。在SFP模組1007中，對晶圓進行SFP製程去除非凹進區域上全部的金屬層。SFP製程完成後，製程機械手1005從SFP模組1007取走晶圓並傳輸到清洗模組1017 清洗晶圓。然後機械手1005從清洗模組1017取走晶圓並傳輸到CMP模組1009。在CMP模組1009中，對晶圓進行CMP製程去除非凹進區域上的金屬層殘餘。CMP製程完成後，製程機械手1005從CMP模組1009取走晶圓並傳輸到刷子清洗模組1013清洗晶圓。然後製程機械手從刷子清洗模組1013取走晶圓並傳輸到濕法蝕刻模組1015。在濕法蝕刻模組1015，對晶圓進行阻擋層化學濕法蝕刻製程去除非凹進區域上的阻擋層。阻擋層化學濕法蝕刻製程完成後，製程機械手1005從濕法蝕刻模組1015取走晶圓並傳輸到清洗模組1017清洗晶圓，然後製程機械手1005從清洗模組1017取走晶圓並傳輸到緩衝位元1003，最後，設備前端模組機械手從緩衝位元1003取走晶圓並傳輸到晶圓裝載端。 Referring to FIG. 11, a block diagram of a wafer transfer sequence is shown. The equipment front-end module robot takes a raw wafer from the loading end and transfers the wafer to the buffer position 1003, and the process robot 1005 takes the wafer from the buffer position 1003 and transfers it to the measurement module 1011 to measure the metal layer thickness of. After the measurement module 1011 measures the thickness of the metal layer, the process robot 1005 takes the wafer from the measurement module 1011 and transfers it to one of the SFP modules 1007 . In the SFP module 1007, an SFP process is performed on the wafer to remove all metal layers on the non-recessed areas. After the SFP process is completed, the process robot 1005 takes the wafer from the SFP module 1007 and transfers it to the cleaning module 1017 Clean the wafer. The robot 1005 then removes the wafer from the cleaning module 1017 and transfers it to the CMP module 1009. In the CMP module 1009, a CMP process is performed on the wafer to remove metal layer residues on the non-recessed areas. After the CMP process is completed, the process robot 1005 takes the wafer from the CMP module 1009 and transfers it to the brush cleaning module 1013 to clean the wafer. The process robot then removes the wafer from the brush cleaning module 1013 and transfers it to the wet etch module 1015 . In the wet etching module 1015, a barrier chemical wet etching process is performed on the wafer to remove the barrier layer on the non-recessed areas. After the chemical wet etching process of the barrier layer is completed, the process robot 1005 takes the wafer from the wet etching module 1015 and transfers it to the cleaning module 1017 to clean the wafer, and then the process robot 1005 takes the wafer from the cleaning module 1017 And transfer to the buffer bit 1003, and finally, the equipment front-end module robot takes the wafer from the buffer bit 1003 and transfers it to the wafer loading end.

如果CMP模組1009沒有測量金屬層厚度的功能，在對晶圓進行CMP製程前，晶圓應當被傳輸到測量模組1011測量SFP製程後的金屬層厚度，如圖12所示。 If the CMP module 1009 does not have the function of measuring the thickness of the metal layer, before the CMP process is performed on the wafer, the wafer should be transferred to the measurement module 1011 to measure the thickness of the metal layer after the SFP process, as shown in FIG. 12 .

除了以上晶圓傳輸順序，使用該裝置的其他傳輸順序可以根據不同的製程需求實施。 In addition to the above wafer transfer sequence, other transfer sequences using the device can be implemented according to different process requirements.

綜上所述，與傳統使用CMP製程去除非凹進區域上的金屬層、阻擋層和一部分氧化層的TSV結構平坦化製程相比，本發明利用SFP製程、金屬層化學濕法蝕刻製程和阻擋層化學濕法蝕刻製程無應力的去除非凹進區域上的金屬層105和阻擋層104，僅保留通孔102內的金屬層105和阻擋層104，如圖2所示，改善了TSV結構金屬 層凹陷的均勻性，減少了平坦化製程過程中的應力，使晶圓產生微裂紋的可能性降至最低，縮短了CMP製程持續時間，最終降低了平坦化製程的成本以及減少了化學廢液的排放。 To sum up, compared with the traditional TSV structure planarization process that uses the CMP process to remove the metal layer, the barrier layer and a part of the oxide layer on the non-recessed area, the present invention utilizes the SFP process, the metal layer chemical wet etching process and the barrier process. The layer chemical wet etching process removes the metal layer 105 and the barrier layer 104 on the non-recessed area without stress, leaving only the metal layer 105 and the barrier layer 104 in the through hole 102, as shown in FIG. 2, which improves the metal layer of the TSV structure. The uniformity of the layer depression reduces stress during the planarization process, minimizes the possibility of microcracks in the wafer, shortens the CMP process duration, ultimately reduces the cost of the planarization process and reduces chemical waste emissions.

以上所述，僅是本發明的較佳實施例而已，並非對本發明作任何形式上的限制。任何熟悉本領域的技術人員，在不脫離本發明技術方案範圍情況下，都可利用上述揭示的技術內容對本發明技術方案作出許多可能的變動和修飾，或修改為等同變化的等效實施例。因此，凡是未脫離本發明技術方案的內容，依據本發明的技術實質對以上實施例所做的任何簡單修改、等同變化及修飾，均仍屬於本發明技術方案保護的範圍內。 The above descriptions are only preferred embodiments of the present invention, and do not limit the present invention in any form. Any person skilled in the art, without departing from the scope of the technical solution of the present invention, can make many possible changes and modifications to the technical solution of the present invention by using the technical content disclosed above, or modify the equivalent embodiments of equivalent changes. Therefore, any simple modifications, equivalent changes and modifications made to the above embodiments according to the technical essence of the present invention without departing from the content of the technical solutions of the present invention still fall within the protection scope of the technical solutions of the present invention.

1001:EFEM(設備前端模組) 1001: EFEM (Equipment Front End Module)

1003:緩衝位 1003: buffer bit

1005:機械手 1005: Robot

1007:SFP模組 1007:SFP module

1009:CMP模組 1009: CMP Module

1011:量測模組 1011: Measurement module

1013:刷子清洗模組 1013: Brush Cleaning Module

1015:濕法蝕刻模組 1015: Wet Etching Module

1017:清洗模組 1017: Cleaning Module

Claims (4)

一種TSV結構的平坦化裝置，該TSV結構包括晶圓、晶圓上的通孔、晶圓上的氧化層、氧化層上及通孔的底部和側壁上的阻擋層、通孔內及阻擋層上的金屬層，其特徵在於，TSV結構的平坦化裝置包括：至少一個SFP模組，用於對晶圓進行無應力抛光製程去除晶圓的非凹進區域上的金屬層；CMP模組，用於對晶圓進行化學機械平坦化製程去除非凹進區域上的金屬層；以及濕法蝕刻模組，用於對晶圓進行化學濕法蝕刻製程去除非凹進區域上的金屬層和/或阻擋層。 A planarization device of a TSV structure, the TSV structure includes a wafer, a through hole on the wafer, an oxide layer on the wafer, a barrier layer on the oxide layer and the bottom and sidewalls of the through hole, inside the through hole and the barrier layer It is characterized in that, the planarization device of the TSV structure comprises: at least one SFP module for performing stress-free polishing process on the wafer to remove the metal layer on the non-recessed area of the wafer; CMP module, A chemical mechanical planarization process for removing metal layers on non-recessed areas of wafers; and a wet etch module for performing chemical wet etching processes on wafers to remove metal layers and/or non-recessed areas on wafers or barrier layer. 根據請求項1所述的TSV結構的平坦化裝置，其特徵在於，化學濕法蝕刻製程包括金屬層化學濕法蝕刻製程和/或阻擋層化學濕法蝕刻製程。 The planarization device for a TSV structure according to claim 1, wherein the chemical wet etching process includes a metal layer chemical wet etching process and/or a barrier layer chemical wet etching process. 根據請求項1所述的TSV結構的平坦化裝置，其特徵在於，濕法蝕刻製程採取脈衝模式，每個脈衝模式步驟包括使用蝕刻劑之步驟和使用DIW之步驟。 The planarization device of the TSV structure according to claim 1, wherein the wet etching process adopts a pulse mode, and each pulse mode step includes a step of using an etchant and a step of using DIW. 根據請求項1所述的TSV結構的平坦化裝置，其特徵在於，進一步包括：測量模組，用於測量金屬層的厚度；刷子清洗模組，用於在化學機械平坦化製程完成後清洗晶圓； 清洗模組，用於在無應力抛光製程或化學濕法蝕刻製程完成後清洗晶圓。 The planarization device of the TSV structure according to claim 1, further comprising: a measuring module for measuring the thickness of the metal layer; a brush cleaning module for cleaning the crystal after the chemical mechanical planarization process is completed round; The cleaning module is used to clean the wafer after the stress-free polishing process or the chemical wet etching process is completed.
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