TWI758603B - Optoelectronic device and method for manufacturing the same - Google Patents

Abstract

An optoelectronic device including a epitaxial stack including a first semiconductor layer, an active layer formed on the first semiconductor layer, and a second semiconductor layer formed on the active layer; multiple boundaries exposing the first semiconductor layer, two adjacent boundaries of the multiple boundaries forming a corner of the first semiconductor layer; first parts of a first conductive type electrodes formed on the first semiconductor layer exposed by the multiple boundaries, wherein the first parts of a first conductive type electrodes are separated from each other, and not surrounded by the second semiconductor layer; a third electrode formed on the first parts of a first conductive type electrodes and the second semiconductor layer; and one or more fourth electrodes formed on the second semiconductor layer.

Description

Photoelectric element and method of manufacturing the same

The present invention relates to an optoelectronic element, in particular to an electrode design of an optoelectronic element.

The light-emitting principle of light-emitting diode (LED) is to use the energy difference of electrons moving between n-type semiconductor and p-type semiconductor to release energy in the form of light. This light-emitting principle is different from incandescent lamps. The light-emitting principle of heat generation, so light-emitting diodes are called cold light sources. In addition, light-emitting diodes have the advantages of high durability, long life, light weight, and low power consumption. Therefore, today's lighting market places high hopes on light-emitting diodes, and regards them as a new generation of lighting tools, which have gradually replaced traditional Light source, and used in various fields, such as traffic signs, backlight modules, street lighting, medical equipment, etc.

FIG. 1 is a schematic structural diagram of a conventional light-emitting device. As shown in FIG. 1, a conventional light-emitting device 100 includes a transparent substrate 10, a semiconductor stack 12 on the transparent substrate 10, and at least one electrode 14 on the semiconductor On the stack 12 , the above-mentioned semiconductor stack 12 at least includes a first conductivity type semiconductor layer 120 , an active layer 122 , and a second conductivity type semiconductor layer 124 from top to bottom.

In addition, the above-mentioned light-emitting device 100 can be further combined and connected with other devices to form a light-emitting apparatus. FIG. 2 is a schematic structural diagram of a conventional light-emitting device. As shown in FIG. 2, a light-emitting device 200 includes a sub-mount 20 having at least one circuit 202; at least one solder 22 is located on the sub-mount 20, the above-mentioned light-emitting element 100 is bonded and fixed on the sub-carrier 20 by the solder 22, and the substrate 10 of the light-emitting element 100 is electrically connected to the circuit 202 on the sub-carrier 20; and an electrical connection structure 24 is formed to The electrode 14 of the light-emitting element 100 is electrically connected to the circuit 202 on the sub-carrier 20 ; wherein, the sub-carrier 20 can be a lead frame or a large-sized mounting substrate to facilitate the circuit of the light-emitting device 200 Plan and improve its cooling effect.

An optoelectronic element, comprising: a first semiconductor layer with at least four boundaries, a first surface, and a second surface opposite to the first surface, wherein any two adjacent boundaries can form a corner; a second semiconductor layer layer is formed on the first surface of the first semiconductor layer; a second electrical type electrode is formed on the second semiconductor layer; and at least two first electrical type electrodes are formed on the first surface of the first semiconductor layer , wherein the at least two first electrical electrodes are separated from each other and form a design type.

The present invention discloses a light-emitting device and a manufacturing method thereof. In order to make the description of the present invention more detailed and complete, please refer to the following description in conjunction with the illustrations in FIGS. 3A to 7 .

3A and 3B are the top view and the side view of the photoelectric device 300 according to the first embodiment of the present invention. Fig. 3B is a side view of the structure in the direction A-B-C in Fig. 3A. The photovoltaic element 300 has a substrate 30 . The substrate 30 is not limited to a single material, and may also be a composite substrate formed by combining a plurality of different materials. For example, the substrate 30 may include two mutually bonded first substrates (not shown) and second substrates (not shown).

On the substrate 30, a conventional epitaxial growth process is used to form an epitaxial stack 31, including the first semiconductor layer 311 having a first surface 3111 and a second surface 3112 opposite to the first surface, and an active layer 312 is formed On the first surface 3111 of the first semiconductor layer 311 , and a second semiconductor layer 313 is formed on the active layer 312 . Next, a portion of the epitaxial stack is selectively removed by a yellow photolithography process technology to expose a portion of the first semiconductor layer 311 at the boundary of the photoelectric element 300 , and a trench S is formed in the photoelectric element 300 . In one embodiment, the trench S exposes part of the first semiconductor layer 311 and is surrounded by the second semiconductor layer 313 . In one embodiment, the trench S is a long strip in the top view.

Next, a first insulating layer 341 is deposited on the surface of the epitaxial stack 31 of the photoelectric element 300 and the sidewall of the trench S by chemical vapor deposition (CVD) or physical vapor deposition (PVD) techniques.

Next, at least one first first electrical type electrode 321 is formed on the exposed first semiconductor layer 311 beside the boundary of the photoelectric element 300 . In one embodiment, the first first electrical type electrode 321 is not surrounded by the second semiconductor layer 313 , and a second first electrical type electrode 322 is formed in the trench S. In this embodiment, the separated first first electrical type electrode 321 and the second first electrical type electrode 322 form an electrode design type of the first electrical type electrode.

In the embodiment of the present invention, the electrode design pattern may include the selection of the number of electrodes, the shape of the electrodes, and the positions of the electrodes, so as to improve the current distribution of the photovoltaic element near the boundary region. For example, the electrode design type of the first electrical type electrode may include one or more first first electrical type electrodes 321 and one or more second first electrical type electrodes 322, and the second first electrical type electrodes 322 are automatically The top view is surrounded by the second semiconductor layer 313 and has an extended shape.

In one embodiment, the first semiconductor layer 311 of the optoelectronic device 300 has at least four borders, two adjacent borders may form a corner, and there is no conductive structure crossing the borders. In this embodiment, the first first electrical type electrodes 321 are formed at two corners on the same boundary of the photoelectric element 300 , separated from each other and not crossing the boundary of the photoelectric element 300 .

In one embodiment, the projection of the first first electrical type electrode 321 on the first semiconductor layer 311 may have a shape, and the shape may be a polygon, a circle, an ellipse, a semi-circle, or a circle. Arc. The second first electrical type electrode 322 may be linear, arc, a mixture of linear and arc, or may have at least one branch. In one embodiment, the second first electrical type electrode 322 may have a head end and a tail end, and the head end has a width greater than a width of the tail end.

Next, a second electrical type electrode 33 is formed on the second semiconductor layer 313 . In one embodiment, the ratio of the projected area of the second electrical type electrode 33 on the first semiconductor layer 311 to the surface area above the second semiconductor layer 313 is between 90% and 100%.

After that, a second insulating layer 342 can be formed on the first first electrical type electrode 321 , the second first electrical type electrode 322 , the second electrical type electrode 33 and part of the first insulating layer 341 . The second insulating layer 342 may have a first opening 3421 for electrically connecting the second electrical type electrode 33 and the fourth electrode 36 to be formed later, and the second insulating layer 342 may also have a second opening 3422 as a first A first electrical electrode 321 is used for electrical connection with the third electrode 35 formed subsequently. In one embodiment, the first insulating layer 341 or the second insulating layer 342 can completely cover the exposed first semiconductor layer 311 .

In one embodiment, the first insulating layer 341 or the second insulating layer 342 may be a transparent insulating layer. The material of the first insulating layer 341 or the second insulating layer 342 may be oxide, nitride, or polymer, and the oxide may include aluminum oxide (Al2O3), silicon oxide (SiO2), titanium dioxide (TiO2), Tantalum Pentoxide (Ta2O5) or Alumina (AlOx); Nitride may include Aluminum Nitride (AlN), Silicon Nitride (SiNx); Polymer may include Polyimide (Polyimide) or Benzene Butane (benzocyclobutane, BCB) and other materials or a composite combination of the above. In one embodiment, the first insulating layer 341 or the second insulating layer 342 may be a Bragg reflector (Distributed Bragg Reflector) structure.

Finally, a third electrode 35 is formed on the second insulating layer 342 , the first first electrical type electrode 321 and the second first electrical type electrode 322 and is connected with the first first electrical type electrode 321 and the second first electrical type electrode 321 The electrical electrode 322 is electrically connected; and a fourth electrode 36 is formed on the second insulating layer 342 and the second electrical electrode 33 and is electrically connected to the second electrical electrode 33 . In one embodiment, viewed from the top, the ratio of the projected areas of the third electrode 35 and the fourth electrode 36 on the first semiconductor layer 311 is between 80% and 100%.

In one embodiment, the third electrode 35 may only cover part of the first first electrical type electrode 321 ; in another embodiment, the third electrode 35 may not cover the first first electrical type electrode 321 at all.

In one embodiment, there is a height H1 from the upper edge of the third electrode 35 to the upper edge of the substrate 30 , and a height H2 from the upper edge of the fourth electrode 36 to the upper edge of the substrate 30 , and H1 is substantially equal to H2 . In one embodiment, the difference between H1 and H2 is less than 5-10%. By adjusting the difference between H1 and H2, the probability of disconnection of the optoelectronic device 300 to form a flip-chip structure with the carrier board or the circuit device can be reduced, thereby increasing the product yield. In one embodiment, the boundary of the third electrode 35 and the boundary of the fourth electrode 36 have a minimum distance D1 , and D1 is greater than 50 μm. In one embodiment, D1 may be 50-200 μm, 100-200 μm.

In one embodiment, the first first electrical type electrode 321 , the second first electrical type electrode 322 , the second electrical type electrode 33 , the third electrode 35 and the fourth electrode 36 may be a multi-layer structure, and/or It includes a reflective layer (not shown in the figure), and can have a reflectivity of more than 80% for the light emitted by the active layer 312 . In one embodiment, the first first electrical type electrode 321 , the second first electrical type electrode 322 and the third electrode 35 can also be formed in the same process. In one embodiment, the light emitted by the optoelectronic element 300 can be reflected by the first first electrical type electrode 321 , the second first electrical type electrode 322 , the second electrical type electrode 33 , the third electrode 35 or the fourth electrode 36 . The photovoltaic element 300 is separated from the direction of the substrate 30 .

In order to achieve a certain degree of conductivity, the material of the first first electrical type electrode 321 , the second first electrical type electrode 322 , the second electrical type electrode 33 , the third electrode 35 and the fourth electrode 36 can preferably be metal, for example, For example, gold (Au), silver (Ag), copper (Cu), chromium (Cr), aluminum (Al), platinum (Pt), nickel (Ni), titanium (Ti), tin (Sn), etc., their alloys or its stacking combination.

In one embodiment, a carrier or a circuit element (not shown) can be provided, and a first carrier electrode (not shown) and a The second carrier electrode (not shown). The first carrier electrode and the second carrier electrode can form a flip-chip structure with the third electrode 35 and the fourth electrode 36 of the photoelectric element 300 .

In one embodiment, a first adjustment layer (not shown) may be formed between the first first electrical type electrode 321 , and/or the second first electrical type electrode 322 and the third electrode 35 , and the electrical Connected to the first first electrical type electrode 321 and/or the second first electrical type electrode 322 and the third electrode 35 . In one embodiment, a second adjustment layer (not shown) may be formed between the second electrical type electrode 33 and the fourth electrode 36 and electrically connected to the second electrical type electrode 33 and the fourth electrode 36 . In this embodiment, the first adjustment layer and the second adjustment layer may have a height respectively, and because of the formation positions of the first adjustment layer and the second adjustment layer, the heights of the first adjustment layer and the second adjustment layer will affect The heights of H1 and H2 above. Therefore, by separately designing the formation heights of the first adjustment layer and/or the second adjustment layer, the height difference between the above-mentioned H1 and H2 can be reduced, and the breakage of the photoelectric element 300 in the subsequent flip-chip structure formation with the carrier or circuit element can be reduced. Line probability, thereby increasing product yield. In one embodiment, the projected area of the first adjustment layer on the first semiconductor layer 311 is larger than the projected area of the third electrode 35 on the first semiconductor layer 311 , or the projected area of the second adjustment layer on the first semiconductor layer 311 The area is larger than the projected area of the fourth electrode 36 on the first semiconductor layer 311 . In one embodiment, the material of the first adjustment layer or the second adjustment layer may preferably be, for example, a metal, such as gold (Au), silver (Ag), copper (Cu), chromium (Cr), aluminum (Al), Platinum (Pt), nickel (Ni), titanium (Ti), tin (Sn), etc., alloys thereof, or laminate combinations thereof. In one embodiment, the first adjustment layer or the second adjustment layer can be a multi-layer structure, and/or include a reflective layer (not shown), and can reflect more than 80% of the light emitted by the active layer 312 Rate.

FIG. 3C is a top view of the photoelectric device 400 according to the second embodiment of the present invention. The manufacturing method, used materials, and labels of this embodiment are the same as those of the above-mentioned first embodiment, and will not be repeated here. In the embodiment of the present invention, the electrode design pattern may include the selection of the number of electrodes, the shape of the electrodes, and the position of the electrodes, so as to improve the current spreading of the photovoltaic element 400 near the boundary region.

In one embodiment, the first semiconductor layer 311 of the optoelectronic device 400 has at least four borders, two adjacent borders may form a corner, and there is no conductive structure crossing the borders. In this embodiment, the first first electrical type electrode 321 is formed on any corner of the first semiconductor layer 311, and the second insulating layer 342 may have a second opening 3422 as the first first electrical type electrode 321 is used for electrical connection with the third electrode 35 formed later. The second first electrical type electrode 322 is formed on the first semiconductor layer 311 and surrounded by the second semiconductor layer 313, and the second insulating layer 342 may also have a third opening 3423 as the second first electrical type electrode 322 is used for electrical connection with the third electrode 35 formed later.

In this embodiment, the projection of the first first electrical type electrode 321 on the first semiconductor layer 311 may have a shape, wherein the shape may be a polygon, a circle, an ellipse, a semicircle or a Arc face. The second first electrical type electrode 322 is an extension shape, and the shape can be a line shape, an arc shape, a mixed shape of the line shape and the arc shape, or can have at least one branch. In one embodiment, the second first electrical type electrode 322 may have a head end and a tail end, and the head end may have a width greater than a width of the tail end.

In this embodiment, the third first electrical type electrode 323 is formed on the exposed first semiconductor layer 311 beside the boundary of the photoelectric element 400 . In one embodiment, the third first electrical type electrode 323 is not surrounded by the second semiconductor layer 313 , and the second insulating layer 342 has a fourth opening 3424 to serve as the third first electrical type electrode 323 and the subsequent formed first electrode 323 . The three electrodes 35 are used for electrical connection. The fourth first electrical type electrode 324 is formed on the exposed first semiconductor layer 311 beside the boundary of the photoelectric element 400 . In one embodiment, the fourth first electrical type electrode 324 is not surrounded by the second semiconductor layer 313 , and the second insulating layer 342 has a fifth opening 3425 to serve as the fourth first electrical type electrode 324 and the subsequent formed first electrode 324 . The three electrodes 35 are used for electrical connection.

In this embodiment, the projection of the third first electrical type electrode 323 on the first semiconductor layer 311 may have a shape, wherein the shape may be a polygon, a circle, an ellipse, a semi-circle, or a Arc face. The shape of the fourth first electrical type electrode 324 may be linear, arc, a mixture of linear and arc, or may have at least one branch. In one embodiment, the fourth first electrical type electrode 324 may have a head end and a tail end, and the head end may have a width greater than a width of the tail end. In one embodiment, the shapes of the third first electrical type electrode 323 and the fourth first electrical type electrode 324 are different.

In one embodiment, according to product design requirements, the first first electrical type electrode 321 and the third first electrical type electrode 323 can be formed beside the same boundary of the optoelectronic device 400 and separated from each other. In one embodiment, the first first electrical type electrode 321 and the fourth first electrical type electrode 324 , or the third first electrical type electrode 323 and the fourth first electrical type electrode 324 are not formed on the same part of the photoelectric element 400 . next to the border.

In one embodiment, the head end of the fourth first electrical type electrode 324 may be covered by the third electrode 35 , and the tail end of the fourth first electrical type electrode 324 is not covered by the fourth electrode 36 . In this embodiment, the projected area of the third electrode 35 on the first semiconductor layer 311 is larger than the projected area of the fourth electrode 36 on the first semiconductor layer 311 , and the third electrode 35 and the fourth electrode 36 are on the first semiconductor layer 311 . The ratio of the projected area on the layer 311 is between 110-120%. In one embodiment, the extending directions of the tail ends of the second first electrical type electrode 322 and the fourth first electrical type electrode 324 are substantially parallel to each other.

FIG. 4A is a top view of a photovoltaic device 500 according to the third embodiment of the present invention. The manufacturing method, used materials, and labels of this embodiment are the same as those of the above-mentioned first embodiment, and will not be repeated here. In the embodiment of the present invention, the electrode design pattern may include the selection of the number of electrodes, the shape of the electrodes, and the positions of the electrodes, so as to improve the current spreading of the photovoltaic element 500 near the boundary region.

In this embodiment, the four borders of the photoelectric element 500 form a rectangle, two adjacent borders can form a corner, and there is no conductive structure crossing the borders, and the borders have a first long side B1 and a second long side B3 , a first short side B2 and a second short side B4. In one embodiment, the length of the first long side B1 or the second long side B3 is greater than the length of the first short side B2 or the second short side B4 . In this embodiment, the projections of the third electrode 35 and the fourth electrode 36 on the first semiconductor layer 311 are arranged along the first long side B1 or the second long side B3.

In this embodiment, the two first first electrical type electrodes 321 separated from each other are formed on two corners of the first short side B2, and the second insulating layer 342 may also have a second opening 3422 as a The first first electrical electrode 321 is used for electrical connection with the third electrode 35 formed later. The two fourth first electrical type electrodes 324 are respectively located on the exposed first semiconductor layer 311 beside the boundary between the first long side B1 and a second long side B3 . In this embodiment, the third first electrical type electrode 323 is formed on the first short side B2, and the second insulating layer 342 may also have a fourth opening 3424 for the third first electrical type electrode 323 and the The third electrode 35 formed subsequently is used for electrical connection. The fourth first electrical type electrode 324 is not surrounded by the second semiconductor layer 313 , and the second insulating layer 342 may also have a third opening 3423 to serve as the fourth first electrical type electrode 324 and the third electrode 35 formed subsequently. for sexual connection.

In one embodiment, the distance between the third first electrical type electrode 323 and the above-mentioned two first first electrical type electrodes 321 is substantially equal. In addition, the first first electrical type electrode 321 , the fourth first electrical type electrode 324 , and the third electrode 35 can be formed in the same process.

In this embodiment, the projection of the first first electrical type electrode 321 on the first semiconductor layer 311 may have a figure, wherein the figure is a polygon, a circle, an ellipse, a semi-circle or has an arc noodle. The projection of the third first electrical type electrode 323 on the first semiconductor layer 311 may have a figure, wherein the figure is a polygon, a circle, an ellipse, a semicircle or a circular arc surface. The fourth first electrical type electrode 324 is an extension shape, and can be a line shape, an arc shape, a mixed shape of a line shape and an arc shape, or can have at least one branch. In one embodiment, the fourth first electrical type electrode 324 has a head end and a tail end, and the head end may have a width greater than that of the tail end. In one embodiment, the shapes of the third first electrical type electrode 323 and the fourth first electrical type electrode 324 are different.

In one embodiment, the head end of the fourth first electrical type electrode 324 points to the first short side B2 and the tail end points to the second short side B4. In one embodiment, the head end of the fourth first electrical type electrode 324 can be covered by the third electrode 35 , and the tail end of the fourth first electrical type electrode 324 is not covered by the fourth electrode 36 . In one embodiment, the extending directions of the tail ends of the two fourth first electrical type electrodes 324 are substantially parallel to each other. In this embodiment, the projected area of the third electrode 35 on the first semiconductor layer 311 is larger than the projected area of the fourth electrode 36 on the first semiconductor layer 311; and the third electrode 35 and the fourth electrode 36 are on the first semiconductor layer The ratio of the projected area on the layer 311 is between 110-120%.

FIG. 4B shows a top view of the optoelectronic device 600 according to the fourth embodiment of the present invention. The manufacturing method, used materials, and labels of this embodiment are the same as those of the above-mentioned first embodiment, and will not be repeated here. In the embodiment of the present invention, the electrode design pattern may include the selection of the number of electrodes, the shape of the electrodes, and the position of the electrodes, so as to improve the current spreading of the photovoltaic element 600 near the boundary region.

In this embodiment, the four borders of the photoelectric element 600 form a rectangle, two adjacent borders can form a corner, and there is no conductive structure crossing the borders. The photoelectric element 600 has a first long side B1, a second long side B3, a first short side B2 and a second short side B4. In one embodiment, the length of the first long side B1 or the second long side B3 is greater than the length of the first short side B2 or the second short side B4 . In this embodiment, the projections of the third electrode 35 and the fourth electrode 36 on the first semiconductor layer 311 are arranged along the first long side B1 or the second long side B3.

In this embodiment, at least one first electrode 321 of the first electrical type is included. In one embodiment, four first first electrical type electrodes 321 may be formed on the four corners of the first semiconductor layer 311, and the second insulating layer 342 may also have a second opening 3422 as the first An electrical electrode 321 is used for electrical connection with the third electrode 35 formed later. Two second first electrical type electrodes 322 are formed on the first semiconductor layer 311 and surrounded by the second semiconductor layer 313, and the second insulating layer 342 may also have a third opening 3423 as the second first electrical electrode. The sex electrode 322 is used for electrical connection with the third electrode 35 formed later.

In this embodiment, the projection of the first first electrical type electrode 321 on the first semiconductor layer 311 may have a figure, wherein the figure is a polygon, a circle, an ellipse, a semi-circle or has an arc noodle. The projection of the second first electrical type electrode 322 on the first semiconductor layer 311 may have a figure, wherein the figure is a polygon, a circle, an ellipse, a semicircle or a circular arc surface. In one embodiment, the projected shapes of the two second first electrical type electrodes 322 on the first semiconductor layer 311 may be the same or different.

In this embodiment, the third electrode 35 includes two extending portions 351 , and the two extending portions 351 may substantially form a recess R, and the fourth electrode 36 is located in the recess R. In addition, the first first electrical type electrode 321 , the second first electrical type electrode 322 and the third electrode 35 can be formed in the same process.

FIG. 4C shows a top view of the optoelectronic device 700 according to the fifth embodiment of the present invention. The manufacturing method, used materials, and labels of this embodiment are the same as those of the above-mentioned first embodiment, and will not be repeated here. In the embodiment of the present invention, the electrode design can include the selection of the number of electrodes, the shape of the electrodes, and the positions of the electrodes, so as to improve the current spreading of the photovoltaic element 700 near the boundary region.

In one embodiment, the first semiconductor layer 311 of the optoelectronic device 700 has at least four borders, two adjacent borders may form a corner, and there is no conductive structure crossing the borders. In this embodiment, there are four first first electrical type electrodes 321, which are respectively formed on the four corners of the first semiconductor layer 311, and the second insulating layer 342 may also have a second opening 3422 as a The first first electrical electrode 321 is used for electrical connection with the third electrode 35 formed later. A plurality of second first electrical type electrodes 322 are formed on the first semiconductor layer 311 and are surrounded by the second semiconductor layer 313, and the second insulating layer 342 may also have a fourth opening 3424 as the second first electrical electrode. The sex electrode 322 is used for electrical connection with the third electrode 35 formed later. A plurality of third first electrical type electrodes 323 are formed on the exposed first semiconductor layer 311 beside the boundary of the photoelectric element 700 . In other words, the third first electrical type electrode 323 is not surrounded by the second semiconductor layer 313 , and any boundary of the first semiconductor layer 311 may include one or more third first electrical type electrodes 323 . The second insulating layer 342 may have a third opening 3423 for electrically connecting the second first electrical type electrode 322 to the third electrode 35 formed subsequently.

In this embodiment, the projection of the first first electrical type electrode 321 on the first semiconductor layer 311 may have a figure, wherein the figure is a polygon, a circle, an ellipse, a semi-circle or has an arc noodle. The projection of the second first electrical type electrode 322 on the first semiconductor layer 311 may have a figure, wherein the figure is a polygon, a circle, an ellipse, a semicircle or a circular arc surface. In one embodiment, the shape of the second first electrical type electrode 322 can be extended, and the extending direction thereof can be parallel to the extending direction of the extending portion 351 . The second first electrical type electrode 322 may be linear, arc, a mixture of linear and arc, or may have at least one branch. In one embodiment, the projected areas of the plurality of second first electrical type electrodes 322 on the first semiconductor layer 311 may be the same or different. The projection of the third first electrical type electrode 323 on the first semiconductor layer 311 may have a figure, wherein the figure is a polygon, a circle, an ellipse, a semicircle or a circular arc surface.

In this embodiment, the third electrode 35 includes three extending portions 351 , and the three extending portions 351 can substantially form two notches R, and the two fourth electrodes 36 can be formed in the two notches R . In this embodiment, at least one second first electrical type electrode 322 may be formed in the above-mentioned extension portion 351 .

In one embodiment, the projection shapes of the first first electrical type electrode 321 , the second first electrical type electrode 322 , and the third first electrical type electrode 323 on the first semiconductor layer 311 can also be the same or different. In addition, the first first electrical type electrode 321 , the second first electrical type electrode 322 , the third first electrical type electrode 323 and the third electrode 35 can also be formed in the same process.

FIG. 4D is a top view of a photovoltaic device 700' according to the sixth embodiment of the present invention. This embodiment is a possible variation of the fifth embodiment, and its fabrication method, materials used, electrode designs and labels are the same as those of the fifth embodiment, and will not be repeated here.

In this embodiment, the second insulating layer 342 of the optoelectronic element 700' has a plurality of first openings 3421' for electrically connecting the second electrical electrodes 33 and the fourth electrodes 36 formed subsequently. In this embodiment, the second insulating layer 342 has a plurality of first openings 3421 to reduce the height difference between the third electrode 35 and the fourth electrode 36 , thereby reducing the probability of wire breakage when the flip chip structure is subsequently formed with the carrier board or the circuit element. , thereby increasing the product yield.

5A to 5C are schematic diagrams of a light-emitting module, and FIG. 5A is an external perspective view of a light-emitting module. A light-emitting module 800 may include a carrier 502, a photoelectric element (not shown), a plurality of lenses 504 , 506 , 508 and 510 , and two power supply terminals 512 and 514 . The light emitting module 800 can be connected to the light emitting unit 540 described later.

FIGS. 5B-5C are cross-sectional views of a light-emitting module 800 , wherein FIG. 8C is an enlarged view of the area E of FIG. 8B . The carrier 502 can include an upper carrier 503 and a lower carrier 501 , wherein a surface of the lower carrier 501 can be in contact with the upper carrier 503 . Lenses 504 and 508 are formed on the upper carrier 503 . The upper carrier 503 can form at least one through hole 515, and the optoelectronic element 300 formed according to the embodiment of the present invention or the optoelectronic element (not shown) of other embodiments can be formed in the through hole 515 and contact with the lower carrier 501, and be The glue material 521 surrounds. There is a lens 508 on the adhesive material 521, wherein the material of the adhesive material 521 can be silicone resin, epoxy resin or other materials. In one embodiment, a reflective layer 519 can be formed on the two sidewalls of the through hole 515 to increase the light extraction efficiency; a metal layer 517 can be formed on the lower surface of the carrier 501 to improve the heat dissipation efficiency.

FIGS. 6A-6B are schematic diagrams of a light source generating device 900 . A light source generating device 900 may include a light-emitting module 800 , a light-emitting unit 540 , and a power supply system (not shown) for supplying a current to the light-emitting module 800 , and a control element (not shown) for controlling the power supply system (not shown). The light source generating device 900 may be a lighting device, such as a street lamp, a vehicle lamp or an indoor lighting source, or a traffic sign or a backlight source of a backlight module in a flat panel display.

FIG. 7 is a schematic diagram of a light bulb. The light bulb 1000 includes a housing 921 , a lens 922 , a lighting module 924 , a bracket 925 , a heat sink 926 , a serial connection portion 927 and an electrical connector 928 . The lighting module 924 includes a carrier 923, and the carrier 923 includes at least one optoelectronic element 300 in the above embodiment or an optoelectronic element in other embodiments (not shown).

Specifically, the substrate 30 is a growth and/or carrying base. Candidate materials may include conductive or non-conductive substrates, light transmissive or opaque substrates. One of the conductive substrate materials can be germanium (Ge), gallium arsenide (GaAs), indium phosphorus (InP), silicon carbide (SiC), silicon (Si), lithium aluminate (LiAlO2), zinc oxide (ZnO) , Gallium Nitride (GaN), Aluminum Nitride (AlN), Metal. One of the transparent substrate materials can be sapphire (Sapphire), lithium aluminate (LiAlO2), zinc oxide (ZnO), gallium nitride (GaN), glass, diamond, CVD diamond, and diamond-like carbon (Diamond-Like Carbon; DLC), spinel (spinel, MgAl2O4), alumina (Al2O3), silicon oxide (SiOX) and lithium gallate (LiGaO2).

The epitaxial stack 31 includes a first semiconductor layer 311 , an active layer 312 , and a second semiconductor layer 313 . The first semiconductor layer 311 and the second semiconductor layer 313 are, for example, a cladding layer or a confinement layer, which can be a single-layer or multi-layer structure. The first semiconductor layer 311 and the second semiconductor layer 313 are different in electrical properties, polarities or dopants, and their electrical properties can be a combination of at least any two of p-type, n-type, and i-type, which can be provided separately. Electrons and holes are combined in the active layer 312 to emit light. The materials of the first semiconductor layer 311, the active layer 312, and the second semiconductor layer 313 may include III-V semiconductor materials, such as AlxInyGa(1-x-y)N or AlxInyGa(1-x-y)P, where 0≦x, y ≦1; (x+y)≦1. Depending on the material of the active layer 312, the epitaxial stack can emit red light with wavelengths between 610 nm and 650 nm, green light with wavelengths between 530 nm and 570 nm, and wavelengths between 450 nm and 490 nm. between blue light, or ultraviolet light with a wavelength less than 400nm.

In another embodiment of the present invention, the photoelectric element 300, 400, 500, 600, 700, 700' can be an epitaxial element or a light emitting diode, and its emission spectrum can be changed by changing the epitaxial stacked monolayer or multiple layers of physical or chemical elements to adjust. The single-layer or multi-layer epitaxial stack material can be selected from aluminum (Al), gallium (Ga), indium (In), phosphorus (P), nitrogen (N), zinc (Zn) and oxygen (O) group. The structure of the active layer 312 is, for example, a single heterostructure (SH), a double heterostructure (DH), a double-side double heterostructure (DDH), or a multi-layer quantum well (multi-heterostructure). quantum well; MQW) structure. Furthermore, adjusting the logarithm of the quantum wells in the active layer 312 can also change the emission wavelength.

In an embodiment of the present invention, a buffer layer (not shown) may optionally be included between the first semiconductor layer 311 and the substrate 30 . The buffer layer is between the two material systems, "transitioning" the material system of the substrate 30 to the material system of the first semiconductor layer 311 . For the structure of the light emitting diode, on the one hand, the buffer layer is a material layer used to reduce the lattice mismatch between the two materials. On the other hand, the buffer layer can also be a single layer, a multi-layer or a structure for combining two materials or two separate structures. The materials that can be used are: organic materials, inorganic materials, metals, and semiconductors, etc.; Selected structures are: reflective layer, thermally conductive layer, conductive layer, ohmic contact layer, anti-deformation layer, stress release layer, stress adjustment layer, bonding layer, wavelength Conversion layer, and mechanical fixing structure, etc. In one embodiment, the material of the buffer layer can be selected from aluminum nitride or gallium nitride, and the buffer layer can be formed by sputtering or atomic layer deposition (ALD).

A contact layer (not shown) can be selectively formed between the second semiconductor layer 313 and the second electrical type electrode 33 . Specifically, the contact layer can be an optical layer, an electrical layer, or a combination of the two. The optical layer system can alter the electromagnetic radiation or light coming from or entering the active layer. "Modifying" as used herein means changing at least one optical property of electromagnetic radiation or light, including but not limited to frequency, wavelength, intensity, flux, efficiency, color temperature, rendering index, light field (light field), and angle of view. The electrical layer can make the value, density and distribution of at least one of the voltage, resistance, current, and capacitance between any set of opposite sides of the contact layer change or have a tendency to change. The constituent materials of the contact layer include oxides, conductive oxides, transparent oxides, oxides with a transmittance of 50% or more, metals, relatively light-transmitting metals, metals with a transmittance of 50% or more, organic substances, At least one of inorganic substances, phosphors, phosphors, ceramics, semiconductors, doped semiconductors, and undoped semiconductors. In some applications, the material of the contact layer is at least one of indium tin oxide, cadmium tin oxide, antimony tin oxide, indium zinc oxide, zinc aluminum oxide, and zinc tin oxide. If it is a relatively light-transmitting metal, its thickness is preferably about 0.005 μm~0.6 μm.

Although the above drawings and descriptions only correspond to specific embodiments, the elements, implementations, design criteria, and technical principles described or disclosed in each embodiment are in conflict with each other, contradictory, or difficult to implement together. In addition, we shall be free to refer to, exchange, collocate, coordinate, or combine as desired. Although the present invention has been described above, it is not intended to limit the scope of the present invention, the order of implementation, or the materials and process methods used. Various modifications and changes made to the present invention do not depart from the spirit and scope of the present invention.

100, 200, 300, 400, 500, 600, 700, 700’‧‧‧Light-emitting element

10‧‧‧Transparent substrate

12‧‧‧Semiconductor stack

14. E1, E2‧‧‧electrode

30‧‧‧Substrate

31‧‧‧Epitaxy Lamination

311‧‧‧First semiconductor layer

312‧‧‧Active layer

313‧‧‧Second semiconductor layer

S‧‧‧ditch

341‧‧‧First insulating layer

342‧‧‧Second insulating layer

3421‧‧‧First Opening

3422‧‧‧Second opening

3423‧‧‧Third opening

3424‧‧‧Fourth Opening

3425‧‧‧Fifth Opening

321‧‧‧The first electrode of the first electrical type

322‧‧‧Second first electrical type electrode

323‧‧‧The third electrode of the first electrical type

324‧‧‧The fourth electrode of the first electrical type

33‧‧‧Second electrical electrode

35‧‧‧Third electrode

B1‧‧‧First Long Side

B3‧‧‧Second Long Side

B2‧‧‧First Short Side

B4‧‧‧Second short side

351‧‧‧Long extensions

R‧‧‧notch

36‧‧‧Fourth electrode

800‧‧‧Lighting Module

501‧‧‧Download

502‧‧‧Carrier

503‧‧‧Upload carrier

504, 506, 508, 510‧‧‧Lens

512, 514‧‧‧Power supply terminal

515‧‧‧Through hole

519‧‧‧Reflector

521‧‧‧Adhesive

540‧‧‧Enclosure

900‧‧‧Light Source Generator

1000‧‧‧Bulbs

721‧‧‧Enclosure

722‧‧‧Lens

724‧‧‧Lighting Module

725‧‧‧Bracket

726‧‧‧Radiator

727‧‧‧Connections

728‧‧‧Electrical Connectors

ABC‧‧‧ direction

D1‧‧‧distance

H1, H2‧‧‧Height

Figure 1 is a structural diagram showing a side view of a conventional array optoelectronic device;

FIG. 2 is a schematic diagram showing the structure of a conventional light-emitting device;

FIG. 3A is a structural diagram showing a top-view structural diagram of a photoelectric element unit according to an embodiment of the present invention;

FIG. 3B is a structural diagram showing a side view of a photoelectric element unit according to an embodiment of the present invention;

FIG. 3C is a structural diagram showing a top-view structural diagram of a photoelectric element unit according to another embodiment of the present invention;

FIGS. 4A-4D are structural diagrams showing a top-view structural diagram of a photoelectric element unit according to another embodiment of the present invention;

5A-5C are schematic diagrams showing a light-emitting module;

6A-6B are schematic diagrams illustrating a light source generating device; and

FIG. 7 is a schematic diagram of a light bulb.

700‧‧‧Photoelectric Components

311‧‧‧First semiconductor layer

321‧‧‧The first electrode of the first electrical type

322‧‧‧Second first electrical type electrode

323‧‧‧The third electrode of the first electrical type

342‧‧‧Second insulating layer

3422‧‧‧Second opening

3423‧‧‧Third opening

3424‧‧‧Fourth Opening

35‧‧‧Third electrode

351‧‧‧Extensions

36‧‧‧Fourth electrode

Claims (10)

A photoelectric element, comprising: an epitaxial stack, including a first semiconductor layer, an active layer formed on the first semiconductor layer, and a second semiconductor layer formed on the active layer; a plurality of boundaries expose the a first semiconductor layer, two adjacent borders of the plurality of borders form a corner of the first semiconductor layer; a plurality of first electrical electrodes are formed on the first semiconductor layer exposed by the plurality of borders, Wherein the plurality of first first electrical type electrodes are separated from each other and are not surrounded by the second semiconductor layer; a third electrode is formed on the plurality of first first electrical type electrodes and the second semiconductor layer; and a plurality of fourth electrodes are formed on the second semiconductor layer; wherein, viewed from above, the third electrode includes at least two extension parts, and one of the plurality of fourth electrodes is located between the at least two extension parts or the One of at least two extension parts is located between the plurality of fourth electrodes. The optoelectronic device according to claim 1, wherein, viewed from above, the projection of any one of the plurality of first first electrical type electrodes on the first semiconductor layer comprises a figure, and the figure comprises a polygon , a circle, an ellipse or a semicircle. The optoelectronic device as described in item 1 of the claimed scope further comprises a plurality of second electrodes of the first electrical type formed on the first semiconductor layer and surrounded by the second semiconductor layer, wherein the plurality of second first electrical electrodes are formed on the first semiconductor layer and surrounded by the second semiconductor layer. An electrical electrode is separated from each other. The optoelectronic device according to claim 3, wherein when viewed from above, the projection of any one of the plurality of second first electrical type electrodes on the first semiconductor layer comprises a figure, and the figure comprises a polygon , a circle, an ellipse, a semicircle or a circular arc surface. The optoelectronic device according to claim 3, wherein, viewed from above, the projected areas of the plurality of second first electrical type electrodes on the first semiconductor layer are the same. The optoelectronic device as claimed in claim 3, wherein, viewed from above, the projected areas of the plurality of second first electrical type electrodes on the first semiconductor layer are different. The optoelectronic device according to claim 1, further comprising a second electrical electrode located between the third electrode and the second semiconductor layer, and the second electrical electrode is electrically connected to the second semiconductor layer and the plurality of fourth electrodes, and the plurality of fourth electrodes do not overlap with the third electrodes. The optoelectronic device of claim 3, wherein one of the plurality of second electrodes of the first electrical type is formed in the at least two extending portions. The optoelectronic device of claim 1, wherein the plurality of extending portions form a notch. The optoelectronic device according to claim 1, wherein, when viewed from above, a top-view area of one of the plurality of fourth electrodes is smaller than a top-view area of one of the third electrodes.

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