TWI739252B - Trench mosfet and manufacturing method of the same - Google Patents

Trench mosfet and manufacturing method of the same Download PDF

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TWI739252B
TWI739252B TW108147542A TW108147542A TWI739252B TW I739252 B TWI739252 B TW I739252B TW 108147542 A TW108147542 A TW 108147542A TW 108147542 A TW108147542 A TW 108147542A TW I739252 B TWI739252 B TW I739252B
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region
doping concentration
epitaxial layer
trench
conductivity type
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TW108147542A
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TW202125822A (en
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劉莒光
羅禕侖
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杰力科技股份有限公司
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Priority to TW108147542A priority Critical patent/TWI739252B/en
Priority to CN202010113782.5A priority patent/CN113035931B/en
Priority to US16/830,225 priority patent/US11588021B2/en
Publication of TW202125822A publication Critical patent/TW202125822A/en
Priority to US17/377,408 priority patent/US20210343840A1/en
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Publication of TWI739252B publication Critical patent/TWI739252B/en

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Abstract

A trench MOSFET and a manufacturing method of the same are provided. The trench MOSFET includes a substrate, an epitaxial layer with a first conductive type, a gate within a trench in the epitaxial layer, a gate oxide layer, a source region with the first conductive type, a body region and an anti-punch through region with a second conductive type. The anti-punch through region is disposed at the interface between the source region and the body region, and the doping concentration thereof is higher than that of the body region. The epitaxial layer has a first pn junction close to the source region and a second pn junction near the substrate. N regions are divided into N equally between the two pn junctions, and N is an integer greater than 1. The closer the N regions are to the first pn junction, the larger the doping concentration thereof is. Each of the N regions has an integrated area of a doping concentration to a depth of epitaxial layer, and the closer the N regions are to the first pn junction, the greater integrated area of a doping concentration to a depth of epitaxial layer is.

Description

溝槽式MOSFET元件及其製造方法 Trench type MOSFET element and manufacturing method thereof

本發明是有關於一種功率半導體元件，且特別是有關於一種溝槽式金氧半導體場效電晶體(MOSFET)元件及其製造方法。 The present invention relates to a power semiconductor device, and more particularly to a trench metal oxide semiconductor field effect transistor (MOSFET) device and a manufacturing method thereof.

在功率半導體元件中，垂直設置於溝槽的功率半導體元件因為能大幅增加單元密度，所以已成為各界發展的重點之一。 Among the power semiconductor components, the power semiconductor components vertically arranged in the trenches have become one of the focuses of development in all walks of life because they can greatly increase the cell density.

圖1是習知的一種溝槽式MOSFET元件的示意圖。在圖1中，基板100上的磊晶層102內有源極區104和本體(body)區106，而溝槽式閘極108則是設置於磊晶層102中，內層介電層(ILD)110覆蓋磊晶層102與溝槽式閘極108。另外，溝槽式閘極108表面會有閘氧化層112。 FIG. 1 is a schematic diagram of a conventional trench MOSFET device. In FIG. 1, the active region 104 and the body region 106 in the epitaxial layer 102 on the substrate 100, and the trench gate 108 is arranged in the epitaxial layer 102, the inner dielectric layer ( The ILD) 110 covers the epitaxial layer 102 and the trench gate 108. In addition, there is a gate oxide layer 112 on the surface of the trench gate 108.

圖2是沿著圖1的溝槽式閘極結構108的側壁108a的摻雜濃度曲線圖，其中顯示源極區104和本體區106之間的摻雜濃度分佈平緩，而使本體電阻(body resistance)變高。一旦本體電阻變高，將容易造成寄生N(源極104)-P(本體106)-N(磊晶層102)雙極性電晶體導通，MOSFET發生二次崩潰(Secondary breakdown)，使得元件溫度上升，造成元件永久損傷，即非箝制電感切換(Unclamped Inductive Switching,UIS)的性能變差。 2 is a graph showing the doping concentration along the sidewall 108a of the trench gate structure 108 of FIG. resistance) becomes high. Once the body resistance becomes high, it will easily cause the parasitic N (source 104)-P (body 106)-N (epitaxial layer 102) bipolar transistor to turn on, and the MOSFET will undergo secondary collapse (Secondary breakdown), which causes the component temperature to rise, causing permanent damage to the component, that is, the performance of Unclamped Inductive Switching (UIS) deteriorates.

本發明提供一種溝槽式MOSFET元件，其本體與源極之間設有特定摻雜濃度範圍的抗擊穿摻雜區(anti-punch through region)，能降低本體電阻率，藉此改善溝槽式MOSFET元件的UIS能力。 The present invention provides a trench-type MOSFET device, which is provided with an anti-punch through region with a specific doping concentration range between the body and the source, which can reduce the body resistivity, thereby improving the trench-type UIS capability of MOSFET components.

本發明另提供一種溝槽式MOSFET元件的製造方法，可使本體與源極之間產生高摻雜濃度區域，以降低本體電阻率(RS_Body)，以抑制寄生雙極性電晶體開啟。 The present invention also provides a method for manufacturing a trench MOSFET device, which can generate a high doping concentration region between the body and the source, so as to reduce the body resistivity (R S_Body ) to prevent the parasitic bipolar transistor from turning on.

本發明的溝槽式MOSFET元件，包括基板、具有第一導電型的磊晶層、閘極、閘氧化層、具有第一導電型的源極區、具有第二導電型的本體區與具有第二導電型的抗擊穿摻雜區。磊晶層係形成於基板上。磊晶層則具有溝槽，閘極位於所述溝槽內，閘氧化層位於閘極與溝槽之間。源極區是位於溝槽兩側的磊晶層的表面，本體區是位於源極區下方的部分磊晶層內，且抗擊穿摻雜區是位於本體區與源極區的界面，其中所述抗擊穿摻雜區的摻雜濃度高於本體區的摻雜濃度。所述磊晶層具有接近源極區的一個第一pn接面(pn junction)及接近基板的一個第二pn接面，且以第一pn接面與第二pn接面之間劃分為N等分的N個區域，N是大於1的整數。所述N個區域內的摻雜濃度愈接近第一pn接面愈 大。所述N個區域分別具有一摻雜濃度對於磊晶層深度之積分面積，且所述N個區域中愈接近第一pn接面的區域的摻雜濃度對於磊晶層深度之積分面積愈大。 The trench MOSFET device of the present invention includes a substrate, an epitaxial layer having a first conductivity type, a gate electrode, a gate oxide layer, a source region having a first conductivity type, a body region having a second conductivity type, and a body region having a first conductivity type. Two conductivity type anti-breakdown doped regions. The epitaxial layer is formed on the substrate. The epitaxial layer has a trench, the gate is located in the trench, and the gate oxide layer is located between the gate and the trench. The source region is the surface of the epitaxial layer located on both sides of the trench, the body region is located in the part of the epitaxial layer below the source region, and the anti-breakdown doped region is located at the interface between the body region and the source region. The doping concentration of the anti-breakdown doped region is higher than the doping concentration of the body region. The epitaxial layer has a first pn junction (pn junction) close to the source region and a second pn junction close to the substrate, and the first pn junction and the second pn junction are divided into N N equally divided regions, where N is an integer greater than 1. The doping concentration in the N regions is closer to the first pn junction, the more Big. Each of the N regions has an integrated area of doping concentration for the depth of the epitaxial layer, and the region closer to the first pn junction among the N regions has a larger integrated area for the depth of the epitaxial layer. .

在本發明的一實施例中，上述N為2，且所述N個區域包括接近第一pn接面的第一區域與接近第二pn接面的第二區域，所述第一區域內的摻雜濃度均大於所述第二區域內的摻雜濃度，所述第一區域的所述摻雜濃度對於磊晶層深度之積分面積大於所述第二區域的所述摻雜濃度對於磊晶層深度之積分面積。 In an embodiment of the present invention, the above N is 2, and the N regions include a first region close to the first pn junction and a second region close to the second pn junction. The doping concentration is greater than the doping concentration in the second region, and the integrated area of the doping concentration in the first region with respect to the depth of the epitaxial layer is greater than the doping concentration in the second region with respect to the epitaxial layer. The integral area of the layer depth.

在本發明的一實施例中，上述N為3，且所述N個區域包括接近第一pn接面的第一區域、接近第二pn接面的第三區域與介於第一區域與第三區域之間的第二區域，所述第一區域內的摻雜濃度均大於所述第二區域內的摻雜濃度、所述第二區域內的摻雜濃度均大於所述第三區域內的摻雜濃度，且所述第一區域的所述摻雜濃度對於磊晶層深度之積分面積大於所述第二區域的所述摻雜濃度對於磊晶層深度之積分面積，所述第二區域的所述摻雜濃度對於磊晶層深度之積分面積大於所述第三區域的所述摻雜濃度對於磊晶層深度之積分面積。 In an embodiment of the present invention, the above N is 3, and the N regions include a first region close to the first pn junction, a third region close to the second pn junction, and between the first region and the first region. In the second region between the three regions, the doping concentration in the first region is all greater than the doping concentration in the second region, and the doping concentration in the second region is all greater than that in the third region And the integrated area of the doping concentration of the first region with respect to the depth of the epitaxial layer is greater than the integrated area of the doping concentration of the second region with respect to the depth of the epitaxial layer, the second The integrated area of the doping concentration of the region with respect to the depth of the epitaxial layer is greater than the integrated area of the doping concentration of the third region with respect to the depth of the epitaxial layer.

本發明的溝槽式MOSFET元件的製造方法，包括在一基板上的具有第一導電型的磊晶層內形成溝槽式閘極；以植入劑量往所述基板的方向逐漸減少的方式，對所述磊晶層進行多道植入具有第二導電型的摻雜物的步驟；進行第一驅入(drive-in)步驟，使具有所述第二導電型的所述摻雜物在所述磊晶層的上半部擴 散，形成具有所述第二導電型的本體區；在所述磊晶層的表面植入具有所述第一導電型的摻雜物；進行第二驅入步驟，使具有所述第一導電型的所述摻雜物擴散形成源極區；以及在形成所述源極區之後，在本體區與源極區的界面全面地植入具有第二導電型的摻雜物，以形成一抗擊穿摻雜區，其中所述抗擊穿摻雜區的摻雜濃度高於所述本體區的摻雜濃度。 The manufacturing method of the trench MOSFET device of the present invention includes forming a trench gate in an epitaxial layer with a first conductivity type on a substrate; and the implant dose is gradually reduced toward the substrate. A step of implanting a dopant having the second conductivity type in multiple passes is performed on the epitaxial layer; a first drive-in step is performed to make the dopant having the second conductivity type in The upper half of the epitaxial layer is expanded Dispersing, forming a body region with the second conductivity type; implanting dopants with the first conductivity type on the surface of the epitaxial layer; Type the dopant diffuses to form a source region; and after forming the source region, a dopant with the second conductivity type is implanted in the interface between the body region and the source region to form a resist The penetration doping region, wherein the doping concentration of the anti-breakdown doping region is higher than the doping concentration of the body region.

在本發明的另一實施例中，上述進行多道植入具有第二導電型的摻雜物的步驟包括兩道或三道植入步驟。 In another embodiment of the present invention, the above-mentioned step of multiple implantation of the dopant having the second conductivity type includes two or three implantation steps.

在本發明的另一實施例中，上述植入具有第一導電型的摻雜物的能量例如在20KeV~45KeV之間。 In another embodiment of the present invention, the energy for implanting the dopant having the first conductivity type is, for example, between 20 KeV and 45 KeV.

在本發明的另一實施例中，上述第二驅入步驟包括快速熱處理(RTP)。 In another embodiment of the present invention, the above-mentioned second drive-in step includes rapid thermal processing (RTP).

在本發明的另一實施例中，形成上述溝槽式閘極的步驟包括：在上述磊晶層先形成溝槽，在所述溝槽的表面形成閘氧化層，再在上述溝槽內沉積導體作為閘極。 In another embodiment of the present invention, the step of forming the trench gate includes: first forming a trench in the epitaxial layer, forming a gate oxide layer on the surface of the trench, and then depositing the trench in the trench The conductor acts as a gate.

在本發明的各個實施例中，上述抗擊穿摻雜區的摻雜濃度介於5E+16原子/cm3~5E+17原子/cm3。 In various embodiments of the present invention, the doping concentration of the anti-breakdown doped region ranges from 5E+16 atoms/cm 3 to 5E+17 atoms/cm 3 .

在本發明的各個實施例中，上述第一導電型為N型，上述第二導電型為P型。 In various embodiments of the present invention, the first conductivity type is N-type, and the second conductivity type is P-type.

在本發明的各個實施例中，上述第一導電型為P型，上述第二導電型為N型。 In each embodiment of the present invention, the first conductivity type is P type, and the second conductivity type is N type.

基於上述，本發明藉由本體與源極之間形成的抗擊穿摻 雜區，使該處具有陡峭的濃度分佈並因而降低本體電阻率，以抑制寄生雙極性電晶體開啟，改善溝槽式MOSFET元件的UIS能力。 Based on the above, the present invention uses the anti-breakdown doping formed between the body and the source. The impurity area has a steep concentration distribution there and thus reduces the body resistivity, so as to prevent the parasitic bipolar transistor from turning on and improve the UIS capability of the trench MOSFET device.

為讓本發明的上述特徵和優點能更明顯易懂，下文特舉實施例，並配合所附圖式作詳細說明如下。 In order to make the above-mentioned features and advantages of the present invention more comprehensible, the following specific embodiments are described in detail in conjunction with the accompanying drawings.

100、300:基板 100, 300: substrate

102、302:磊晶層 102, 302: epitaxial layer

104、304:源極區 104, 304: source region

106、306:本體區 106, 306: body area

108:溝槽式閘極 108: grooved gate

108a:側壁 108a: sidewall

110、316:內層介電層 110, 316: inner dielectric layer

112、310:閘氧化層 112, 310: gate oxide layer

302a:表面 302a: Surface

308:閘極 308: Gate

312:抗擊穿摻雜區 312: Anti-breakdown doped region

314:溝槽 314: Groove

400a:第一pn接面 400a: first pn junction

400b:第二pn接面 400b: second pn junction

404a、500a:第一區域 404a, 500a: the first area

404b、500b:第二區域 404b, 500b: second area

500c:第三區域 500c: third area

S600、S602、S604、S606、S608、S610:步驟 S600, S602, S604, S606, S608, S610: steps

圖1是習知的一種溝槽式MOSFET元件的示意圖。 FIG. 1 is a schematic diagram of a conventional trench MOSFET device.

圖2是沿著圖1的溝槽式閘極結構的側壁的摻雜濃度曲線圖 FIG. 2 is a graph of doping concentration along the sidewall of the trench gate structure of FIG. 1

圖3是依照本發明的第一實施例的一種溝槽式MOSFET元件的示意圖。 FIG. 3 is a schematic diagram of a trench MOSFET device according to the first embodiment of the present invention.

圖4是沿著圖3的溝槽式閘極結構的側壁的一種摻雜濃度曲線圖。 FIG. 4 is a graph of a doping concentration along the sidewall of the trench gate structure of FIG. 3.

圖5是沿著圖3的溝槽式閘極結構的側壁的另一種摻雜濃度曲線圖。 FIG. 5 is another graph of doping concentration along the sidewall of the trench gate structure of FIG. 3.

圖6是依照本發明的第二實施例的一種溝槽式MOSFET元件的製造流程步驟圖。 6 is a step diagram of a manufacturing process of a trench MOSFET device according to a second embodiment of the present invention.

以下揭示內容提供許多不同的實施方式或範例，用於實施本發明的不同特徵。當然這些實施例僅為範例，並非用於限制本發明的範圍與應用。再者，為了清楚起見，各個構件、膜層或 區域的相對厚度及位置可能縮小或放大。另外，在各圖式中使用相似或相同的元件符號來標示相似或相同元件或特徵，且圖式中如有與前一圖相同的元件符號，則將省略其贅述。 The following disclosure provides many different implementations or examples for implementing different features of the present invention. Of course, these embodiments are only examples, and are not intended to limit the scope and application of the present invention. Furthermore, for the sake of clarity, each member, layer or The relative thickness and location of the area may be reduced or enlarged. In addition, similar or identical element symbols are used in the various drawings to indicate similar or identical elements or features, and if there are elements in the drawings that are the same as the previous figure, their description will be omitted.

圖3是依照本發明的第一實施例的一種溝槽式MOSFET元件的示意圖。 FIG. 3 is a schematic diagram of a trench MOSFET device according to the first embodiment of the present invention.

請參照圖3，第一實施例的溝槽式MOSFET元件包括基板300、具有第一導電型的磊晶層302、具有第一導電型的源極區304、具有第二導電型的本體區306、閘極308、閘氧化層310與具有第二導電型的抗擊穿摻雜區312。在本實施例中，第一導電型為N型，第二導電型為P型。但是本發明並不限於此，於另一實施例中，第一導電型可為P型，第二導電型可為N型。磊晶層302係形成於基板300上，且磊晶層302具有溝槽314。雖然圖3只顯示一個溝槽314，但是應知用於功率裝置的溝槽式MOSFET元件實際上具有多個溝槽314。 3, the trench MOSFET device of the first embodiment includes a substrate 300, an epitaxial layer 302 with a first conductivity type, a source region 304 with a first conductivity type, and a body region 306 with a second conductivity type. , The gate 308, the gate oxide layer 310 and the anti-breakdown doped region 312 with the second conductivity type. In this embodiment, the first conductivity type is N type, and the second conductivity type is P type. However, the present invention is not limited to this. In another embodiment, the first conductivity type may be P-type, and the second conductivity type may be N-type. The epitaxial layer 302 is formed on the substrate 300, and the epitaxial layer 302 has a trench 314. Although FIG. 3 only shows one trench 314, it should be understood that the trench MOSFET device used in a power device actually has a plurality of trenches 314.

請繼續參照圖3，閘極308位於溝槽314內，且閘氧化層310位於閘極308與溝槽314之間。源極區304是位於溝槽314兩側的磊晶層302的表面302a，本體區306則是位於源極區304下方的部分磊晶層302內。一般來說，磊晶層302若是N型磊晶，則源極區304是N+區。抗擊穿摻雜區312則是位於本體區306與源極區304的界面，其中抗擊穿摻雜區312的摻雜濃度需高於本體區306的摻雜濃度。也就是說，相對於本體區306若是P型井區，則抗擊穿摻雜區312是P+區。在一實施例中，抗擊穿摻雜區312的摻雜濃度例如介於5E+16 原子/cm3~5E+17原子/cm3。此外，可形成一內層介電層316覆蓋磊晶層302與閘極308。 Please continue to refer to FIG. 3, the gate 308 is located in the trench 314, and the gate oxide layer 310 is located between the gate 308 and the trench 314. The source region 304 is the surface 302 a of the epitaxial layer 302 located on both sides of the trench 314, and the body region 306 is located in the part of the epitaxial layer 302 under the source region 304. Generally speaking, if the epitaxial layer 302 is an N-type epitaxy, the source region 304 is an N+ region. The breakdown-resistant doped region 312 is located at the interface between the body region 306 and the source region 304, and the doped concentration of the breakdown-resistant doped region 312 needs to be higher than the doped concentration of the body region 306. In other words, if the body region 306 is a P-type well region, the breakdown-resistant doped region 312 is a P+ region. In one embodiment, the doping concentration of the anti-breakdown doped region 312 is, for example, between 5E+16 atoms/cm 3 to 5E+17 atoms/cm 3 . In addition, an inner dielectric layer 316 can be formed to cover the epitaxial layer 302 and the gate electrode 308.

圖4是沿著圖3的溝槽式閘極結構的側壁的一種摻雜濃度曲線圖。 FIG. 4 is a graph of a doping concentration along the sidewall of the trench gate structure of FIG. 3.

在圖4中，磊晶層具有接近源極區304的一個第一pn接面(pn junction)400a以及接近基板300的一個第二pn接面400b，且以第一pn接面400a與第二pn接面400b之間劃分為2個等分，接近第一pn接面400a的設為第一區域404a、接近第二pn接面400b的設為第二區域404b。然而本發明並不限於此，第一pn接面400a與第二pn接面400b之間可劃分為N等份，N除了2以外也可以是大於1的其他整數。在圖4中，所述第一區域404a內的摻雜濃度均大於第二區域404b內的摻雜濃度，且第一區域404a具有一第一摻雜濃度對於磊晶層深度之積分面積、第二區域404b具有一第二摻雜濃度對於磊晶層深度之積分面積，所述第一摻雜濃度對於磊晶層深度之積分面積大於所述第二摻雜濃度對於磊晶層深度之積分面積。而且位於本體區306與源極區304的界面的抗擊穿摻雜區312具有陡峭的濃度分佈，使得此處的本體電阻率變低，進而改善溝槽式MOSFET元件的UIS能力。也就是說，本發明中的上述區域內的摻雜濃度愈接近第一pn接面400a愈大，愈接近第一pn接面400a的區域的摻雜濃度對於磊晶層深度之積分面積也愈大。關於這樣特別的摻雜濃度分佈的製作方式，將於下文描述。 4, the epitaxial layer has a first pn junction (pn junction) 400a close to the source region 304 and a second pn junction 400b close to the substrate 300, and the first pn junction 400a and the second pn junction 400a The pn junction 400b is divided into two equal parts, and the area close to the first pn junction 400a is set as the first area 404a, and the area close to the second pn junction 400b is set as the second area 404b. However, the present invention is not limited to this. The first pn junction 400a and the second pn junction 400b can be divided into N equal parts. In addition to 2, N can also be other integers greater than 1. In FIG. 4, the doping concentration in the first region 404a is greater than the doping concentration in the second region 404b, and the first region 404a has an integral area of the first doping concentration with respect to the depth of the epitaxial layer, the second The second region 404b has an integrated area of the second doping concentration with respect to the depth of the epitaxial layer, and the integrated area of the first doping concentration with respect to the depth of the epitaxial layer is greater than the integrated area of the second doping concentration with respect to the depth of the epitaxial layer . Moreover, the breakdown-resistant doped region 312 located at the interface between the body region 306 and the source region 304 has a steep concentration distribution, so that the body resistivity here becomes lower, thereby improving the UIS capability of the trench MOSFET device. That is to say, the doping concentration in the above-mentioned region in the present invention is closer to the first pn junction 400a, and the doping concentration in the region closer to the first pn junction 400a is also greater for the integrated area of the epitaxial layer depth. Big. The manufacturing method of such a special doping concentration distribution will be described below.

圖5是圖3的元件的溝槽側壁的另一種摻雜濃度曲線圖，其中使用與圖4相同的元件符號來表示相同或近似的區域，且相同或近似的區域內容也可參照上述，不再贅述。 FIG. 5 is another doping concentration curve diagram of the trench sidewall of the device of FIG. 3, in which the same component symbols as in FIG. 4 are used to denote the same or similar regions, and the content of the same or similar regions can also be referred to above. Go into details again.

在圖5中與圖4不同的地方在於，第一pn接面400a與第二pn接面400b之間劃分為3等分，即包含接近第一pn接面400a的第一區域500a、接近第二pn接面400b的第三區域500c與介於第一區域500a與第三區域500c之間的第二區域500b。第一區域500a內的摻雜濃度均大於第二區域500b內的摻雜濃度、第二區域500b內的摻雜濃度均大於第三區域500c內的摻雜濃度，且第一區域500a的摻雜濃度對於磊晶層深度之積分面積大於第二區域500b的摻雜濃度對於磊晶層深度之積分面積，第二區域500b的摻雜濃度對於磊晶層深度之積分面積大於第三區域500c的摻雜濃度對於磊晶層深度之積分面積。所述摻雜濃度分佈的製作方式，也會於下文描述。 The difference between FIG. 5 and FIG. 4 is that the first pn junction 400a and the second pn junction 400b are divided into three equal parts, that is, the first area 500a close to the first pn junction 400a and the first area 500a close to the first pn junction 400a are included. The third area 500c of the two pn junction 400b and the second area 500b between the first area 500a and the third area 500c. The doping concentration in the first region 500a is greater than the doping concentration in the second region 500b, the doping concentration in the second region 500b is greater than the doping concentration in the third region 500c, and the doping concentration in the first region 500a The integrated area of the concentration for the depth of the epitaxial layer is greater than the integrated area of the doping concentration of the second region 500b for the depth of the epitaxial layer, and the integrated area of the doping concentration of the second region 500b for the depth of the epitaxial layer is greater than that of the third region 500c The integrated area of the impurity concentration with respect to the depth of the epitaxial layer. The manufacturing method of the doping concentration distribution will also be described below.

圖6是依照本發明的第二實施例的一種溝槽式MOSFET元件的製造流程步驟圖。而且，根據第二實施例的步驟，可製作出如圖4或圖5的的摻雜濃度分佈。 6 is a step diagram of a manufacturing process of a trench MOSFET device according to a second embodiment of the present invention. Moreover, according to the steps of the second embodiment, the doping concentration distribution as shown in FIG. 4 or FIG. 5 can be produced.

請參照圖6，先進行步驟S600，在一基板上的具有第一導電型的磊晶層內形成溝槽式閘極。在本實施例中，上述第一導電型為N型，第二導電型為P型；反之亦然。形成溝槽式閘極的步驟可列舉但不限於：在N型磊晶層先形成溝槽，在溝槽的表面形成閘氧化層，再在溝槽內沉積導體作為閘極，其中所述導體例如多晶矽。 Please refer to FIG. 6, step S600 is first performed to form a trench gate in the epitaxial layer with the first conductivity type on a substrate. In this embodiment, the above-mentioned first conductivity type is N-type, and the second conductivity type is P-type; and vice versa. The steps of forming the trench gate include but are not limited to: first forming a trench in the N-type epitaxial layer, forming a gate oxide layer on the surface of the trench, and then depositing a conductor in the trench as the gate, wherein the conductor For example, polysilicon.

接著，在步驟S602中，以植入劑量往基板的方向逐漸減少的方式，對磊晶層進行多道植入具有第二導電型的摻雜物的步驟；在本實施例中，上述植入步驟可為兩道或三道植入P型的摻雜物的步驟。 Next, in step S602, the epitaxial layer is implanted with the dopant having the second conductivity type in a manner that the implant dose gradually decreases toward the substrate; in this embodiment, the above-mentioned implantation The steps can be two or three steps of implanting P-type dopants.

然後，在步驟S604中，進行第一驅入(drive-in)步驟，使上述P型摻雜物在N型磊晶層的上半部擴散，形成P型本體區。而且，為避免源極區底部趨近平緩的N型濃度與本體區平緩的P型濃度，在第一pn接面處相互抵消彼此的濃度，導致本體區的電阻率增加，本發明的製程藉由降低熱裕度(thermal budget)，使本體區的摻雜濃度分佈接近步驟S602的植入步驟後的濃度分佈。舉例來說，若是習知的驅入步驟是高溫長時間的製程(如高於1000℃一小時)，則步驟S604則是採取高溫短時間(如高於1000℃ 30分鐘以下)或者採取同時降低溫度與縮短時間(如1000℃以下且短於一小時)的驅入。也就是說，當步驟S602的植入步驟是兩道，則所形成的本體區的雜濃度分佈如圖4所示；另一方面，若是步驟S602的植入步驟是三道，則所形成的本體區的摻雜濃度分佈會如圖5所示。 Then, in step S604, a first drive-in step is performed to diffuse the above-mentioned P-type dopant in the upper half of the N-type epitaxial layer to form a P-type body region. Moreover, in order to avoid the near-flat N-type concentration at the bottom of the source region and the flat P-type concentration in the body region, the concentrations at the first pn junction cancel each other out, resulting in an increase in the resistivity of the body region. The process of the present invention uses By reducing the thermal budget, the doping concentration distribution of the body region is close to the concentration distribution after the implantation step of step S602. For example, if the conventional drive-in step is a high-temperature and long-term process (such as one hour higher than 1000°C), step S604 is to adopt a high-temperature short time (such as higher than 1000°C and less than 30 minutes) or adopt simultaneous reduction Drive in with temperature and shortened time (such as below 1000°C and less than one hour). That is to say, when the implantation steps of step S602 are two, the impurity concentration distribution of the formed body region is shown in FIG. 4; on the other hand, if the implantation steps of step S602 are three, the formed The doping concentration distribution of the body region will be as shown in FIG. 5.

隨後，在步驟S606中，在磊晶層的表面植入具有第一導電型(如N型)的摻雜物。而且，為了後續所形成的源極區具有較陡峭的摻雜濃度分佈，上述植入步驟的能量要比習知形成源極區所進行的植入要低，例如在20KeV~45KeV之間。然而，本發並不限於此。依據溝槽式MOSFET元件的設計準則，上述植入步驟的能量可進行變更。 Subsequently, in step S606, dopants having the first conductivity type (such as N-type) are implanted on the surface of the epitaxial layer. Moreover, in order to have a steeper doping concentration distribution in the source region to be formed later, the energy of the above-mentioned implantation step is lower than that of the conventional implantation for forming the source region, for example, between 20KeV and 45KeV. However, the present invention is not limited to this. According to the design criteria of the trench MOSFET device, the energy of the above-mentioned implantation step can be changed.

之後，在步驟S608中，進行第二驅入步驟，使具有第一導電型(如N型)的摻雜物擴散形成源極區。同樣地，為了使源極區具有較陡峭的摻雜濃度分佈，本發明的製程需進一步降低熱裕度，因此第二驅入步驟的時間要比習知的驅入步驟短，例如在5分鐘以下。舉例來說，第二驅入步驟可採用快速熱處理(RTP)。 After that, in step S608, a second drive-in step is performed to diffuse dopants having the first conductivity type (such as N-type) to form a source region. Similarly, in order to make the source region have a steeper doping concentration distribution, the process of the present invention needs to further reduce the thermal margin. Therefore, the time of the second drive-in step is shorter than that of the conventional drive-in step, for example, in 5 minutes. the following. For example, the second drive-in step may use rapid thermal processing (RTP).

然後，在步驟S608之後再進行步驟S610，在不需要任何光阻遮罩的情況下，在本體區與源極區的界面全面地植入具有第二導電型(如P型)的摻雜物，以形成抗擊穿摻雜區，其中所述抗擊穿摻雜區的摻雜濃度高於本體區的摻雜濃度，且後續將不再進行高溫的驅入步驟，使得本體區與源極區的界面形成陡峭的濃度分佈，如圖4與圖5中第一pn接面400a左側(往源極區304)的直線。在本實施例中，抗擊穿摻雜區的摻雜濃度例如介於5E+16原子/cm3~5E+17原子/cm3。然而，本發並不限於此。根據本體區的摻雜濃度大小，抗擊穿摻雜區的摻雜濃度也可作變更。後續的製程可按照既有技術進行，故不贅述。 Then, step S610 is performed after step S608. Without any photoresist mask, the interface between the body region and the source region is fully implanted with dopants with the second conductivity type (such as P-type) , To form an anti-breakdown doped region, wherein the dopant concentration of the anti-breakdown doped region is higher than that of the body region, and subsequent high-temperature driving steps will not be performed, so that the body region and the source region are The interface forms a steep concentration distribution, such as a straight line on the left side (toward the source region 304) of the first pn junction 400a in FIGS. 4 and 5. In this embodiment, the doping concentration of the anti-breakdown doped region is, for example, between 5E+16 atoms/cm 3 to 5E+17 atoms/cm 3 . However, the present invention is not limited to this. According to the doping concentration of the body region, the doping concentration of the anti-breakdown doped region can also be changed. The subsequent manufacturing process can be carried out according to the existing technology, so it will not be repeated.

綜上所述，本發明藉由製程的控制在本體與源極之間形成特別的摻雜濃度分佈，而降低本體電阻率，並藉此改善溝槽式MOSFET元件的UIS能力。 In summary, the present invention forms a special doping concentration distribution between the body and the source through the control of the process, thereby reducing the body resistivity and thereby improving the UIS capability of the trench MOSFET device.

雖然本發明已以實施例揭露如上，然其並非用以限定本發明，任何所屬技術領域中具有通常知識者，在不脫離本發明的精神和範圍內，當可作些許的更動與潤飾，故本發明的保護範圍當視後附的申請專利範圍所界定者為準。 Although the present invention has been disclosed in the above embodiments, it is not intended to limit the present invention. Anyone with ordinary knowledge in the relevant technical field can make some changes and modifications without departing from the spirit and scope of the present invention. The protection scope of the present invention shall be subject to those defined by the attached patent application scope.

300:基板 300: substrate

304:源極區 304: source region

306:本體區 306: body area

312:抗擊穿摻雜區 312: Anti-breakdown doped region

400a:第一pn接面 400a: first pn junction

400b:第二pn接面 400b: second pn junction

404a:第一區域 404a: The first area

404b:第二區域 404b: second area

Claims (14)

一種溝槽式MOSFET元件，包括：基板；具有第一導電型的磊晶層，形成於所述基板上，且所述磊晶層具有溝槽；閘極，位於所述溝槽內；閘氧化層，位於所述閘極與所述溝槽之間；具有所述第一導電型的源極區，位於所述溝槽兩側的所述磊晶層的表面；具有第二導電型的本體區，位於所述源極區下方的部分所述磊晶層內；以及具有所述第二導電型的抗擊穿摻雜區，位於所述本體區與所述源極區的界面，其中所述抗擊穿摻雜區的摻雜濃度高於所述本體區的摻雜濃度，其中所述磊晶層具有接近所述源極區的一第一pn接面以及接近所述基板的一第二pn接面，且以所述第一pn接面與所述第二pn接面之間劃分為N等分的N個區域，N是大於1的整數，其中所述N個區域內的摻雜濃度愈接近所述第一pn接面愈大，且其中所述N個區域分別具有一摻雜濃度對於磊晶層深度之積分面積，且所述N個區域中愈接近所述第一pn接面的區域的所述摻雜濃度對於磊晶層深度之積分面積愈大。 A trench type MOSFET device includes: a substrate; an epitaxial layer having a first conductivity type formed on the substrate, and the epitaxial layer has a trench; a gate electrode located in the trench; gate oxide A layer located between the gate and the trench; a source region with the first conductivity type located on the surface of the epitaxial layer on both sides of the trench; a body with a second conductivity type Region located in a portion of the epitaxial layer below the source region; and a breakdown-resistant doped region having the second conductivity type located at the interface between the body region and the source region, wherein the The doping concentration of the anti-breakdown doped region is higher than the doping concentration of the body region, wherein the epitaxial layer has a first pn junction close to the source region and a second pn close to the substrate Junction, and divided into N equally divided N regions between the first pn junction and the second pn junction, where N is an integer greater than 1, wherein the doping concentration in the N regions The closer to the first pn junction, the larger, and wherein the N regions each have an integral area of doping concentration with respect to the depth of the epitaxial layer, and the closer the N regions are to the first pn junction The integrated area of the doping concentration of the region with respect to the depth of the epitaxial layer is greater. 如申請專利範圍第1項所述的溝槽式MOSFET元件，其中所述抗擊穿摻雜區的摻雜濃度介於5E+16原子/cm3~5E+17原子/cm3。 In the trench MOSFET device described in item 1 of the scope of the patent application, the doping concentration of the anti-breakdown doped region ranges from 5E+16 atoms/cm 3 to 5E+17 atoms/cm 3 . 如申請專利範圍第1項所述的溝槽式MOSFET元件，其中N為2，且所述N個區域包括接近所述第一pn接面的第一區域與接近所述第二pn接面的第二區域，所述第一區域內的摻雜濃度均大於所述第二區域內的摻雜濃度，所述第一區域的所述摻雜濃度對於磊晶層深度之積分面積大於所述第二區域的所述摻雜濃度對於磊晶層深度之積分面積。 The trench MOSFET device described in the first item of the scope of patent application, wherein N is 2, and the N regions include a first region close to the first pn junction and a first region close to the second pn junction In the second region, the doping concentration in the first region is greater than the doping concentration in the second region, and the integrated area of the doping concentration in the first region with respect to the depth of the epitaxial layer is greater than that in the first region The integrated area of the doping concentration of the two regions with respect to the depth of the epitaxial layer. 如申請專利範圍第1項所述的溝槽式MOSFET元件，其中N為3，且所述N個區域包括接近所述第一pn接面的第一區域、接近所述第二pn接面的第三區域與介於所述第一區域與所述第三區域之間的第二區域，所述第一區域內的摻雜濃度均大於所述第二區域內的摻雜濃度、所述第二區域內的摻雜濃度均大於所述第三區域內的摻雜濃度，且所述第一區域的所述摻雜濃度對於磊晶層深度之積分面積大於所述第二區域的所述摻雜濃度對於磊晶層深度之積分面積，所述第二區域的所述摻雜濃度對於磊晶層深度之積分面積大於所述第三區域的所述摻雜濃度對於磊晶層深度之積分面積。 The trench MOSFET device described in the first item of the scope of patent application, wherein N is 3, and the N regions include a first region close to the first pn junction and a region close to the second pn junction. In the third region and the second region between the first region and the third region, the doping concentration in the first region is greater than the doping concentration in the second region, and the doping concentration in the second region The doping concentration in the two regions is greater than the doping concentration in the third region, and the integrated area of the doping concentration in the first region with respect to the depth of the epitaxial layer is greater than the doping concentration in the second region The integrated area of the impurity concentration with respect to the depth of the epitaxial layer, and the integrated area of the doping concentration in the second region with respect to the depth of the epitaxial layer is greater than the integrated area of the doping concentration in the third region with respect to the depth of the epitaxial layer . 如申請專利範圍第1項所述的溝槽式MOSFET元件，其中所述第一導電型為N型，所述第二導電型為P型。 In the trench MOSFET device described in the first item of the scope of patent application, the first conductivity type is N-type, and the second conductivity type is P-type. 如申請專利範圍第1項所述的溝槽式MOSFET元件，其中所述第一導電型為P型，所述第二導電型為N型。 In the trench MOSFET device described in the first item of the scope of patent application, the first conductivity type is P-type, and the second conductivity type is N-type. 一種溝槽式MOSFET元件的製造方法，包括：在一基板上的具有第一導電型的磊晶層內形成溝槽式閘極；以植入劑量往所述基板的方向逐漸減少的方式，對所述磊晶層進行多數道植入具有第二導電型的摻雜物的步驟；進行第一驅入(drive-in)步驟，使具有所述第二導電型的所述摻雜物在所述磊晶層的上半部擴散，形成具有所述第二導電型的本體(body)區；在所述磊晶層的表面植入具有所述第一導電型的摻雜物；進行第二驅入步驟，使具有所述第一導電型的所述摻雜物擴散形成源極區；以及在形成所述源極區之後，在所述本體區與所述源極區的界面全面地植入具有所述第二導電型的摻雜物，以形成一抗擊穿摻雜區，其中所述抗擊穿摻雜區的摻雜濃度高於所述本體區的摻雜濃度。 A method for manufacturing a trench MOSFET element includes: forming a trench gate in an epitaxial layer with a first conductivity type on a substrate; The epitaxial layer undergoes a plurality of steps of implanting dopants with the second conductivity type; a first drive-in step is performed to make the dopants with the second conductivity type in the The upper half of the epitaxial layer is diffused to form a body region having the second conductivity type; implanting dopants having the first conductivity type on the surface of the epitaxial layer; performing a second In the driving step, the dopant having the first conductivity type is diffused to form a source region; and after the source region is formed, the interface between the body region and the source region is fully implanted Dopants with the second conductivity type are introduced to form an anti-breakdown doped region, wherein the dopant concentration of the anti-breakdown doped region is higher than the dopant concentration of the body region. 如申請專利範圍第7項所述的溝槽式MOSFET元件的製造方法，其中所述多數道植入具有第二導電型的摻雜物的步驟包括兩道或三道植入具有所述第二導電型的摻雜物的步驟。 According to the manufacturing method of the trench type MOSFET device described in the scope of patent application, the step of implanting the dopant having the second conductivity type in a plurality of passes includes two or three passes of implanting the dopant having the second conductivity type. Conductive dopant step. 如申請專利範圍第7項所述的溝槽式MOSFET元件的製造方法，其中所述抗擊穿摻雜區的摻雜濃度介於5E+16原子/cm3~5E+17原子/cm3。 According to the manufacturing method of the trench MOSFET device described in item 7 of the scope of patent application, the doping concentration of the anti-breakdown doped region ranges from 5E+16 atoms/cm 3 to 5E+17 atoms/cm 3 . 如申請專利範圍第7項所述的溝槽式MOSFET元件的製造方法，其中所述第一導電型為N型，所述第二導電型為P型。 According to the manufacturing method of the trench MOSFET device described in the scope of the patent application, the first conductivity type is N type, and the second conductivity type is P type. 如申請專利範圍第7項所述的溝槽式MOSFET元件的製造方法，其中所述第一導電型為P型，所述第二導電型為N型。 According to the method for manufacturing a trench MOSFET device described in the scope of the patent application, the first conductivity type is P type, and the second conductivity type is N type. 如申請專利範圍第7項所述的溝槽式MOSFET元件的製造方法，其中所述植入具有所述第一導電型的摻雜物的能量在20KeV~45KeV之間。 According to the manufacturing method of the trench MOSFET device described in the scope of the patent application, the energy of the implantation of the dopant having the first conductivity type is between 20 KeV and 45 KeV. 如申請專利範圍第7項所述的溝槽式MOSFET元件的製造方法，其中所述第二驅入步驟包括快速熱處理(RTP)。 According to the manufacturing method of the trench MOSFET device described in claim 7, wherein the second drive-in step includes rapid thermal processing (RTP). 如申請專利範圍第7項所述的溝槽式MOSFET元件的製造方法，其中形成所述溝槽式閘極的步驟包括：在所述磊晶層形成溝槽；在所述溝槽的表面形成閘氧化層；以及在所述溝槽內沉積導體作為閘極。 The method for manufacturing a trench MOSFET device according to the seventh of the scope of patent application, wherein the step of forming the trench gate includes: forming a trench in the epitaxial layer; and forming a trench on the surface of the trench A gate oxide layer; and depositing a conductor in the trench as a gate electrode.
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TW108147542A TWI739252B (en) 2019-12-25 2019-12-25 Trench mosfet and manufacturing method of the same
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