TWI718245B - Integrated circuits, computer-implemented method of manufacturing the same, and standard cell defining the same - Google Patents

Abstract

Provided are integrated circuits, a computer-implemented method of manufacturing the same, and a standard cell defining the same. The computer-implemented method of manufacturing an integrated circuit includes placing a plurality of standard cells that define the integrated circuit, selecting a timing critical path from among a plurality of timing paths included in the placed standard cells, and selecting at least one net from among a plurality of nets included in the timing critical path as at least one timing critical net. The method further includes pre-routing the at least one timing critical net with an air-gap layer, routing unselected nets, generating a layout using the pre-routed at least one timing critical net and the routed unselected nets, and manufacturing the integrated circuit based on the layout.

Description

Integrated circuit, computer implementation method for manufacturing it, and standard components that define it

This application claims the priority of Korean Patent Application No. 10-2016-0015820 filed on February 11, 2016 and Korean Patent Application No. 10-2016-0100122 filed on August 5, 2016 , The disclosed content of the application case is incorporated into this case for reference.

The exemplary embodiment of the inventive concept relates to an integrated circuit, and more specifically, to an integrated circuit including an air gap layer and a computer-implemented method for manufacturing the integrated circuit.

With the advancement of semiconductor process technology, the process has become more and more sophisticated. Therefore, the parasitic capacitance may increase as the interval between the conductive patterns decreases. In order to reduce parasitic capacitance, air gap technology in which air gap patterns are placed between conductive patterns is being implemented. Since air has a small dielectric constant, the parasitic capacitance can be reduced due to the air gap pattern, and the operating speed of the semiconductor chip can be increased.

According to an exemplary embodiment of the concept of the present invention, a computer-implemented method for manufacturing an integrated circuit includes: placing a plurality of standard components, and the plurality of standard components define the integrated circuit; Select the timing critical path from the timing path; select at least one of the multiple networks contained in the timing critical path as at least one timing critical net; use the air gap layer to at least A timing critical network is pre-routing; the unselected network is routed; at least one timing critical network that is pre-routed and the routed unselected network are used to generate a layout; and based on the layout To manufacture integrated circuits.

According to an exemplary embodiment of the inventive concept, an integrated circuit includes: a first conductive pattern extending in a first direction; a second conductive pattern extending in a second direction different from the first direction; and a first interlayer The window is electrically connected to the first conductive pattern and the second conductive pattern; and the first air gap pattern to the fourth air gap pattern. The first air gap pattern extends in the first direction and is disposed on the first side of the first conductive pattern. The second air gap pattern extends in the first direction and is disposed on the second side of the first conductive pattern. The first side of the first conductive pattern is opposite to the second side of the first conductive pattern. The third air gap pattern extends in the second direction and is disposed on the first side of the second conductive pattern. The fourth air gap pattern extends in the second direction and is disposed on the second side of the second conductive pattern. The first side of the second conductive pattern is opposite to the second side of the second conductive pattern.

According to an exemplary embodiment of the inventive concept, an integrated circuit includes: a first conductive pattern extending in a first direction; a second conductive pattern extending in a second direction different from the first direction; and a first interlayer The window electrically connects the first conductive pattern and the second conductive pattern; the first air gap pattern extends in the first direction and is disposed on the first side of the first conductive pattern; and the second air gap pattern is in the second It extends in the direction and is arranged on the first side of the second conductive pattern.

According to an exemplary embodiment of the inventive concept, an integrated circuit includes: a first conductive pattern extending in a first direction; a second conductive pattern extending in a second direction different from the first direction; and a third conductive pattern , Extending in the first direction; and the first air gap pattern to the third air gap pattern. The first air gap pattern extends in the first direction and is disposed on the first side of the first conductive pattern. The second air gap pattern extends in the second direction and is disposed on the first side of the second conductive pattern. The third air gap pattern extends in the first direction and is disposed on the first side of the third conductive pattern. The first conductive pattern, the second conductive pattern, the third conductive pattern, the first air gap pattern, the second air gap pattern, and the third air gap pattern are arranged in the same layer.

According to an exemplary embodiment of the inventive concept, a standard component defining an integrated circuit includes: a first active area; a second active area; a plurality of fins extending in a first direction; a plurality of first metal lines in and Extending in a second direction intersecting the first direction; and a second metal wire extending in the first direction. A plurality of first metal wires and second metal wires are arranged between the first active area and the second active area. The standard element further includes: a plurality of first air gap patterns extending in the second direction and disposed between the plurality of first metal lines; and a second air gap pattern extending in the first direction and disposed on the second metal On the first side of the line.

Hereinafter, exemplary embodiments of the inventive concept will be explained more fully with reference to the accompanying drawings. In the drawings, the same reference numbers may refer to the same components throughout.

It should be understood that the terms "first", "second", "third", etc. are used herein to distinguish various components, and the components are not limited to these terms. Therefore, the “first” component in one exemplary embodiment may be described as the “second” component in another exemplary embodiment. It should be further understood that when two parts or directions are described as extending substantially parallel to each other or perpendicular to each other, the two parts or directions are exactly parallel to each other or extend perpendicular to each other, or approximately parallel to each other or extend perpendicular to each other, so Those who have general knowledge in this technology will understand.

FIG. 1 is a flowchart illustrating a method of manufacturing an integrated circuit according to an exemplary embodiment of the inventive concept.

1, according to an exemplary embodiment, a method of manufacturing an integrated circuit may include an integrated circuit design operation S10 and an integrated circuit manufacturing process S20. The integrated circuit design operation S10 may include operations S110 to S130 in which a tool for designing an integrated circuit is used to design the layout of the integrated circuit. In this case, the tool for designing the integrated circuit may be a program including multiple instructions executed by the processor. The program can be stored on the memory. Therefore, the integrated circuit design operation S10 can be referred to as a computer-implemented method for designing an integrated circuit that can be executed by a processor. The integrated circuit manufacturing process S20 corresponds to an operation of manufacturing a semiconductor device based on an integrated circuit based on the designed layout, and can be performed by a semiconductor manufacturing process device.

The integrated circuit can be defined by multiple components. For example, a component library including characteristic information of the plurality of components can be used to design an integrated circuit. For example, in the component library, the component name, size, gate width, pin, delay characteristic, leakage current, threshold voltage, and function of the component can be defined. In an exemplary embodiment, the component library may be a standard component library. The standard component library may include, for example, information such as layout information and timing information of a plurality of standard components. The component library including the standard component library can be stored in a computer-readable storage medium.

In operation S110, operation S110 may be performed by a processor using a placement and routing (P/R) tool, for example. First, receive the input data defining the integrated circuit. Here, the input data can be generated by synthesizing the data defined in the summary form of the integrated circuit behavior (for example, the data defined in the register transfer level (RTL)) using the standard component library . The input data can be, for example, by comparing very high speed integrated circuit (VHSIC) hardware description language (VHDL) and hardware description language (hardware description language, HDL) (for example, for example, In other words, the bit stream or netlist generated by the synthesis of integrated circuits defined by VERILOG. Subsequently, the storage medium storing the standard component library is accessed, and the standard component selected from the plurality of standard components stored in the standard component library is placed according to the input data.

In operation S120, the air gap layer is used to pre-route the network selected from the placed standard components, as described further below. In operation S130, a network that is not selected from the placed standard components is routed (for example, in the case of no air gap layer). Here, the air gap layer refers to a layer including air gaps or air gap patterns. For example, at least one of the plurality of nets included in the placed standard element may be selected, and the selected at least one net may be allocated to the air gap layer. In an exemplary embodiment, the at least one network may correspond to one network of the timing critical path, as described further below.

In this article, the net can represent the equipotential in the equivalent circuit diagram of an integrated circuit. One net can correspond to one interconnection in the layout of the integrated circuit. The interconnection may correspond to, for example, a wiring structure including a plurality of wiring layers and vias electrically connected to each other. Each of the wiring layers may include, for example, a plurality of conductive patterns. The conductive patterns formed in the wiring layers that can be arranged on different levels can be electrically connected to each other through the vias formed of conductive materials. In an exemplary embodiment, the wiring layer may include metal as a conductive material, and may be referred to as a metal layer. In an exemplary embodiment, the wiring layer may include conductive materials other than metals.

According to an exemplary embodiment, the net may include: a first conductive pattern included in the first wiring layer; a second conductive pattern included in the second wiring layer; and a via window disposed in the first conductive pattern The first conductive pattern and the second conductive pattern are electrically connected to the second conductive pattern. The first wiring layer and the second wiring layer may be arranged at different levels. However, the concept of the present invention is not limited to this. For example, in an exemplary embodiment, the net may include conductive patterns included in the same wiring layer. In addition, in an exemplary embodiment, the net may include a plurality of first conductive patterns included in the first wiring layer and a plurality of second conductive patterns included in the second wiring layer.

According to an exemplary embodiment, since the air gap pattern is disposed adjacent (for example, next to) the conductive pattern corresponding to the selected net, the selected net may be pre-routed by the air gap layer. In an exemplary embodiment, the air gap layer may be implemented by a bidirectional air gap layer. For example, the air gap pattern included in the air gap layer may extend in a first direction, or may extend in a second direction substantially perpendicular to the first direction. Hereinafter, an air gap layer according to an exemplary embodiment will be explained with reference to FIG. 2A.

2A is a cross-sectional view illustrating an integrated circuit IC including an air gap layer according to an exemplary embodiment of the inventive concept.

2A, the integrated circuit IC may include first to third wiring layers M1, M2, and M3, a first insulating layer ILD1 and a second insulating layer ILD2, and a first barrier layer BM1 and a second barrier layer BM2. The integrated circuit IC can be designed, for example, according to the process S10 shown in FIG. 1, and can be manufactured, for example, according to the process S20 shown in FIG.

The first wiring layer M1 may extend in the X direction, the first barrier layer BM1 may include a plurality of barrier layers disposed on the first wiring layer M1, and the first insulating layer ILD1 may be disposed on the first barrier layer BM1. The second wiring layer M2 may be disposed on the first insulating layer ILD1 and extending in the Y direction, the second barrier layer BM2 may include a plurality of barrier layers disposed on the second wiring layer M2, and the second insulating layer ILD2 may be disposed On the second barrier layer BM2. The first insulating layer ILD1 and the second insulating layer ILD2 can be referred to as interlayer dielectric. The third wiring layer M3 is disposed on the second insulating layer ILD2 and extends in the X direction.

In an exemplary embodiment, one of the first wiring layer M1 to the third wiring layer M3 to be allocated to the air gap layer AGL may be selected in advance. In an exemplary embodiment, the wiring layer to be allocated to the air gap layer AGL may be selected based on the height and/or width of the first wiring layer M1 to the third wiring layer M3. For example, a wiring layer having a relatively large height and/or width among the first wiring layer M1 to the third wiring layer M3 may have a relatively low resistance. This wiring layer can be selected as an air gap layer. For example, the resistance of a lower-level wiring layer such as the first wiring layer M1 may be higher than the resistance of a higher-level wiring layer such as the third wiring layer M3. In an exemplary embodiment, the wiring layer to be allocated to the air gap layer AGL may be selected based on the height and/or width of the via window connecting the first wiring layer M1 to the third wiring layer M3. For example, the resistance of a via of a lower-level wiring layer such as the first wiring layer M1 may be lower than the resistance of a via of a higher-level wiring layer such as the third wiring layer M3. In an exemplary embodiment, it may be based on the height and/or width of the first wiring layer M1 to the third wiring layer M3 and the height and/or width of the via window connecting the first wiring layer M1 to the third wiring layer M3. The wiring layer to be allocated is selected as the air gap layer AGL.

In an exemplary embodiment, the second wiring layer M2 may be allocated to the air gap layer AGL including the air gap pattern AGP, and the first wiring layer M1 and the third wiring layer M3 may be allocated to the normal layer not including the air gap pattern AGP , As shown in Figure 2A. In an exemplary embodiment, the second wiring layer M2 may be pre-routed by the air gap layer AGL, and the first wiring layer M1 and the third wiring layer M3 may be routed in the normal layer. Therefore, a two-stage wiring scheme can be used to route the first wiring layer to the third wiring layer M1, M2, and M3. In an exemplary embodiment, before routing other layers with the normal layer or after routing other layers with the normal layer, the wiring layer pre-routed with the air gap layer AGL may be pre-routed with the air gap layer AGL.

According to an exemplary embodiment, the second wiring layer M2 may include conductive patterns CPT extending in the Y direction and air gap patterns AGP disposed between the respective conductive patterns CPT. The air gap pattern AGP can be generated by replacing the inter-metal dielectric (IMD) material between the conductive patterns CPT with air. Since the dielectric constant of air is a low value of 1, the air gap pattern AGP can reduce the parasitic capacitance between the conductive patterns CPT, and thus can increase the operating speed of the semiconductor chip including the integrated circuit IC. However, due to the increase in process costs such as mask cost when generating the air gap pattern AGP, air gap layers are used in all the first wiring layers to the third wiring layers M1, M2, and M3 included in the integrated circuit IC. When it comes to implementation, the manufacturing cost of the wafer increases significantly.

Therefore, according to the exemplary embodiment, all layers included in the integrated circuit IC (for example, the first to third wiring layers M1, M2, and M3 in the exemplary embodiment shown in FIG. 2A) are It is implemented without using an air gap layer. Rather, only certain layers (for example, the layer corresponding to the network of the timing critical path)-for example (for example) only the second wiring layer M2 in the exemplary embodiment shown in FIG. 2A may use an air gap layer To implement. Therefore, the performance of the integrated circuit IC can be improved without significantly increasing the manufacturing cost. For example, according to the exemplary embodiment, the operating speed of the chip in which the integrated circuit IC is implemented can be increased to a level that is substantially equivalent to the level of the integrated circuit in which all layers of the integrated circuit are implemented using an air gap layer.

2B is a cross-sectional view illustrating an integrated circuit IC′ including an air gap layer according to an exemplary embodiment of the inventive concept.

2B, the integrated circuit IC' may include first to third wiring layers M1, M2', and M3, a first insulating layer ILD1 and a second insulating layer ILD2, and a first barrier layer BM1 and a second barrier. Layer BM2. The exemplary embodiment shown in FIG. 2B includes certain similarities to the exemplary embodiment shown in FIG. 2A. For ease of explanation, further detailed description of the components and configurations previously described with reference to FIG. 2A may be omitted herein. In an exemplary embodiment, the second wiring layer M2' may be allocated to the air gap layer AGL including the air gap pattern AGP, and the first wiring layer M1 and the third wiring layer M3 may be allocated to the general air gap layer M1 and M3 that do not include the air gap pattern AGP. Floor.

According to an exemplary embodiment, the second wiring layer M2' may include a conductive pattern CPT extending in the Y direction. For example, the conductive pattern CPT may include: a first conductive pattern CPT1 having an air gap pattern AGP disposed on opposite side surfaces of the first conductive pattern CPT1; a second conductive pattern CPT2 having an air gap pattern disposed on the second conductive pattern CPT2 The air gap pattern AGP on one side surface; and the third conductive pattern CPT3 does not have the air gap pattern AGP disposed on either opposite side surface of the third conductive pattern CPT3. Therefore, the first conductive pattern CPT1 and the second conductive pattern CPT2 may be referred to as an air gap conductive pattern, and the third conductive pattern CPT3 may be referred to as a normal conductive pattern. Therefore, in an exemplary embodiment, one of the conductive patterns CPT included in the air gap layer AGL (for example, the second wiring layer M2' in the exemplary embodiment shown in FIG. 2B) may use the air gap conductive pattern To implement.

Referring back to FIG. 1, after operation S130, the output data defining the integrated circuit may be provided to the semiconductor process device. Here, the output data may have a format including all layout information of standard components. For example, the output data may include pattern information of all layers, and may have, for example, a graphic design system (GDS) II format. In addition, the output data may have a format including external information of standard components (for example, pins of standard components). For example, the output data may have a library exchange format (LEF) or a Milky Way (MILKYWAY) format.

As described above, according to the exemplary embodiment, routing can be performed by applying a two-stage wiring scheme to the arranged standard components. For example, the routing of the arranged standard elements may include a first routing operation (for example, operation S120) and a second routing operation (for example, operation S130). For example, at least one net of the timing critical path among the plurality of timing critical paths in the arranged standard components may be allocated to the air gap layer, and the remaining nets may be allocated to the normal layer. Therefore, a high-performance integrated circuit can be manufactured by using a small number of air gap layers.

The operation S10 of designing an integrated circuit may include the above-mentioned operations S110 to S130. However, the concept of the present invention is not limited to this. For example, in an exemplary embodiment, the operation S10 may include various operations related to designing an integrated circuit, such as, for example, the generation of a standard component library, the calibration of the standard component library, and the verification of the layout. In addition, in an exemplary embodiment, operations S110 to S130 may correspond to a back-end design process of an integrated circuit design process, and the front-end design process may be performed before operation S110. The front-end design process can include, for example, the determination of design specifications, the modeling and verification of the act level, the design of register-transfer level (RTL), the verification of functions, the synthesis of logic, and the gate level Verification (or pre-layout simulation).

In operation S140, a mask is generated based on the layout. For example, first, optical proximity correction (OPC) can be implemented based on the layout. Optical proximity correction refers to the process of changing the layout while reflecting errors based on the optical proximity effect. Subsequently, the mask may be manufactured according to the layout changed based on the result of the optical proximity correction performance. Then, a layout that reflects optical proximity correction (eg, for example, a graphic data system (GDS) that reflects optical proximity correction) can be used to manufacture the mask.

In operation S150, the mask is used to manufacture an integrated circuit. For example, by using the mask to perform various semiconductor processes on a semiconductor substrate such as a wafer, a semiconductor device in which an integrated circuit is implemented is formed. The process using the mask may refer to, for example, a patterning process performed by a photolithography process. The desired pattern can be formed on the semiconductor substrate or material layer through a patterning process. The semiconductor process may include, for example, a deposition process, an etching process, an ionization process, and a cleaning process. The semiconductor manufacturing process may further include, for example, a packaging process including the following operations: mounting a semiconductor device on a printed circuit board (PCB) and sealing the semiconductor with an encapsulant. The semiconductor manufacturing process may further include a testing process such as testing semiconductor devices or packaging.

FIG. 3 is an integrated circuit design system 10 according to an exemplary embodiment of the concept of the present invention.

Referring to FIG. 3, the integrated circuit design system 10 may include a processor 11, a working memory 13, an input/output device 15, an auxiliary storage 17, and a bus 19. The integrated circuit design system 10 can implement the integrated circuit design process shown in FIG. 1. In an exemplary embodiment, the integrated circuit design system 10 may be implemented by an integrated device, and therefore, may be referred to as an integrated circuit design device. The integrated circuit design system 10 can be provided as a dedicated device for designing integrated circuits of semiconductor devices, and can be a computer for driving various simulation tools or design tools.

The processor 11 may be used to execute instructions for performing at least one of various integrated circuit design operations. The processor 11 can communicate with the working memory 13, the input/output (I/O) device 15, and the auxiliary storage 17 through the bus 19. The processor 11 can perform an operation of designing an integrated circuit by driving a placement and routing (P&R) module 13a and a timing analysis module 13b loaded in the working memory 13. For example, the processor 11 can perform an operation of designing an integrated circuit by executing instructions stored in the memory and related to placement and routing and timing analysis.

The working memory 13 can store a placement and routing module 13a (for example, instructions related to placement and routing) and a timing analysis module 13b (for example, instructions related to timing analysis). The placement and routing module 13a and the timing analysis module 13b can be loaded from the auxiliary storage 17 to the working memory 13. The working memory 13 may be a volatile memory, such as, for example, a static random access memory (SRAM) or a dynamic random access memory (DRAM), or it may be Non-volatile memory, such as (for example) phase change random access memory (PRAM), magneto-resistive random access memory (MRAM), resistance-based Random access memory (resistance based random access memory, ReRAM), or reverse or flash memory.

The placement and routing module 13a may be, for example, a program including instructions for performing the arrangement operation according to the operation S110 shown in FIG. 1 and performing the wiring operation according to the operation S120 and the operation S130 shown in FIG. 1. The timing analysis module 13b may be, for example, a program including an instruction for determining whether a timing constraint is satisfied. Determining whether the timing restriction condition is satisfied may include, for example, performing timing analysis on all timing paths in the arranged standard components. The timing analysis module 13b may refer to, for example, a static timing analysis (STA) tool.

The input/output device 15 can control user input and output from the user interface device. The input/output device 15 may include, for example, an input device such as a keyboard, a mouse, or a touch pad, and may receive input data defining an integrated circuit. The input/output device 15 may include an output device such as, for example, a display or a speaker, and may display, for example, an arrangement result, a wiring result, or a timing analysis result.

The auxiliary storage 17 can store various data related to the placement and routing module 13a and the timing analysis module 13b. The auxiliary storage 17 may include, for example, a memory card (for example, a multimedia card (MMC), an embedded multimedia card (eMMC), a secure digital (SD) card, a micro secure digital card, etc.), Solid state drives, and hard disk drives.

FIG. 4 is an integrated circuit design system 20 according to an exemplary embodiment of the inventive concept.

Referring to FIG. 4, the integrated circuit design system 20 may include a user device 21, an integrated circuit design platform 22, and an auxiliary storage 23. The integrated circuit design system 20 can perform the integrated circuit design operation S10 shown in FIG. 1. In an exemplary embodiment, at least one of the user device 21, the integrated circuit design platform 22, and the auxiliary storage 23 may be a separate device, and the user device 21, the integrated circuit design platform 22, and the auxiliary storage The storage 23 can communicate with each other through wired/wireless communication via a network. In an exemplary embodiment, at least one of the user device 21, the integrated circuit design platform 22, and the auxiliary storage 23 may be placed at a different location from other components.

The user device 21 may include a processor 21a and a user interface (UI) 21b. The processor 21a can drive the integrated circuit design platform 22 according to user input input through the user interface 21b. The integrated circuit design platform 22 is a set of computer-readable instructions for designing integrated circuits, and may include a placement and routing module 22a (for example, corresponding to instructions related to placement and routing) and a timing analysis module 22b (For example, corresponding to instructions related to timing analysis). The auxiliary storage 23 may include a component database (database, DB) 23a and a layout database 23b. The component library database 23a stores information related to components used to generate the layout of the integrated circuit, and the layout database 23b stores information related to the layout generated by the placement and routing module 22a (for example, physical information of the layout).

FIG. 5 is a flowchart illustrating a method S10A for designing an integrated circuit according to an exemplary embodiment of the concept of the present invention.

Referring to FIG. 5, a method S10A for designing an integrated circuit according to an exemplary embodiment may correspond to the implementation of the integrated circuit design operation S10 shown in FIG. 1. The method S10A of designing an integrated circuit can be implemented, for example, by the processor 11 of the integrated circuit design system 10 shown in FIG. 3 or the processor 21a of the integrated circuit design system 20 shown in FIG. 4.

In operation S210, floor planning is implemented. Base Chu planning is the placement planning stage, and refers to the operation of briefly planning the placement/wiring methods of standard components and macro cells. For example, the infrastructure planning may include, for example, operations such as placing input/output pads, standard components, random access memory (RAM), etc. on the chip.

In operation S220, a standard component defining an integrated circuit is placed. After that, optimization after placement can be performed. In operation S230, clock tree synthesis is performed. Clock tree synthesis refers to the operation of automatically generating a clock network when generating the circuit layout and inserting a buffer at an appropriate position. Once the standard components are placed in operations S220 and S230 and the clock tree synthesis is performed, the placement of the standard components is completed.

In operation S240, an air gap layer is selected. In an exemplary embodiment, a timing critical path among a plurality of timing paths included in the placed standard element may be selected, and the timing critical path may be assigned to the air gap layer. In operation S250, a network on the timing critical path (hereinafter also referred to as a timing critical network) is selected. In an exemplary embodiment, the network included in the timing critical path range may be selected as the timing critical network. In an exemplary embodiment, operation S240 and/or operation S250 may be performed during the placing operation S220. In an exemplary embodiment, operation S240 and/or operation S250 may be performed during pre-routing operation S260 and routing operation S270.

In an exemplary embodiment, the integrated circuit design method may further include an operation of reselecting the timing critical network after operation S250. For example, some of the timing critical networks can be excluded from the air gap layer target network based on, for example, the delay of the timing critical network, the physical condition of the wiring layer corresponding to the timing critical network, and the like. The previously selected timing critical networks can be excluded through the reselection operation.

In an exemplary embodiment, the delay (for example, the delay of the air gap conductive pattern routing) corresponding to the case where the air gap conductive pattern (for example, CPT1 or CPT2 shown in FIG. 2B) is used to route the timing critical network can be compared And the delay corresponding to the situation in which the normal conductive pattern (for example, CPT3 shown in FIG. 2B) is used to route the timing critical network (for example, the delay of the normal conductive pattern routing), and the timing critical network can be reselected based on the comparison result road. For example, when the length of the first net in the selected timing critical net is small (for example, when the first net connects two connection points of the same wiring layer), the air of the first net The delay of the gap conductive pattern may be greater than the delay of the routing of the normal conductive pattern. Therefore, the first network can be excluded from the selected timing critical network (for example, via a reselection operation).

In an exemplary embodiment, it may be determined whether the space between the conductive pattern corresponding to the timing critical network and the adjacent conductive pattern is less than the threshold value, and the timing critical network may be reselected based on the determination result. For example, in an exemplary embodiment, if the space near the conductive pattern corresponding to the first network in the selected timing critical network is not less than the threshold value, the selected timing critical network ( For example, through a reselection operation) exclude the first network.

In addition, in an exemplary embodiment, the position of the conductive pattern corresponding to the timing critical net may be determined, and the timing critical net may be reselected based on the determination result. For example, when the conductive pattern corresponding to the first net of the selected timing critical net is located at the far end of the wiring layer, the first net can be excluded from the selected timing critical net (for example, through a reselection operation). One network.

In operation S260, the timing critical network is pre-routed on the air gap layer with high priority. In operation S270, the non-critical path network (hereinafter also referred to as the unselected network) among the timing paths in the placed standard components is routed. In this way, according to an exemplary embodiment, in the method S10A of designing an integrated circuit, a high-performance integrated circuit can be implemented by using a small number of air gap layers and by applying a two-stage wiring scheme, in which the air gap layer In the above, the network included in the timing critical path is pre-routed with a relatively high priority, and the network of the non-critical path is routed with a relatively low priority without an air gap layer.

FIG. 6 is a flowchart illustrating a method S10B for designing an integrated circuit according to an exemplary embodiment of the concept of the present invention.

Referring to FIG. 6, the method S10B for designing an integrated circuit according to an exemplary embodiment may correspond to the implementation of the integrated circuit design process S10A shown in FIG. 5. The method S10B of designing an integrated circuit can be implemented, for example, by the processor 11 of the integrated circuit design system 10 shown in FIG. 3 or the processor 21a of the integrated circuit design system 20 shown in FIG. 4.

In operation S310, a plurality of standard components defining an integrated circuit are placed. Operation S310 may be performed, for example, using a placement tool and a routing tool (for example, the part 13a shown in FIG. 3 or the part 22a shown in FIG. 4). In an exemplary embodiment, operation S310 may correspond to operation S220 shown in FIG. 5. In addition, in an exemplary embodiment, operation S310 may correspond to operation S220 and operation S230 shown in FIG. 5.

In operation S320, trial-routing may be performed on the placed standard components. Here, the attempted route refers to a route used to classify timing critical paths. However, the concept of the present invention is not limited to this. For example, operation S320 may be omitted in an exemplary embodiment. For example, when the timing analysis is enabled only by the placement information of the standard components in operation S310, operation S320 may be omitted. In operation S330, timing analysis is performed. For example, timing analysis can be performed to select a timing critical path among multiple timing paths in the placed standard component, and timing analysis result data can be provided. For example, in operation S330, the timing critical path may be selected from a plurality of timing paths included in the placed standard component based on the timing analysis result data obtained by performing the timing analysis. In addition, at least one network can be selected as the timing critical network based on the timing analysis result data.

The timing path can be divided into, for example, a data path, a clock path, a clock gating path, and an asynchronous path. Each of the timing paths has a start point and an end point. The timing path can refer to, for example, between the various parts of the integrated circuit (for example, between the input pad and the output pad, between the input pad and the data input of the flip-flop, the data output of the flip-flop and another Combination logic and interconnection between the data input of the flip-flop, and between the data output of the flip-flop and the output pad. The delay through the timing path can have a significant impact on the operating speed of the integrated circuit.

A timing critical path may refer to a timing path in which the total timing delay from input (eg, start point) to output (eg, end point) exceeds timing constraints. The timing path in which the total timing delay from the input (for example, the start point) to the output (for example, the end point) does not exceed the timing limit may be referred to as a non-critical path. In an exemplary embodiment, the timing critical path may refer to the timing path with the greatest delay. Hereinafter, the timing analysis will be explained in more detail with reference to FIG. 7.

FIG. 7 is a graph showing a timing analysis result according to an exemplary embodiment of the inventive concept.

Referring to FIG. 7, the horizontal axis represents slack and the vertical axis represents the number of timing paths. Here, the lag time represents the difference between the time required for the timing request and the actual arrival time, and can be determined by a timing analyzer or a timing analysis module (for example, the timing analysis module 13b shown in Figure 3 or the timing analysis module Timing analysis module 22b) to measure. A positive lag time indicates that a timing violation (for example, meeting timing requirements) has not occurred, while a negative lag time indicates that a timing violation has occurred (for example, timing requirements are not met). Therefore, the timing path corresponding to the negative delay time in FIG. 7 may correspond to a timing critical path (TCP).

Referring back to FIG. 6, in operation S340, the network of the timing critical path is selected. For example, it can be selected by applying the analysis data obtained in operation S330 to the standard components placed in operation S310 (for example, by applying the analysis data to the state before the attempted routing of operation S320 is performed). At least one of the multiple networks included in the timing critical path. For example, the network corresponding to the specific range of the timing critical path can be selected. Therefore, in operation S340, at least one network may be selected from a plurality of networks included in the timing critical path. The selected at least one network may be referred to as at least one timing critical network of the timing critical path.

In operation S350, the selected network is pre-routed with the air gap layer. In an exemplary embodiment, the selected net may correspond to a first conductive pattern included in the first wiring layer, a via window electrically connected to the first conductive pattern, and a second wiring layer included In and electrically connected to the second conductive pattern of the via. In an exemplary embodiment, two air gap layers can be selected by disposing an air gap pattern on the opposite side of the first conductive pattern and by disposing an air gap pattern on the opposite side of the second conductive pattern. Network for routing. Hereinafter, operation S350 will be explained in more detail with reference to FIG. 8 and FIGS. 9A to 9C.

FIG. 8 illustrates a wiring structure 81 for routing using an air gap layer AGL according to an exemplary embodiment of the inventive concept.

Referring to FIG. 8, the wiring structure 81 corresponds to a timing critical path. In the wiring structure 81, only the fifth wiring layer M5 and the sixth wiring layer M6 corresponding to certain regions of the wiring structure 81 are routed by the air gap layer AGL. The fifth wiring layer M5 and the sixth wiring layer M6 may correspond to the selected net of the timing critical path (for example, the timing critical net). The first wiring layer M1 may include a first pin P1 and a second pin P2. The first pin P1 and the second pin P2 may correspond to, for example, an input pin (for example, the start point) and an output pin (for example, the end point) of the critical path of timing.

The critical timing path is one of the timing paths in the placed standard components that does not meet the timing restriction conditions. Therefore, the parasitic capacitance between the conductive patterns in the critical path of timing can significantly affect the performance (for example, the operating speed) of the integrated circuit and the chip including the integrated circuit. According to an exemplary embodiment, the air gap layer is used to pre-route the selected network included in the timing critical path (for example, the timing critical network). Pre-routing the selected net with the air gap layer includes, for example, placing an air gap pattern on the opposite side of the wiring layer corresponding to the selected net.

According to an exemplary embodiment, since the selected network of the timing critical path is pre-routed with the air gap layer, the parasitic capacitance between the conductive patterns corresponding to the selected network of the timing critical path can be reduced. Therefore, the timing delay of the timing critical path can be reduced, so that the timing critical path meets the timing constraints. Therefore, the operating speed of the integrated circuit and the chip including the integrated circuit can be increased.

9A to 9E are perspective views illustrating a timing critical network routed with an air gap layer according to an exemplary embodiment of the inventive concept. The timing critical net illustrated in FIGS. 9A and 9C to 9E may correspond to, for example, the fifth wiring layer M5 and the sixth wiring layer M6 shown in FIG. 8. The timing critical net illustrated in FIG. 9B may include a fifth wiring layer M5 and an eighth wiring layer M8, as described further below.

Referring to FIG. 9A, a bidirectional air gap layer may be disposed on a continuous metal layer (for example, a continuous wiring layer). For example, a bidirectional air gap layer including air gap pattern AGP1, air gap pattern AGP1', air gap pattern AGP2, and air gap pattern AGP2' can be disposed on the continuous fifth wiring layer M5 and the continuous sixth wiring layer M6. In FIG. 9A, the timing-critical network 100 may be a network connecting the first connection point CP1 and the second connection point CP2. The timing critical network 100 may include: a fifth wiring layer M5, which is electrically connected to the first connection point CP1; a via window V5, which is arranged on the fifth wiring layer M5 and is electrically connected to the fifth wiring layer M5; and The six wiring layer M6 is arranged on the via V5 and electrically connected to the via V5 and the second connection point CP2. The fifth wiring layer M5 may extend in the Y direction, and the sixth wiring layer M6 may extend in the X direction. In all the figures, the X direction and the Y direction may be substantially perpendicular to each other. The fifth wiring layer M5 and the sixth wiring layer M6 may respectively correspond to, for example, the fifth wiring layer M5 and the sixth wiring layer M6 shown in FIG. 8.

In the exemplary embodiment shown in FIG. 9A, both the fifth wiring layer M5 and the sixth wiring layer M6 may be implemented by an air gap layer. For example, the air gap pattern AGP1 and the air gap pattern AGP1' may be arranged on the opposite sides of the fifth wiring layer M5, and the air gap patterns AGP2 and AGP2' may be arranged on the opposite sides of the sixth wiring layer M6. However, the concept of the present invention is not limited to this. For example, in an exemplary embodiment, an air gap pattern may be disposed on only one side of the fifth wiring layer M5, and an intermetallic containing a general dielectric material may be disposed on the opposite side of the fifth wiring layer M5. Dielectric. Similarly, an air gap pattern may be disposed on only one side of the sixth wiring layer M6, and an intermetal dielectric including a general dielectric material may be disposed on the opposite side of the sixth wiring layer M6.

In an exemplary embodiment, the air gap pattern AGP1 and the air gap pattern AGP1' may extend in the Y direction, and the air gap patterns AGP2 and AGP2' may extend in the X direction. According to an exemplary embodiment, the timing critical net 100 may be implemented by a bidirectional air gap layer that includes an air gap pattern and extends in two different directions as shown in 9A. In addition, according to an exemplary embodiment, it may be on two continuous wiring layers in the Z direction as shown in FIG. 9A and FIGS. 9C to 9E or on two non-continuous wiring layers in the Z direction as shown in FIG. 9B Place an air gap pattern on it. For example, in an exemplary embodiment, the fifth wiring layer M5 and the sixth wiring layer M6 are two consecutive layers that are adjacent (for example, next to each other) in the Z direction as shown in FIGS. 9A and 9C to 9E. The wiring layer is implemented by the air gap layer. Therefore, according to the exemplary embodiment, due to the use of the bidirectional air gap layer, the air gap volume can be increased regardless of the positions of the first connection point CP1 and the second connection point CP2 of the timing critical network 100. Therefore, the performance gain of the integrated circuit can be increased. In an exemplary embodiment, the air gap volume can be approximately 100% due to the use of a bidirectional air gap layer, regardless of the positions of the first connection point CP1 and the second connection point CP2 of the timing critical network 100.

Referring to FIG. 9B, a bidirectional air gap layer may be disposed on a discontinuous metal layer (for example, a discontinuous wiring layer). For example, a bidirectional air gap layer including an air gap pattern AGP1, an air gap pattern AGP1', an air gap pattern AGP2, and an air gap pattern AGP2' can be arranged on the discontinuous fifth wiring layer M5 and the eighth wiring layer M8. . The intermediate wiring layer M6 and the intermediate wiring layer M7 may be disposed between the discontinuous fifth wiring layer M5 and the eighth wiring layer M8. In FIG. 9B, the timing critical network 100 may be a network connecting the first connection point CP1 and the second connection point CP2. The timing-critical network 100 may include: a fifth wiring layer M5, which is electrically connected to the first connection point CP1; a via window V5, which is arranged on the fifth wiring layer M5 and is electrically connected to the fifth wiring layer M5; and sixth The wiring layer M6 is arranged on the interlayer window V5 and is electrically connected to the interlayer window V5; the interlayer window V6 is arranged on the sixth wiring layer M6 and is electrically connected to the sixth wiring layer M6; the seventh wiring layer M7 , Arranged on the via window V6 and electrically connected to the via window V6; via the window V7, arranged on the seventh wiring layer M7 and electrically connected to the seventh wiring layer M7; and the eighth wiring layer M8, arranged It is on the via V7 and electrically connected to the via V7 and the second connection point CP2. The fifth wiring layer M5 and the seventh wiring layer M7 may extend in the Y direction, and the sixth wiring layer M6 and the eighth wiring layer M8 may extend in the X direction. In all the figures, the X direction and the Y direction may be substantially perpendicular to each other.

In the exemplary embodiment shown in FIG. 9B, the fifth wiring layer M5 and the eighth wiring layer M8, which are discontinuous wiring layers, may be implemented by air gap layers. For example, the air gap pattern AGP1 and the air gap pattern AGP1' may be arranged on opposite sides of the fifth wiring layer M5, and the air gap layer AGP2 and the air gap pattern may be arranged on opposite sides of the eighth wiring layer M8 AGP2'. However, the concept of the present invention is not limited to this. For example, in an exemplary embodiment, an air gap pattern may be disposed on only one side of the fifth wiring layer M5, and an intermetallic containing a general dielectric material may be disposed on the opposite side of the fifth wiring layer M5. Dielectric. Similarly, an air gap pattern may be disposed on only one side of the eighth wiring layer M8, and an intermetal dielectric including a general dielectric material may be disposed on the opposite side of the eighth wiring layer M8. In an exemplary embodiment, the air gap pattern AGP1 and the air gap pattern AGP1' may extend in the Y direction, and the air gap pattern AGP2 and the air gap pattern AGP2' may extend in the X direction. According to an exemplary embodiment, an air gap pattern may be arranged on two discontinuous wiring layers in the Z direction as shown in FIG. 9B. For example, in an exemplary embodiment, the fifth wiring layer M5 and the eighth wiring layer M8 are two non-contiguous wiring layers that are not adjacent (for example, not immediately adjacent) to each other in the Z direction as shown in FIG. 9B, And can be implemented by an air gap layer.

Referring to FIGS. 9C to 9E, an air gap pattern may be disposed on only one side of the fifth wiring layer M5 and/or the sixth wiring layer M6. An intermetal dielectric including a general dielectric material may be disposed on the opposite side of the fifth wiring layer M5 and/or the sixth wiring layer M6 on which the air gap pattern is disposed only on one side. For example, in the exemplary embodiment shown in FIG. 9C, the bidirectional air gap layer may include air gap patterns AGP1 and AGP1' disposed on opposite sides of the fifth wiring layer M5, and the sixth wiring layer M5. The air gap pattern AGP2 on only one side of the layer M6. An intermetal dielectric including a general dielectric material may be disposed on the side of the sixth wiring layer M6 that does not include the air gap pattern disposed adjacent thereto. In the exemplary embodiment shown in FIG. 9D, the bidirectional air gap layer may include the air gap pattern AGP2 and the air gap pattern AGP2' disposed on opposite sides of the sixth wiring layer M6, and only the air gap pattern AGP2' disposed on the fifth wiring layer M5. Air gap pattern AGP1 on one side. An intermetal dielectric including a general dielectric material may be disposed on the side of the fifth wiring layer that does not include the air gap pattern disposed adjacent thereto. In the exemplary embodiment shown in FIG. 9E, the bidirectional air gap layer may include an air gap pattern AGP1 disposed on only one side of the fifth wiring layer M5 and an air gap disposed on only one side of the sixth wiring layer M6 Pattern AGP2. An intermetal dielectric including a general dielectric material may be disposed on the side of the fifth wiring layer M5 and the sixth wiring layer M6 that does not include the air gap pattern disposed adjacent thereto.

As described with reference to FIGS. 9A to 9E, the pre-routing of the selected network (for example, the timing critical network) can be implemented in various ways. For example, the number of air gap layers and/or the number of air gap patterns can be variably determined according to the size of the lag time based on the timing analysis result. In addition, the number of air gap layers and/or the number of air gap patterns can be variably determined in view of other constraints (for example, power constraints or area constraints, and timing constraints). The air gap layer can be used to pre-route multiple selected networks (for example, timing critical networks) in the above-mentioned manner.

Referring back to FIG. 6, in operation S360, the unselected network is routed. In an exemplary embodiment, the unselected network may include a network included in a non-critical path among the plurality of timing paths in the standard element. In addition, the unselected network may include the network included in the timing critical path other than the network selected in operation S340. For example, in the timing critical path, certain networks can be selected as timing critical networks and can be pre-routed with an air gap layer, while other networks can be unselected and can be performed without an air gap layer. Routing (for example, routing in a layer that does not include an air gap pattern). The unselected network can also be called a non-critical network.

In an exemplary embodiment, the unselected net may correspond to a first conductive pattern included in the first wiring layer, a via window electrically connected to the first conductive pattern, and a second wiring layer included In and electrically connected to the second conductive pattern of the via. Unselected networks can be routed without an air gap layer. For example, it is possible to arrange a general dielectric material on opposite sides of each of the first conductive pattern and the second conductive pattern instead of each of the first conductive pattern and the second conductive pattern. Air gap patterns are placed on opposite sides to route unselected nets. However, the concept of the present invention is not limited to this. For example, in an exemplary embodiment, at least one of the unselected networks may be routed through an air gap layer. For example, the number or length of critical timing paths may be relatively small (for example, less than a predetermined threshold), and the number of networks included in critical timing paths may also be relatively small (for example, less than a predetermined threshold). Therefore, the number of networks selected in operation S340 may be small. In this case, when the resources of the air gap layer remain, the air gap layer may route at least one of the networks not selected in operation S360.

Hereinafter, operation S360 will be explained in more detail with reference to FIG. 10.

FIG. 10 illustrates a wiring structure 101 for routing using a normal layer according to an exemplary embodiment of the inventive concept.

10, the wiring structure 101 may correspond to a non-critical path, and the first wiring layer M1 to the sixth wiring layer M6 included in the wiring structure 101 may be routed in normal layers (for example, in the case of no air gap layer) For routing). The first wiring layer M1 may include a first pin P1 and a second pin P2. The first pin P1 and the second pin P2 may respectively correspond to, for example, an input pin (for example, the start point) and an output pin (for example, the end point) of a non-critical path.

The non-critical path is one of the timing paths in the placed standard components that meets the timing restriction conditions. Therefore, the parasitic capacitance between the conductive patterns of the non-critical path may not significantly affect the performance (for example, the operating speed) of the integrated circuit and the chip including the integrated circuit. Therefore, according to an exemplary embodiment, the air gap layer may be replaced by the normal layer to route the network included in the non-critical path. For example, an intermetallic dielectric containing a general dielectric material can be placed on opposite sides of the wiring layer corresponding to the net included in the non-critical path (for example, instead of placing air on opposite sides thereof) Gap pattern).

According to an exemplary embodiment of the inventive concept, the number of air gap layers used when manufacturing an integrated circuit including an air gap layer can be reduced by the following ways: the air gap layer is used to select the network of the critical path for timing Perform pre-routing, and use normal layers (for example, using intermetallic dielectrics containing general dielectric materials) instead of air gap layers for unselected networks (for example, non-critical path networks and/or timing critical Path of the unselected network) for routing. Therefore, the manufacturing cost of the integrated circuit can be reduced, and the operating speed of the integrated circuit and the chip including the integrated circuit can be increased.

Referring back to FIG. 6, in operation S370, post-routing optimization is performed. Post-routing optimization will correct timing and/or design rule violations that may exist after routing is completed. After the post-routing optimization, the final layout can be generated by implementing engineering change order (ECO) routing and reflecting any changes in the network connection table.

FIG. 11A is a plan view illustrating an integrated circuit 200 for routing by applying an air gap pattern according to an exemplary embodiment of the inventive concept. FIG. 11B is a perspective view illustrating the integrated circuit 200 shown in FIG. 11A according to an exemplary embodiment of the inventive concept.

Referring to FIGS. 11A and 11B, the integrated circuit 200 may correspond to include a first connection point 210 and a second connection point 215 (indicated by CP in FIGS. 11A and 11B) and a conductive pattern 220 (in FIGS. 11A and 11B) A network marked by Mb). The first connection point 210 and the second connection point 215 may be arranged in the same layer, and the Y coordinate of the first connection point 210 and the second connection point 215 may be the same, and the first connection point 210 and the second connection point 215 may be the same. The X coordinate can be different. The integrated circuit 200 may include, for example, a conductive pattern 220 disposed between the first connection point 210 and the second connection point 215, and air gap patterns 230 and 235 disposed on opposite sides of the conductive pattern 220 (in FIGS. 11A and 11B is marked by AGPb).

In an exemplary embodiment, the conductive pattern 220 may correspond to a timing critical path. Therefore, the air gap pattern 230 and the air gap pattern 235 may be disposed on opposite sides of the conductive pattern 220. The conductive pattern 220 may extend in the X direction, and therefore, the air gap pattern 230 and the air gap pattern 235 may also extend in the X direction. The conductive pattern 220 may correspond to, for example, the fifth wiring layer M5 or the sixth wiring layer M6 shown in FIG. 8.

FIG. 12 is a plan view illustrating an integrated circuit 300 for routing by applying an air gap pattern according to an exemplary embodiment of the inventive concept. FIG. 12B is a perspective view illustrating the integrated circuit 300 shown in FIG. 12A according to an exemplary embodiment of the inventive concept.

Referring to FIGS. 12A and 12B, the integrated circuit 300 may correspond to include a first connection point 310 and a second connection point 315 (denoted by CP in FIGS. 12A and 12B), and a first conductive pattern 320 and a second conductive pattern 350 (Denoted by Ma and Mb in Figure 12A and Figure 12B, respectively) of a network. The first connection point 310 and the second connection point 315 can be arranged in different layers, and the Y coordinate of the first connection point 310 and the second connection point 315 can be the same, and the Y coordinate of the first connection point 310 and the second connection point 315 The X coordinate can be different. The integrated circuit 300 may include, for example, a first conductive pattern 320 connected to the first connection point 310; a first via 340 and a second via 345 disposed on the first conductive pattern 320; and a second conductive pattern 350 , Arranged on the second via 345; the first air gap pattern 330 and the first air gap pattern 335 (indicated by AGPa in FIGS. 12A and 12B), arranged on opposite sides of the first conductive pattern 320; And the second air gap pattern 360 and the second air gap pattern 365 (indicated by AGPb in FIGS. 12A and 12B) are disposed on opposite sides of the second conductive pattern 350.

In an exemplary embodiment, the first conductive pattern 320 and the second conductive pattern 350 may correspond to a timing critical path. Therefore, the first air gap pattern 330 and the first air gap pattern 335 may be disposed on opposite sides of the first conductive pattern 320, and the second air gap pattern 360 and the second air gap pattern 365 may be disposed on the second conductive pattern 350 on opposite sides. The first conductive pattern 320 may extend in the X direction, and therefore, the first air gap pattern 330 and the first air gap pattern 335 may also extend in the X direction. The second conductive pattern 350 may extend in the X direction, and therefore, the second air gap pattern 360 and the second air gap pattern 365 may also extend in the X direction. The first conductive pattern 320 and the second conductive pattern 350 may respectively correspond to, for example, the fifth wiring layer M5 and the sixth wiring layer M6 shown in FIG. 8.

FIG. 13A is a plan view illustrating an integrated circuit 400 for routing by applying an air gap pattern according to an exemplary embodiment of the inventive concept. FIG. 13B is a perspective view illustrating the integrated circuit 400 shown in FIG. 13A according to an exemplary embodiment of the inventive concept.

Referring to FIGS. 13A and 13B, the integrated circuit 400 may correspond to include a first connection point 410 and a second connection point 415 (indicated by CP in FIGS. 13A and 13B) and a conductive pattern 420 (in FIGS. 13A and 13B) A network marked by Ma). The first connection point 410 and the second connection point 415 can be arranged in the same layer, and the X coordinates of the first connection point 410 and the second connection point 415 can be the same, and the X coordinates of the first connection point 410 and the second connection point 415 can be the same. The Y coordinate can be different. The integrated circuit 400 may include, for example, a conductive pattern 420 disposed between the first connection point 410 and the second connection point 415, and an air gap pattern 430 and an air gap pattern 435 disposed on opposite sides of the conductive pattern 420.

In an exemplary embodiment, the conductive pattern 420 may correspond to a timing critical path. Therefore, the air gap pattern 430 and the air gap pattern 435 (denoted by AGPa in FIGS. 13A and 13B) may be disposed on opposite sides of the conductive pattern 420. The conductive pattern 420 may extend in the Y direction, and therefore, the air gap pattern 430 and the air gap pattern 435 may also extend in the Y direction. The conductive pattern 420 may correspond to, for example, the fifth wiring layer M5 or the sixth wiring layer M6 shown in FIG. 8.

14A is a plan view illustrating an integrated circuit 600 for routing by applying an air gap pattern according to an exemplary embodiment of the inventive concept. FIG. 14B is a perspective view illustrating the integrated circuit 600 shown in FIG. 14A according to an exemplary embodiment of the inventive concept.

Referring to FIGS. 14A and 14B, the integrated circuit 600 may correspond to include a first connection point 610 and a second connection point 615 (denoted by CP in FIGS. 14A and 14B), and a first conductive pattern 620 and a second conductive pattern 650 (Denoted by Ma and Mb in Figure 14A and Figure 14B, respectively) of a network. The first connection point 610 and the second connection point 615 can be arranged in different layers, and the X and Y coordinates of the first connection point 610 and the second connection point 615 can be different. The integrated circuit 600 may include, for example: a first conductive pattern 620 connected to the first connection point 610; a via 640 disposed on the first conductive pattern 620; and a second conductive pattern 650 disposed on the via 640; The first air gap pattern 630 and the first air gap pattern 635 (indicated by AGPa in FIGS. 14A and 14B) are disposed on opposite sides of the first conductive pattern 620; and the second air gap pattern 660 and the second air gap The patterns 665 (denoted by AGPb in FIGS. 14A and 14B) are disposed on opposite sides of the second conductive pattern 650.

In an exemplary embodiment, the first conductive pattern 620 and the second conductive pattern 650 may correspond to a timing critical path. Therefore, the first air gap pattern 630 and the first air gap pattern 635 may be disposed on opposite sides of the first conductive pattern 620, and the second air gap pattern 660 and the second air gap pattern 665 may be disposed on the second conductive pattern 650 on opposite sides. The first conductive pattern 620 may extend in the Y direction, and therefore, the first air gap pattern 630 and the first air gap pattern 635 may also extend in the Y direction. The second conductive pattern 650 may extend in the X direction, and therefore, the second air gap pattern 660 and the second air gap pattern 665 may also extend in the X direction. The first conductive pattern 620 and the second conductive pattern 650 may respectively correspond to, for example, the fifth wiring layer M5 and the sixth wiring layer M6 shown in FIG. 8.

In this way, according to an exemplary embodiment of the inventive concept, the first air gap pattern 630 and the first air gap pattern 635 may be arranged to extend in the Y direction, and the second air gap pattern 660 and the second air gap The pattern 665 may be arranged to extend in the X direction. Therefore, the first air gap pattern 630, the first air gap pattern 635, the second air gap pattern 660, and the second air gap pattern 665 are implemented by a bidirectional air gap pattern. Therefore, two continuous layers that are adjacent (eg, next to each other) in the Z direction can be implemented by an air gap layer (eg, each continuous layer can include an air gap pattern). For example, when only a unidirectional air gap pattern is used, two adjacent (eg, immediately adjacent) layers may not be implemented by the air gap layer, and only alternately arranged layers may be implemented by the air gap layer. In an exemplary embodiment of the inventive concept, a bidirectional air gap pattern is used to allow two continuous layers adjacent (eg, immediately adjacent to) each other in the Z direction to be implemented by an air gap layer. For example, according to an exemplary embodiment, two layers adjacent to (eg, immediately adjacent to) each other may include air gap patterns, respectively. Therefore, according to the exemplary embodiment of the inventive concept, the parasitic capacitance between the conductive patterns corresponding to the network of the timing critical path can be reduced, and the operating speed of the integrated circuit and the chip including the integrated circuit can be improved.

15 is a perspective view illustrating an integrated circuit 700 for routing by applying an air gap pattern according to an exemplary embodiment of the inventive concept.

15, the integrated circuit 700 may correspond to include a first connection point 710 and a second connection point 715 (indicated by CP in FIG. 15) and first to third conductive patterns 720a to 720c (in FIG. 15 by Mx mark) a network. The first connection point 710 and the second connection point 715 can be arranged in the same layer, and the X and Y coordinates of the first connection point 710 and the second connection point 715 can be different. The first to third conductive patterns 720a to 720c may be disposed in the same layer. The first to third conductive patterns 720a to 720c may correspond to, for example, the fifth wiring layer M5 or the sixth wiring layer M6 shown in FIG. 8.

In an exemplary embodiment, the first to third conductive patterns 720a to 720c disposed in the same layer may correspond to timing critical paths. Therefore, the first to third conductive patterns 720a to 720c may be implemented by air gap conductive patterns. For example, the first air gap pattern 730a and the first air gap pattern 735a (denoted by AGPx in FIG. 15) may be disposed on opposite sides of the first conductive pattern 720a. The first conductive pattern 720a and the first air gap pattern 730a and the first air gap pattern 735a may extend in the X direction. The second air gap pattern 730b and the second air gap pattern 735b (indicated by AGPx in FIG. 15) may be disposed on opposite sides of the second conductive pattern 720b. The second conductive pattern 720b and the second air gap pattern 730b and the second air gap pattern 735b may extend in the Y direction. The third air gap pattern 730c and the third air gap pattern 735c (denoted by AGPx in FIG. 15) may be disposed on opposite sides of the third conductive pattern 720c. The third conductive pattern 720c and the third air gap pattern 730c and the third air gap pattern 735c may extend in the X direction.

The second air gap pattern 730b and the second air gap pattern 735b may extend in the Y direction, and the first air gap pattern 730a, the first air gap pattern 735a, and the third air gap pattern 730c and the third air gap pattern 735c may extend in the Y direction. Extend in the X direction. Therefore, in an exemplary embodiment, the first air gap pattern 730a to the third air gap pattern 735c disposed in the same layer may be implemented by a bidirectional air gap pattern. Therefore, in an exemplary embodiment, conductive patterns that extend in different directions and are disposed in the same layer may be implemented by air gap conductive patterns.

FIG. 16 is a perspective view illustrating an integrated circuit 800 for routing by applying an air gap pattern according to an exemplary embodiment of the inventive concept.

Referring to FIG. 16, the integrated circuit 800 may correspond to include a first connection point 810 and a second connection point 815 (indicated by CP in FIG. 16) and first to fourth conductive patterns 820 to 850 (in FIG. 16 by Ma, Ma+2, and Mb, Mb+2 mark) a network. The first connection point 810 and the second connection point 815 can be arranged in different layers, and the X and Y coordinates of the first connection point 810 and the second connection point 815 can be different. The first conductive pattern 820 to the fourth conductive pattern 850 may be disposed in different layers. The first conductive pattern 820 and the second conductive pattern 830 may respectively correspond to the fifth wiring layer M5 and the sixth wiring layer M6 shown in FIG. The seventh wiring layer and the eighth wiring layer above the wiring layer M6.

The integrated circuit 800 may include, for example, a first conductive pattern 820 connected to the first connection point 810; a via 880 disposed on the first conductive pattern 820; and a second conductive pattern 830 disposed on the via 880; The via 885 is disposed on the second conductive pattern 830; the third conductive pattern 840 is disposed on the via 885; the via 890 is disposed on the third conductive pattern 840; and the fourth conductive pattern 850 is disposed On the interlayer window 890. The integrated circuit 800 may further include a first air gap pattern 860 and a first air gap pattern 865 (indicated by AGPa in FIG. 16) disposed on opposite sides of the first conductive pattern 820, and a fourth conductive pattern 850 The second air gap pattern 870 and the second air gap pattern 875 (indicated by AGPb in FIG. 16) on opposite sides of

In an exemplary embodiment, the first to fourth conductive patterns 820 to 850 disposed in different layers may correspond to timing critical paths. In an exemplary embodiment, the first conductive pattern 820 and the fourth conductive pattern 850 may be implemented by an air gap conductive pattern. For example, the first air gap pattern 860 and the first air gap pattern 865 may be disposed on opposite sides of the first conductive pattern 820. The first conductive pattern 820 and the first air gap pattern 860 and the first air gap pattern 865 may extend in the Y direction. The second air gap pattern 870 and the second air gap pattern 875 may be disposed on opposite sides of the fourth conductive pattern 850. The fourth conductive pattern 850 and the second air gap pattern 870 and the second air gap pattern 875 may extend in the X direction.

Therefore, according to an exemplary embodiment, the first air gap pattern 860 and the first air gap pattern 865 may extend in the Y direction, and the second air gap pattern 870 and the second air gap pattern 875 may extend in the X direction. Therefore, in an exemplary embodiment, the first air gap pattern 860, the first air gap pattern 865, and the second air gap pattern 870, the second air gap pattern 875 may be implemented by a bidirectional air gap pattern. Therefore, in an exemplary embodiment, two discontinuous layers that are not adjacent (eg, not adjacent) in the Z direction may be implemented by an air gap layer. For example, in an exemplary embodiment, two layers that are not immediately adjacent to each other (for example, two layers with an intermediate layer disposed therebetween) may be implemented by an air gap layer, and the intermediate layer may not be implemented by an air gap layer. Implementation (for example, the intermediate layer may include an intermetal dielectric containing a general dielectric material and disposed on at least one side thereof).

FIG. 17 is a layout of a standard component 900 included in an integrated circuit according to an exemplary embodiment of the inventive concept.

Referring to FIG. 17, a standard device 900 may be defined by a device boundary CB, and may include a plurality of fins FN, a first active area AR1 and a second active area AR2, a plurality of gate lines GLa, GLb, and GLc(GL), and more A first metal line M1a, M1b, and M1c (M1), and a second metal line M2. The standard element 900 may further include a first air gap pattern AGP1a and a first air gap pattern AGP1b, and a second air gap pattern AGP2a and a second air gap pattern AGP2b. The first metal line M1a, the second via V1 disposed on the first metal line M1a, and the second metal line M2 may correspond to a timing critical network.

The component boundary CB defines the outline of the standard component 900. The placement tool and routing tool (for example, the placement and routing module 13a shown in FIG. 3 or the placement and routing module 22a shown in FIG. 4) can use the component boundary CB to identify the standard component 900. The element boundary CB includes four boundary lines.

The plurality of fins FN may extend in the X direction, and may be arranged substantially parallel to each other along the Y direction that is substantially perpendicular to the X direction. The first active area AR1 and the second active area AR2 may be arranged substantially parallel to each other, and may have different conductivity types. For example, in an exemplary embodiment, three fins FN may be disposed in each of the first active area AR1 and the second active area AR2. However, the concept of the present invention is not limited to this. For example, in an exemplary embodiment, the number of fins disposed in each of the first active area AR1 and the second active area AR2 may be changed.

The plurality of fins FN arranged in the first active area AR1 and the second active area AR2 may be referred to as active fins. Although FIG. 17 only illustrates the active fin, the concept of the present invention is not limited to this. For example, in an exemplary embodiment, the standard device 900 may further include being disposed in the area between the device boundary CB and the first active area AR1, and in the area between the first active area AR1 and the second active area AR2. , Or a dummy fin in the area between the second active area AR2 and the device boundary CB.

The plurality of gate lines GL may extend in the Y direction, and may be arranged substantially parallel to each other in the X direction. The gate line GL may include conductive materials such as, for example, polysilicon, metal, or metal alloy. For ease of description, FIG. 17 illustrates that the standard element 900 includes three gate lines GL. However, the concept of the present invention is not limited to this. For example, according to an exemplary embodiment, the standard element 900 may include four or more gate lines GL extending in the Y direction and arranged parallel to each other in the X direction.

The first via V0 may be respectively disposed on the plurality of gate lines GLa, GLb, and GLc, and may be electrically connected to the plurality of gate lines GLa, GLb, and GLc and the plurality of first A metal wire M1a, M1b, and M1c. The first via V0 may include conductive materials such as, for example, polysilicon, metal, or metal alloy.

The plurality of first metal lines M1 may form a layer disposed on the plurality of gate lines GL. The first metal line M1a may correspond to, for example, the first conductive pattern 620 shown in FIG. 14B. The first metal wire M1 may include conductive materials such as, for example, polysilicon, metal, or metal alloy.

In an exemplary embodiment, the first metal wires M1 may only extend in the Y direction, and may be arranged substantially parallel to each other along the X direction. However, the concept of the present invention is not limited to this. For example, in an exemplary embodiment, a part of a first metal line in the first metal line M1 may extend in the Y direction, and another part of the first metal line may be formed to extend in the X direction. L shape. For ease of description, FIG. 17 illustrates that the standard element 900 includes three first metal wires M1. However, the concept of the present invention is not limited to this. For example, according to an exemplary embodiment, the standard element 900 may include four or more first metal wires M1.

The second via V1 can be respectively disposed on the plurality of first metal wires M1a and M1c, and can connect the plurality of first metal wires M1a and M1c and the second metal wire M2. The second via V1 disposed on the first metal line M1a may correspond to the via 640 shown in FIG. 14B. The second via V1 may include conductive materials such as, for example, polysilicon, metal, or metal alloy.

The second metal line M2 may form a layer disposed on the plurality of first metal lines M1. The second metal line M2 may correspond to, for example, the second conductive pattern 650 shown in FIG. 14B. The second metal wire M2 may include conductive materials such as, for example, polysilicon, metal, or metal alloy.

The second metal wire M2 may only extend in the X direction. However, the concept of the present invention is not limited to this. For example, in an exemplary embodiment, a part of the second metal line M2 may extend in the X direction, and another part of the second metal line M2 may be formed in an L shape extending in the Y direction. For ease of description, FIG. 17 illustrates that the standard element 900 includes a second metal wire M2. However, the concept of the present invention is not limited to this. For example, according to the exemplary embodiment, the standard element 900 may include two or more second metal wires M2.

According to an exemplary embodiment, the first air gap pattern AGP1a and the first air gap pattern AGP1b may be disposed between the plurality of first metal lines M1a to M1c. The first air gap patterns AGP1a and AGP1b may extend in the Y direction. The plurality of first metal lines M1a to M1c and the first air gap pattern AGP1a and the first air gap pattern AGP1b may form a first air gap layer. Therefore, according to an exemplary embodiment of the inventive concept, the parasitic capacitance between the plurality of first metal lines M1a to M1c may be reduced.

According to an exemplary embodiment, the second air gap pattern AGP2a and the second air gap pattern AGP2b may be disposed on opposite sides of the second metal line M2. The second air gap pattern AGP2a and the second air gap pattern AGP2b may extend in the X direction. The second metal line M2 and the second air gap pattern AGP2a and the second air gap pattern AGP2b may form a second air gap layer. Therefore, according to an exemplary embodiment of the inventive concept, the parasitic capacitance between the second metal line M2 and the adjacent metal line can be reduced.

As described with reference to FIGS. 1 to 17, according to an exemplary embodiment of the inventive concept, in the process of designing the layout of an integrated circuit, a timing critical path can be selected from a plurality of timing paths in the placed standard components, and At least one network can be selected from the networks of the selected timing critical path. Subsequently, the selected at least one network can be pre-routed at the air gap layer, and the non-critical path network and/or the timing critical path can be pre-routed at the normal layer (for example, in the case of no air gap layer). The unselected network is routed. Therefore, according to exemplary embodiments of the inventive concept, a high-performance integrated circuit can be implemented at low cost by using a small amount of air gap layers.

FIG. 18 is a block diagram illustrating a storage medium 1000 according to an exemplary embodiment of the inventive concept.

The exemplary embodiments of the inventive concept may be directly implemented in hardware, implemented in software executed by a processor, or implemented in a combination of the hardware and the software. The software module can be tangibly implemented on a non-temporary program storage device (such as the storage medium 1000 shown in FIG. 18).

Referring to FIG. 18, the storage medium 1000 can store a component library 1100, layout data 1200, a placement and routing program (P&R program) 1300, and a timing analysis program 1400. The storage medium 1000 is a computer-readable storage medium (for example, a non-transitory computer-readable storage medium), and may include a storage medium that can be read by a computer to provide instructions and/or data to the computer. The instructions can be executed by the processor of the computer. The computer-readable storage medium 1000 may include, for example, magnetic media or optical media (for example, magnetic disks, magnetic tapes, compact disc read-only memory (CD-ROM), digital versatile disc read-only memory ( digital versatile disk-ROM, DVD-ROM), recordable disc (Compact Disk-Recordable, CD-R), rewritable disc (CD-Rewritable, CD-RW), recordable digital versatile disc (DVD-Recordable, DVD-R), or DVD-Rewritable (DVD-RW)), volatile memory or non-volatile memory (such as random access memory, read-only memory, or flash Memory), non-volatile memory that can be accessed through the Universal Serial Bus (USB) interface, and microelectromechanical system (MEMS). However, the computer-readable storage medium 1000 is not limited to this. The computer-readable storage medium can be inserted into the computer, can be integrated into the computer, or can be combined with the computer through communication media such as a wired network or a wireless network.

The component library 1100 may be a standard component library, and may include information about standard components that are units constituting an integrated circuit. In an exemplary embodiment, the information about the standard components may include layout information needed to generate the layout. In an exemplary embodiment, the information about the standard components may include timing information required for verification or simulation of the layout, for example.

The layout data 1200 may include physical information about the layout generated by placing and routing operations. In an exemplary embodiment, the layout data 1200 may include, for example, the width and pitch values of the conductive patterns, and the number and size of the air gap patterns arranged between the conductive patterns.

The placement and routing program 1300 may include a plurality of instructions for implementing a method of generating the layout of an integrated circuit by using a standard component library according to an exemplary embodiment. For example, the placement and routing program 1300 can be used to perform operations S110 and S130 shown in FIG. 1, operations S210, S260, and S270 shown in FIG. 5, or operations S310, S320, and S350 shown in FIG. And operation S360.

The timing analysis program 1400 may be, for example, a static timing analysis (STA) program. Static timing analysis can correspond to an analog method that calculates the expected timing of a digital circuit. Timing analysis can be performed on all timing paths of the placed standard components, and timing analysis results can be output. The timing analysis program 1400 can be used to perform, for example, operation S120 shown in FIG. 1, operations S240 and S250 shown in FIG. 5, or operation S330 shown in FIG. 6.

In an exemplary embodiment, the storage medium 1000 may further store the analysis program. The analysis program may include a plurality of instructions for executing the method of analyzing the integrated circuit based on the input data defining the integrated circuit. In an exemplary embodiment, the storage medium 1000 may further store a data structure. The data structure may include storage space for extracting specific information from the component library 1100 or managing data generated in the process of analyzing the characteristics of the integrated circuit using an analysis program.

Although the concept of the invention has been specifically illustrated and explained with reference to the exemplary embodiments of the concept of the invention, those skilled in the art should understand that without departing from the spirit and scope of the concept of the invention defined by the scope of the following patent applications , Can make various changes in form and details.

10, 20‧‧‧Integrated circuit design system 11, 21a‧‧‧Processor 13‧‧‧Working memory 13a, 22a‧‧‧Placement and routing module/component 13b, 22b‧‧‧ Timing analysis module 15 ‧‧‧Input/Output Device 17, 23‧‧‧Auxiliary Storage 19‧‧‧Bus 21‧‧‧User Device 21b‧‧‧User Interface 22‧‧‧Integrated Circuit Design Platform 23a‧‧‧Component Library database 23b‧‧‧Layout database 81, 101‧‧‧Wiring structure 100‧‧‧Time critical network 200, 300, 400, 600, 700, 800, IC, IC'‧‧‧Integrated circuit 210, 310, 410, 610, 710, 810, CP1‧‧‧First connection point 215,315,415,615,715,815, CP2‧‧‧Second connection point 220,420, CPT‧‧‧Conductive pattern 230, 235, 430, 435, AGP, AGP1, AGP1', AGP2, AGP2'‧‧‧Air gap pattern 320, 620, 720a, 820, CPT1, Ma‧‧‧First conductive pattern 330, 335, 630, 635, 730a , 735a, 860, 865, AGP1a, AGP1b‧‧‧First air gap pattern 340, V0‧‧‧First via 345, V1‧‧‧Second via 350, 650, 720b, 830, CPT2 Ma+2‧‧‧Second conductive pattern 360, 365, 660, 665, 730b, 735b, 870, 875, AGP2a, AGP2b‧‧‧Second air gap pattern 640, V5, V6, V7, 880, 885, 890 ‧‧‧Interlayer windows 720c, 840, CPT3, Mb, Mx‧‧‧The third conductive pattern 730c, 735c‧‧‧The third air gap pattern 850, Mb+2‧‧‧The fourth conductive pattern 900‧‧‧Standard Component 1000‧‧‧Storage media/computer readable storage media 1100‧‧‧Component library 1200‧‧‧Layout data 1300‧‧‧Placement and routing program 1400‧‧‧Timing analysis program AGL‧‧‧Air gap layer AGPa‧ ‧‧First Air Gap Pattern/Air Gap Pattern AGPb‧‧‧Air Gap Pattern/Second Air Gap Pattern AGPx‧‧‧First Air Gap Pattern/Second Air Gap Pattern/Third Air Gap Pattern AR1‧‧‧第An active area AR2‧‧‧The second active area BM1‧‧‧First barrier layer BM2‧‧‧Second barrier layer CB‧‧‧Component boundary CP‧‧‧First connection point/second connection point FN‧‧‧ Fins GL, GLa, GLb, GLc‧‧‧Gate line ILD1‧‧‧First insulating layer ILD2‧‧‧Second insulating layer M1‧‧‧First wiring layer/first metal line M1a, M1b, M1c‧‧ ‧First metal wire M2‧‧‧Second wiring layer /Second metal wire M2¢‧‧‧Second wiring layer M3‧‧‧Third wiring layer M5‧‧‧Fifth wiring layer/Discontinuous fifth wiring layer M6‧‧‧Sixth wiring layer/Middle wiring layer M7 ‧‧‧Seventh wiring layer/Middle wiring layer M8‧‧‧Discontinuous eighth wiring layer/Eighth wiring layer P1‧‧‧First pin P2‧‧‧Second pin S10‧‧‧Integrated circuit design Operation/Process/Operation S10A, S10B‧‧‧Method S20‧‧‧Integrated circuit manufacturing process/Process S110, S120, S130, S140, S150, S210, S230, S240, S250, S310, S320, S330, S340, S350 , S360, S370‧‧‧Operation S220‧‧‧Placement operation/Operation S260, S270‧‧‧Pre-routing operation/Operation TCP‧‧‧Timing critical path X, Y, Z‧‧‧Direction

The above and other features of the inventive concept will become more apparent by describing in detail the exemplary embodiments of the inventive concept with reference to the accompanying drawings. In the accompanying drawings:

FIG. 1 is a flowchart illustrating a method of manufacturing an integrated circuit according to an exemplary embodiment of the inventive concept.

2A and 2B are cross-sectional views illustrating integrated circuits each including an air gap layer according to an exemplary embodiment of the inventive concept.

3 and 4 illustrate an integrated circuit design system according to an exemplary embodiment of the inventive concept.

FIG. 5 is a flowchart illustrating a method of designing an integrated circuit according to an exemplary embodiment of the concept of the present invention.

Fig. 6 is a flowchart of a method of designing an integrated circuit according to an exemplary embodiment of the concept of the present invention.

FIG. 7 is a graph showing a timing analysis result according to an exemplary embodiment of the inventive concept.

FIG. 8 illustrates a wiring structure for routing using an air gap layer according to an exemplary embodiment of the inventive concept.

9A to 9E are perspective views illustrating a timing critical network for routing with an air gap layer according to an exemplary embodiment of the inventive concept.

FIG. 10 illustrates a wiring structure for routing using a normal layer according to an exemplary embodiment of the inventive concept.

FIG. 11A is a plan view illustrating an integrated circuit for routing by applying an air gap pattern according to an exemplary embodiment of the inventive concept.

FIG. 11B is a perspective view illustrating the integrated circuit shown in FIG. 11A according to an exemplary embodiment of the inventive concept.

FIG. 12A is a plan view illustrating an integrated circuit for routing by applying an air gap pattern according to an exemplary embodiment of the inventive concept.

FIG. 12B is a perspective view illustrating the integrated circuit shown in FIG. 12A according to an exemplary embodiment of the inventive concept.

FIG. 13A is a plan view illustrating an integrated circuit for routing by applying an air gap pattern according to an exemplary embodiment of the inventive concept.

FIG. 13B is a perspective view illustrating the integrated circuit shown in FIG. 13A according to an exemplary embodiment of the inventive concept.

14A is a plan view illustrating an integrated circuit for routing by applying an air gap pattern according to an exemplary embodiment of the inventive concept.

FIG. 14B is a perspective view illustrating the integrated circuit shown in FIG. 14A according to an exemplary embodiment of the inventive concept.

15 is a perspective view illustrating an integrated circuit for routing by applying an air gap pattern according to an exemplary embodiment of the inventive concept.

FIG. 16 is a perspective view illustrating an integrated circuit for routing by applying an air gap pattern according to an exemplary embodiment of the inventive concept.

FIG. 17 is a layout of standard components included in an integrated circuit according to an exemplary embodiment of the inventive concept.

FIG. 18 is a block diagram illustrating a storage medium according to an exemplary embodiment of the inventive concept.

S10‧‧‧Integrated circuit design operation/process/operation

S20‧‧‧Integrated circuit manufacturing process/process

S110, S120, S130, S140, S150‧‧‧Operation

Claims (25)

A computer-implemented method for manufacturing an integrated circuit includes: placing a plurality of standard components, the plurality of standard components defining the integrated circuit; selecting timing from a plurality of timing paths included in the placed standard components Critical path; selecting at least one network from a plurality of networks included in the critical timing path as at least one critical timing network; pre-routing the at least one critical timing network with an air gap layer; The selected network is routed; the at least one timing critical network that is pre-routed and the unselected network that is routed are used to generate a layout; and the integrated circuit is manufactured based on the layout. According to the computer-implemented method described in item 1 of the scope of patent application, the unselected network is routed without the air gap layer. The computer-implemented method according to the first item of the patent application, wherein the air gap layer includes an air gap pattern, and the unselected network is routed in a layer that does not include the air gap pattern. According to the computer-implemented method described in claim 1, wherein the unselected network is included in at least one non-critical path among the plurality of timing paths. According to the computer-implemented method described in item 1 of the scope of patent application, the unselected network is included in the timing critical path. The computer-implemented method as described in item 1 of the scope of patent application, wherein the total timing delay from the input of the timing critical path to the output of the timing critical path exceeds the timing limit. The computer-implemented method described in claim 1, wherein manufacturing the integrated circuit includes: generating a mask based on the layout; and manufacturing the integrated circuit using the mask. The computer-implemented method described in item 1 of the scope of the patent application further includes: attempting to route the placed standard components; and performing timing analysis on the standard components that are attempted to route to generate timing analysis data, wherein The timing critical path is selected from the plurality of timing paths based on the timing analysis data. For example, the computer-implemented method described in item 1 of the scope of patent application further includes: performing timing analysis on the standard component to generate timing analysis data, wherein the timing critical path is based on the timing analysis data from the multiple Choose from one timing path. According to the computer-implemented method described in item 9 of the scope of patent application, the at least one network is selected as the at least one timing critical network based on the timing analysis data. The computer-implemented method described in item 1 of the scope of patent application, wherein the multiple standard components are placed and the at least one timing critical network is pre-routed And routing the unselected network is performed during the back-end design process of the integrated circuit design process. In the computer-implemented method described in item 1 of the scope of the patent application, the multiple standard components are placed using a placement tool and a routing tool. The computer-implemented method according to the first item of the patent application, wherein the at least one timing critical network includes: a first conductive pattern extending in a first direction; a second conductive pattern different from the first direction Extending in the second direction; and a first via window electrically connecting the first conductive pattern and the second conductive pattern, wherein the air gap layer includes: a first air gap pattern, in the first And a second air gap pattern extending in the second direction and disposed on the first side of the first conductive pattern; and a second air gap pattern extending in the second direction and disposed on the first side of the second conductive pattern. According to the computer-implemented method described in item 13 of the scope of patent application, the first direction is substantially perpendicular to the second direction. The computer-implemented method described in item 13 of the scope of patent application, wherein the first conductive pattern and the second conductive pattern are continuously conductive in a third direction different from the first direction and the second direction pattern. Such as the computer implementation method described in item 13 of the scope of patent application, in which all The first conductive pattern and the second conductive pattern are discontinuous conductive patterns in a third direction different from the first direction and the second direction. The computer-implemented method described in the scope of patent application, wherein the at least one timing critical network further includes: a third conductive pattern extending in the second direction and connected via the first via window To the first conductive pattern; a fourth conductive pattern, which extends in the first direction; a second via window, which connects the third conductive pattern and the fourth conductive pattern; and a third via window, The fourth conductive pattern and the second conductive pattern are connected, wherein the third conductive pattern and the fourth conductive pattern are disposed between the first conductive pattern and the second conductive pattern. According to the computer-implemented method described in claim 13, wherein the at least one timing critical network further includes: a third conductive pattern extending in the first direction; and a second via window electrically connected The second conductive pattern and the third conductive pattern, wherein the air gap layer further includes: a third air gap pattern extending in the first direction and disposed on the first side of the third conductive pattern on. The computer implementation method described in item 13 of the scope of patent application, wherein the air gap layer further includes a third air gap pattern and a fourth air gap The third air gap pattern extends in the first direction and is disposed on the second side of the first conductive pattern opposite to the first side of the first conductive pattern, the The fourth air gap pattern extends in the second direction and is disposed on the second side of the second conductive pattern opposite to the first side of the second conductive pattern. The computer-implemented method according to claim 1, wherein the at least one network selected as the at least one timing critical network is based on at least one of the height and the width of the at least one network To choose. The computer-implemented method according to claim 1, wherein the at least one network selected as the at least one timing critical network is based on the interface window electrically connected to the at least one network Choose at least one of height and width. An integrated circuit, comprising: a first conductive pattern extending in a first direction; a second conductive pattern extending in a second direction different from the first direction; and a first via window arranged in a third direction Between the first conductive pattern and the second conductive pattern, and electrically connect the first conductive pattern to the second conductive pattern; the first air gap pattern extends in the first direction and Disposed on the first side of the first conductive pattern; a second air gap pattern extending in the first direction and disposed on the second side of the first conductive pattern, wherein the first conductive pattern The first side of and The second side of the first conductive pattern is opposite; a third air gap pattern that extends in the second direction and is disposed on the first side of the second conductive pattern; and a fourth air gap pattern, Extending in the second direction and disposed on the second side of the second conductive pattern, wherein the first side of the second conductive pattern is opposite to the second side of the second conductive pattern . An integrated circuit, comprising: a first conductive pattern extending in a first direction; a second conductive pattern extending in a second direction different from the first direction; and a first via window arranged in a third direction Between the first conductive pattern and the second conductive pattern, and electrically connect the first conductive pattern to the second conductive pattern; the first air gap pattern extends in the first direction and Disposed on the first side of the first conductive pattern; and a second air gap pattern extending in the second direction and disposed on the first side of the second conductive pattern. An integrated circuit comprising: a first conductive pattern extending in a first direction; a second conductive pattern extending in a second direction crossing the first direction; and a third conductive pattern extending in the first direction Extending upward; a first air gap pattern extending in the first direction and disposed on the first side of the first conductive pattern; A second air gap pattern extending in the second direction and disposed on the first side of the second conductive pattern; and a third air gap pattern extending in the first direction and disposed on the first side Three conductive patterns on the first side, wherein the first conductive pattern, the second conductive pattern, the third conductive pattern, the first air gap pattern, the second air gap pattern, and the first conductive pattern The three air gap patterns are arranged in the same layer, and the first conductive pattern is electrically connected to the second conductive pattern. A standard component for defining an integrated circuit, including: a first active area; a second active area; a plurality of fins extending in a first direction; a plurality of first metal wires in a second Extending in the direction; a second metal line extending in the first direction, wherein the plurality of first metal lines and the second metal line are arranged in the first active area and the second active area A plurality of first air gap patterns extending in the second direction and disposed between the plurality of first metal wires; and a second air gap pattern extending in the first direction and disposed between On the first side of the second metal wire.

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