TWI602181B - Memory system and method for operating test device to transmit fail address to memory device - Google Patents

Description

Memory system and method of using the test component to transmit a failed address to a memory component

Embodiments of the inventive concept relate to a memory system, and more particularly to a method and an element for repairing a memory cell by testing a memory element including a non-volatile storage element using a test element, and including The system of components.

Semiconductor wafers are fabricated in accordance with semiconductor fabrication procedures and then tested in the form of wafers, dies or packages using test equipment. Through testing, defective parts or defective wafers can be selected. The semiconductor wafer is repaired by repairing such defective memory cells when some of the memory cells of the semiconductor wafer are defective.

Recently, as programs for manufacturing semiconductor wafers such as dynamic random access memory (DRAM) have become more and more fine, it has become more and more likely that errors occur during the manufacturing process. Moreover, even if no errors are detected during the initial test period, an error may still occur during the operation of the wafer. For solution To solve this problem, various test methods and components have been developed.

Embodiments of the inventive concept provide a test element for reliably repairing a memory cell.

Embodiments of the inventive concept also provide a test method for reliably repairing memory cells.

Embodiments of the inventive concept also provide a memory system including test elements and methods for reliably repairing memory cells.

The technical objects of the inventive concept are not limited to the above disclosure; other objects may become apparent to those skilled in the art from the following description.

According to an aspect of the inventive concept, a memory system includes: a memory element including a non-volatile storage element having a matrix array structure of at least N×M, wherein N and M each represent an integer equal to or greater than 2; and testing An element configured to test the memory element. A failed address detected by the test component is transmitted to the memory component and stored in the non-volatile storage component.

In an embodiment, the test element can comprise a semiconductor wafer.

In an embodiment, the semiconductor wafer may include an error correcting code (ECC) engine, and the non-volatile storage element may include an antifuse array having a matrix array structure of at least N×M, where N And M each represents an integer equal to or greater than 2.

In an embodiment, the semiconductor wafer may include a built-in self-test A (built-in self test; BIST) unit, and the non-volatile storage element may comprise an antifuse array having a matrix array structure of at least N×M, wherein N and M each represent an integer equal to or greater than two.

In an embodiment, the BIST unit can be connected to an ECC engine.

In an embodiment, the semiconductor wafer can include an error correction code (ECC) engine or a built-in self test (BIST) unit, and a failed address memory configured to store the failed address.

In an embodiment, the failed address memory can be controlled by a control unit.

In an embodiment, the semiconductor wafer may include an error correction code (ECC) engine or a built-in self-test (BIST) unit, a failed address memory, an address output unit, a control output unit, a data buffer, and a control unit. .

In an embodiment, the control output unit may control operation of the ECC engine or the BIST unit, the failed address memory, the data buffer, and the control unit.

In an embodiment, the memory chip can be included in a memory controller and connected to a central processing unit (CPU).

In an embodiment, the CPU may supply test commands to the memory component.

In an embodiment, the test command may include a test start command, a test exit command, or a fail address transfer command.

In an embodiment, the test element can be included in a test device.

In an embodiment, the test device may include a pattern generator, a probe card As well as slots.

In an embodiment, the non-volatile storage element may comprise an anti-fuse array having a matrix array structure of at least N x M, wherein N and M each represent an integer equal to or greater than two.

In an embodiment, the memory system can further include a temporary invalidation address store configured to store the failed address.

In an embodiment, the failed address may be stored in the anti-fuse array under the control of the control unit.

In an embodiment, the control unit is enabled in response to a mode enable signal received from the decoding unit.

In an embodiment, the control unit controls writing the failed address to the anti-fuse array or reading the invalid address from the anti-fuse array, and controlling the memory element Outgoing verification results.

In an embodiment, the anti-fuse array can be coupled to a repair address store configured to store the failed address, the repair address store being connectable to being configured to compare the fail bit A comparison unit of the address and the external address, and the comparison unit is connectable to a multiplexer configured to select one of the failed address and the external address.

According to an aspect of the inventive concept, a memory element includes: a temporary fail address storage for temporarily storing a failed address; and a non-volatile storage element having a matrix array structure of at least N×M to store the fail bit Address, where N and M each represent an integer equal to or greater than 2; and a control unit configured to control the storage The transmission of the failed address in the temporary invalidated address store to the non-volatile storage element.

In an embodiment, the non-volatile storage element can comprise an anti-fuse array.

In an embodiment, in order to determine whether the invalidation address is accurately written, the control unit may control reading the invalidation address from the anti-fuse array and control transmission outside the memory component Validation results.

In an embodiment, the control unit can control sensing or stylizing the anti-fuse array.

In an embodiment, the anti-fuse array can be coupled to a repair address store configured to store the failed address, the repair address store being connectable to being configured to compare the fail bit A comparison unit of the address and the external address, and the comparison unit is connectable to a multiplexer configured to select one of the failed address and the external address.

In an embodiment, the temporary invalidation address store is connectable to an address buffer configured to receive an external address.

In an embodiment, the control unit may be activated in accordance with a mode enable signal generated by the decoding unit.

In an embodiment, the decoding unit is connectable to the address buffer and a control buffer configured to receive a control signal.

In accordance with another aspect of the inventive concept, a test component includes an error correction code (ECC) circuit configured to detect and correct a fail bit; a failed address memory configured to store the fail bit The failure address of the element; and the control unit, The configuration is configured to store the failed address in the failed address memory and transmit to the outside according to a test command.

In an embodiment, the ECC circuit can be coupled to a data buffer configured to receive the failed bit.

In an embodiment, the test command may include a test start command, a test exit command, or a fail address transfer command.

In an embodiment, the ECC circuit can include a built-in self-test (BIST) unit.

In an embodiment, the test component can be included in a memory controller and connected to a central processing unit (CPU).

In an embodiment, the test element can be included in a test device.

In an embodiment, the test device may further include a pattern generator, a probe card, and a slot.

According to another aspect of the inventive concept, a method of operating a test component to transmit a failed address includes: using an error correction code (ECC) circuit to detect the failed address; storing the failed address in a fail bit In the address memory; enter the fail address transfer mode according to the test command; transmit a transfer signal including the mode register set command; and transmit the invalid address.

In an embodiment, the invalidation address may be detected by an ECC engine or a built-in self-test (BIST) unit.

In an embodiment, the transfer signal may further comprise a write command and a wafer select signal.

In an embodiment, the test command may include a command to start transmission of the invalidation address or a command to end the transmission of the invalidation address, and the test command is from a central processing unit (CPU) Given.

According to another aspect of the inventive concept, a method of operating a memory element to write a failed address to the memory element includes: receiving the failed address according to a mode register setting command; The invalidation address is stored in the temporary invalidation address storage; and the failed address is stored in a non-volatile storage element having a matrix array structure of at least N×M, wherein N and M each represent equal to or greater than 2 Integer.

In an embodiment, the method may further comprise checking a storage space of the non-volatile storage element before the failed address is stored in the non-volatile storage element.

In an embodiment, after the invalidation address is stored in the non-volatile storage element, the method may further comprise reading the stored invalidation address.

In an embodiment, after reading the stored invalidation address, the method may further include serially or side-by-side transmitting the verification result indicating the status of the read failed address to the outside.

According to another aspect of the inventive concept, a method of operating a test component to transmit a failed address to a memory component includes: detecting the failed address by an error correction code (ECC) circuit; The address is stored in the invalid address memory; the failed address transmission mode is entered according to the test command; the transmission signal including the mode register setting command is transmitted; the invalid address is transmitted; Receiving the invalidation address by a memory setting command; storing the invalidation address in a temporary invalidation address storage; and storing the invalidation address in a non-volatile matrix structure having at least N×M In the storage element, wherein N and M each represent an integer equal to or greater than 2.

In an embodiment, the method may further comprise checking a storage space of the non-volatile storage element before the failed address is stored in the non-volatile storage element.

According to another aspect of the inventive concept, a memory system includes: a test component configured to provide test data to a memory component; and the memory component includes: a built-in self-test (BIST) unit Configuring to test the memory element; and a non-volatile storage element having a matrix array structure of at least N x M, wherein N and M each represent an integer equal to or greater than two. A failure address generated by testing the memory element with the BIST unit is stored in the non-volatile storage element.

In an embodiment, the non-volatile storage element may comprise an anti-fuse array having a matrix array structure of at least N x M, wherein N and M each represent an integer equal to or greater than two.

In an embodiment, the memory component can further include at least two failed address register arrays configured to temporarily store the failed address.

In an embodiment, the BIST unit may transmit the failed address to the at least two failed address storage register arrays according to a failure flag.

In an embodiment, the failure generation flag may be replaced with a precharge command.

100‧‧‧Test components

110, FAM #1, FAM #2‧‧‧Failed address memory

120, 7101‧‧‧ ECC engine (or BIST unit)

130, 270, 360, 4100, 8110‧‧‧ control unit

140‧‧‧ address output buffer

141‧‧‧Failed address ADD

150‧‧‧Control output unit

151‧‧‧Control signal

160‧‧‧Input/Output (I/O) Data Buffer

200, 5000, 8200‧‧‧ memory components

210‧‧‧ address buffer

220‧‧‧Control buffer

230‧‧‧Data buffer

240‧‧‧Decoding unit

250‧‧‧Repair address register

251‧‧‧Comparative unit

252‧‧‧Multiplexer

260‧‧‧ Temporary invalid address storage

280, 3601~3604, 5100, 7301, 8221‧‧‧ anti-fuse array

290, 320‧‧‧ memory cell array

300‧‧‧ memory components

310, 3801~3804, 5400, 7302, 8222‧‧‧BIST units

330‧‧‧ Temporary Failure Address Memory (FAM)

340‧‧‧Fuse Array

350‧‧‧Fuse Array Information Storage

360, 4100‧‧‧ control unit

1000‧‧‧Non-volatile storage components

1100‧‧‧Fuse Array/System Single Chip (SOC)

1110, 6510‧‧‧ memory controller

1120, 6100, 7100‧‧‧ CPU

1130‧‧ interface

1200‧‧‧Test equipment

1200_1 to 1200_m‧‧‧ position shifter

1210‧‧‧Model generator

1220‧‧ ‧ Probe Card

1230‧‧‧Slots

1300‧‧‧Sense Amplifier

1400‧‧‧First register unit

1500‧‧‧Second register unit

2200‧‧‧ modules

3100‧‧‧Interface Wafer

3200, 3300, 3400, 3500‧‧‧ memory chips

3701~3704‧‧‧Microbump uBump and TSV

4000, 8100‧‧‧ controller

4200, 5200‧‧‧I/O circuits

5300‧‧‧DRAM core

6110, 7110‧‧‧ system bus

6200‧‧‧ Random Access Memory (RAM)

6300, 7200‧‧‧ user interface

6400‧‧‧Data machine

6500‧‧‧ memory system

6520, 7300‧‧‧ memory

8120‧‧‧I/O circuit

8121‧‧‧Controller transmission

8122‧‧‧Controller Receiver

8210‧‧‧I/O circuit

8211‧‧‧ Receiver

8223‧‧‧DRAM core

8500, 8501‧‧‧ optical link

ACT‧‧‧ action order

ADD‧‧‧ invalid address

BL1 to BLn‧‧‧ bit line

CKE‧‧‧ input clock enable signal

CLK‧‧‧ clock signal

CMD‧‧‧Command Line

CS‧‧‧ wafer selection signal

Com, Control‧‧‧ test command

DQ‧‧‧ test data

DQ0 to DQ7‧‧‧ data pins

DQS‧‧‧ data strobe

E/O‧‧‧ Components that convert electrical signals into optical signals

EDQ‧‧‧ test data

F-CA‧‧‧ failure address

F-RA‧‧‧ column failure address

FAM1 to FAMn‧‧‧Failed Address Array

Info_FA, Info_DC‧‧‧ Information

MRS‧‧‧ mode register setting command

O/E‧‧‧ Components that convert optical signals into electrical signals

OUT1 to OUTn‧‧‧Fuse Information

Pre‧‧‧Precharge command

rData, RDQ‧‧‧ reading data

RD‧‧‧ read command

S100, S105, S110, S120, S130, S140, S150, S160, S170, S180, S190, S200, S300, S310, S320, S330, S340, S350, S360, S370‧‧‧ operation

wData‧‧‧Write data

WL1 to WLm‧‧‧ character line

WLP1 to WLPm‧‧‧ voltage signal

WR‧‧‧Write command

The above and other features and advantages of the present invention are apparent from the detailed description of the preferred embodiments of the invention. The drawings are not necessarily to scale,

1 through 4 are conceptual diagrams of a memory system in accordance with an embodiment of the inventive concept.

FIG. 5 illustrates a circuit block diagram of a test element in accordance with an embodiment of the inventive concept.

6A is a diagram illustrating a system single wafer (SOC) including test elements, in accordance with an embodiment of the inventive concept.

FIG. 6B is a diagram illustrating a test apparatus using test elements in accordance with an embodiment of the inventive concept.

FIG. 7 illustrates a circuit block diagram of a memory element in accordance with an embodiment of the inventive concept.

FIG. 8 is a diagram illustrating a non-volatile storage element in accordance with an embodiment of the inventive concept.

FIG. 9 illustrates the structure of a module in accordance with an embodiment of the inventive concept.

10 and 11 are timing diagrams illustrating timings when transmitting a failed address in accordance with an embodiment of the inventive concept.

FIG. 12 is a timing diagram illustrating timings when side-by-side transmission of verification results, according to an exemplary embodiment of the inventive concept.

FIG. 13 is a table illustrating verification results to be performed in parallel transmission according to an exemplary embodiment of the inventive concept.

FIG. 14 is a timing diagram illustrating timings when a verification result is transmitted, according to an exemplary embodiment of the inventive concept.

15 is a table illustrating verification results of a serial transmission in accordance with an exemplary embodiment of the inventive concept.

16 and 17 are timing diagrams illustrating a method of operating a test element in accordance with an illustrative embodiment of the inventive concept.

FIG. 18 is a conceptual diagram of a memory system in accordance with another exemplary embodiment of the inventive concept.

FIG. 19 illustrates a circuit block diagram of a memory element in accordance with another exemplary embodiment of the inventive concept.

20 and 21 are timing diagrams illustrating the operation of a memory element in accordance with an illustrative embodiment of the inventive concept.

FIG. 22 is a flowchart illustrating a method of operating a memory element in accordance with an exemplary embodiment of the inventive concept.

23 is a diagram illustrating an optical link of a memory system in accordance with an illustrative embodiment of the inventive concept.

24 illustrates a through via (TSV) stacked wafer to which a memory system is applied, in accordance with an illustrative embodiment of the inventive concept.

25(a) to 25(d) illustrate various interfaces of a memory system in accordance with an exemplary embodiment of the inventive concept.

26 and 27 are diagrams illustrating system connections of a memory system in accordance with an illustrative embodiment of the inventive concept.

Various embodiments will now be described more fully hereinafter with reference to the accompanying drawings. However, the inventive concept may be embodied in different forms and should not be construed as being limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete. In the figures, like reference numerals indicate similar parts, and, for the sake of clarity, the layers and the size and relative sizes of the layers may be exaggerated.

The terminology used herein is for the purpose of describing particular embodiments, and is not intended to limit the inventive concepts. As used herein, the singular and " It will be further understood that the term "comprising", when used in the specification, is intended to mean the presence of the described features, integers, steps, operations, components and/or components, but does not exclude one or more other features, integers, steps, operations The presence or addition of components, components, and/or groups thereof.

Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning meaning meaning Should be further understood, terms (such as commonly used in dictionaries) The terminology defined should be interpreted as having a meaning consistent with its meaning in the relevant technical context, and should not be interpreted in an idealized or overly formal sense unless explicitly defined herein.

1 through 4 are conceptual diagrams of a memory system in accordance with an embodiment of the inventive concept.

Referring to FIG. 1, a memory system includes a test component 100 and a memory component 200. Test component 100 transmits a control signal that includes a failed address, a command indicating operation of memory component 200, and a data DQ. Although not shown, test component 100 can be included in a memory controller or test device. Memory component 200 includes a dynamic random access memory (DRAM), which is a volatile memory. Alternatively, memory component 200 can comprise non-volatile memory, such as magnetoresistive RAM (MRAM), resistive RAM (RRAM), phase change RAM (PRAM), or "NAND" (NAND) flash memory. Memory element 200 includes a non-volatile storage element that includes an array of antifuse. Non-volatile storage elements are used to store the failed address. Non-volatile storage elements can include MRAM, RRAM, PRAM, "reverse" flash memory, or the like. The memory element 200 operates in accordance with a control signal and transmits the data DQ to the test element 100.

Referring to Figure 2, test component 100 includes an error correction code (ECC) engine. The ECC engine detects the invalidation bit and the invalidation address from the data DQ received from the memory component 200, and corrects the failed bit. The memory component 200 includes an array of antifuse and stores the failed address received from the test component 100. The failed memory cell is repaired based on the stored invalidation address.

Referring to Figure 3, test component 100 includes a built-in self-test (BIST) unit. The BIST unit tests the test component 100 or the memory component 200. To test the memory component 200, test data is generated and the test data is transmitted to the memory component 200. The failed memory cell is detected by writing test data to the memory cell and then reading the test data from the memory cell. The invalidation address, which is the address of the failed memory cell, is temporarily stored in the test component 100 and then transmitted to the memory component 200. The transmitted failed address is stored in the anti-fuse array to repair the failed memory cell.

Referring to Figure 4, test component 100 includes a BIST unit and an ECC engine. The memory component 200 is tested using a BIST cell and the failed address is stored in an antifuse array included in the memory component 200. The invalidation address, which is the address of the failed bit that occurred during operation of the memory component 200, is detected using the ECC engine and stored in the antifuse array of the memory component 200. When the memory element 200 is not operating, the memory element 200 can be tested using a BIST unit based on test commands given from a central processing unit (CPU). When the memory component 200 is operating, the failed address can be detected using the ECC engine.

FIG. 5 illustrates a circuit block diagram of test component 100 in accordance with an embodiment of the present inventive concepts.

Referring to FIG. 5, the test component 100 includes a failed address memory 110, an ECC engine (or BIST unit) 120, a control unit 130, an address output buffer 140, a control output unit 150, and an input/output (I/O) data buffer. 160. The failed address memory 110 stores the invalidated address ADD 141 detected by the ECC engine (or BIST unit) 120. The failed address memory 110 can be implemented as a scratchpad, statically following Machine access memory (SRAM) or non-volatile memory. The address output buffer 140 is coupled to the failed address memory 110 and transmits the failed address ADD 141 to the memory element 200. The control output unit 150 transmits the control signal 151 to the memory element 200, which includes a read command, a write command, a precharge command, a mode register setting command, and the like. The control output unit 150 is connected to and controlled by the control unit 130. The I/O data buffer 160 is controlled by the control unit 130 and receives or transmits input/output (I/O) data. The I/O data may only contain test data for testing the memory component 200. The data received from the memory component 200 is transmitted to the ECC engine (or BIST unit) 120 via the I/O material buffer 160. The control unit 130 is connected to the ECC engine (or BIST unit) 120, the failed address memory 110, the address output unit 140, the control output unit 150, and the I/O data buffer 160. The control unit 130 receives a test command from the CPU. The test command may include a test start command, a test exit command, a command indicating the start of transmission of the invalidation address ADD, and a command indicating termination of transmission of the invalidation address ADD. The invalidation address ADD 141 detected by the ECC engine (or BIST unit) 120 is controlled in accordance with the received test command for storage in the failed address memory 110. Moreover, the transmission of the fail address ADD 141 and the control signal 151 is controlled using the address output unit 140 and the control output unit 150.

FIG. 6A is a diagram illustrating a system single wafer (SOC) 1100 including test elements 100, in accordance with an embodiment of the present inventive concepts.

Referring to FIG. 6A, the SOC 1100 includes a CPU 1120, a memory controller 1110, and an interface 1130. Memory controller 1110 includes test component 100. Test component 100 includes an ECC engine (or BIST unit) 120, a failing address memory (FAM) 110, a control unit, etc., which are components of the test component 100 illustrated in FIG. The memory controller 1110 is connected to the CPU 1120 to receive the test command Com from the CPU 1120. The test command Com may include a test start command, a test exit command, a command indicating the start of transmission of the invalidation address, and a command indicating termination of transmission of the invalidation address. The invalidation address, control signals, and data are transmitted to the memory component 200 via the interface 1130.

FIG. 6B is a diagram illustrating a test apparatus 1200 using test elements 100 in accordance with an embodiment of the present inventive concepts.

Referring to FIG. 6B, test device 1200 includes test component 100, pattern generator 1210, probe card 1220, and slot 1230. Pattern generator 1210 generates various test data to test memory component 200. The probe card 1220 directly contacts the test pad of the memory component 200 via the probe to transmit test data. Slot 1230 secures memory element 200 during testing of memory element 200.

FIG. 7 illustrates a circuit block diagram of a memory element 200 in accordance with an embodiment of the present inventive concepts.

Referring to FIG. 7, the memory component 200 includes an address buffer 210, a control buffer 220, a data buffer 230, a decoding unit 240, a repair address register 250, a comparison unit 251, a multiplexer (MUX) 252, and a temporary Failed address store 260, control unit 270, antifuse array 280 (which is a non-volatile storage element), and memory cell array 290.

The invalidation address is received via the address buffer 210 and temporarily stored in the temporary The time expires in the address store 260. Temporary invalidation address store 260 can be implemented as a scratchpad array, SRAM, or non-volatile memory. The decoding unit 240 receives the control signal via the control buffer 220, performs decoding, and generates a mode enable signal. The control signals include read commands, write commands, precharge commands, mode register settings signals, and the like. Control unit 270 is activated in response to the mode enable signal and stores the failed address in anti-fuse array 280, which is a non-volatile memory storage element. Control unit 270 senses the stored invalidation address to verify that the failed address is correctly programmed. The stylized result (verification result) is transmitted to the test element 100 via the data output pin. The anti-fuse array 280, which is a non-volatile storage element, is coupled to the repair address register 250, and the repair address register 250 is configured to store the failed address. Repair address register 250 is coupled to comparison unit 251, and comparison unit 251 is configured to compare the failed address with the external address. Comparison unit 251 is coupled to multiplexer (MUX) 252, and multiplexer 252 is configured to select one of a failed address and an external address. The material received via the I/O data buffer 230 can be used as a wafer selection signal (component designation) for selecting a wafer on the memory module.

FIG. 8 is a diagram illustrating a non-volatile storage element 1000 in accordance with an embodiment of the inventive concept.

Referring to FIG. 8, the non-volatile storage element 1000 includes: a fuse array 1100a on which a plurality of fuses 1110a are disposed; level shifters 1200_1 to 1200_m which generate a high voltage to change a plurality of fuses 1110a And a sense amplifier 1300 that senses/amplifies information stored in the fuse array 1100a. The non-volatile storage element 1000 further includes a first register unit 1400 to And the second register unit 1500 stores the fuse data generated when reading the information stored in the anti-fuse array 1100a. Each of the first register unit 1400 and the second register unit 1500 can be implemented as a shift register including a plurality of registers.

The fuse array 1100a includes a plurality of fuses 1110a in which information is stored. The fuse array 1100a may comprise a laser fuse (whose connection is controlled via laser radiation) or may comprise an electrical fuse (whose connection is controlled according to electrical signals). In addition, the fuse array 1100a may include an anti-fuse whose state changes from a high resistance state to a low resistance state in accordance with an electrical signal (eg, a high voltage signal). The fuse array 1100a may include any of the various types of fuses described above. In the following embodiments, it is assumed that the fuse array 1100a is an antifuse array including an antifuse. Also, hereinafter, the information stored in the anti-fuse or the data read from the anti-fuse will be referred to as fuse data.

The antifuse array 1100a has an array structure in which a plurality of fuses 1110a are disposed at intersections of a plurality of columns and a plurality of rows. For example, if the antifuse array 1100a includes m rows and n columns, the antifuse array 1100a includes m×n antifuse 1110a. The antifuse array 1100a includes m word lines WL1 to WLm and n bit lines BL1 to BLn for accessing antifuse disposed in m columns, and The n bit lines BL1 to BLn are disposed corresponding to n rows to deliver information read from the plurality of antifuse 1110a.

The anti-fuse array 1100a stores various information related to the operation of the non-volatile storage element 1000. For example, the anti-fuse array 1100a can be stored for setting Multi-segment setting information for the operating environment of the non-volatile storage element 1000. The multi-segment setting information is programmed by changing the states of the plurality of anti-fuse 1110a by supplying the voltage signals WLP1 to WLPm supplied from the level shifters 1200_1 to 1200_m to the anti-fuse array 1100a. Unlike a general fuse circuit (for example, a laser fuse circuit or an electric fuse circuit), information is stored in a plurality of antifuse by staging a plurality of antifuse 1110a from a high resistance state to a low resistance state. In 1110a. The plurality of antifuse 1110a may have a structure in which a dielectric layer is disposed between two conductive layers (ie, a capacitor structure). The plurality of antifuse 1110a are programmed to collapse the dielectric layer by applying a high voltage between the two conductive layers.

After the antifuse array 1100a is programmed, a read operation is performed on the antifuse array 1100a while starting the driving of the non-volatile storage element 1000. The read operation can be performed on the anti-fuse array 1100a simultaneously with the driving of the anti-fuse array 1100a or at a predetermined set time after the driving of the non-volatile storage element 1000. In the antifuse array 1100a, a word line selection signal is supplied via the word lines WL1 to WLm, and information stored in the selected antifuse 1110a is supplied to the sense amplifier 1300 via the bit lines BL1 to BLn. . According to the characteristics of the array structure, the information stored in the anti-fuse array 1100a can be randomly accessed by driving the word lines WL1 to WLm and the bit lines BL1 to BLn.

For example, since the word lines WL1 to WLm are sequentially driven, the plurality of antifuse 1110a are sequentially accessed from the first column to the mth column in the antifuse array 1100a. Information sequentially accessed from the plurality of antifuse 1110a is provided to the sense amplifier 1300. Sense amplifier 1300 includes one or more sense amplifier circuits. For example, When antifuse array 1100a includes n rows, sense amplifier 1300 includes n sense amplifier circuits corresponding to n rows. The n sense amplifier circuits are connected to n bit lines BL1 to BLn, respectively. FIG. 8 illustrates a state in which two sense amplifier circuits are disposed corresponding to each of the n bit lines BL1 to BLn. For example, the odd sense amplifier circuit and the even sense amplifier circuit are disposed corresponding to the first bit line BL1. The odd sense amplifier circuit senses/amplifies and outputs information stored in the antifuse 1110a connected to the odd digital line WL1, WL3, WL5, . The even sense amplifier circuit senses/amplifies and outputs information stored in the antifuse 1110a connected to the even digital line WL2, WL4, WL6, . However, the inventive concept is not limited thereto, and the sense amplifier circuit may be configured in any of various shapes. For example, only one sense amplifier circuit may be configured corresponding to one bit line, or three or more sense amplifier circuits may be configured corresponding to one bit line.

The sense amplifier 1300 senses/amplifies and outputs information accessed from the anti-fuse array 1100a. The sensed/amplified information is fuse data OUT1 to OUTn, which are actually used to set the operating environment of the non-volatile storage element 1000. As described above, since FIG. 8 illustrates a situation in which two sense amplifier circuits are disposed corresponding to each bit line, actually, a piece of fuse data (for example, the first fuse data OUT1) may include odd-numbered fuse data and Even-numbered fuse data.

The fuse data OUT1 to OUTn output from the sense amplifier 1300 are supplied to the first register unit 1400. The first register unit 1400 can be implemented as a shift register in which a plurality of registers are connected in series for sequential delivery signal. Moreover, the number of registers included in the first register unit 1400 is less than the number of the plurality of anti-fuse 1110a included in the anti-fuse array 1100a. Moreover, the number of registers included in the first register unit 1400 can be determined based on the number of rows included in the anti-fuse array 1100a. For example, when the anti-fuse array 1100a includes n rows, the first register unit 1400 can include n registers. In addition, as described above, when two sense amplifier circuits are configured corresponding to each bit line, the first register unit 1400 may include 2×n registers.

The first register unit 1400 receives the fuse data OUT1 to OUTn in units of columns in the anti-fuse array 1100a. For example, when one column is selected from the columns in the anti-fuse array 1100a, the fuse data OUT1 to OUTn stored in the anti-fuse 1110a connected to the word line of the selected column are juxtaposed to the first temporary The memory unit 1400. The first register unit 1400 supplies the fuse data OUT1 to OUTn to the second register unit 1500 by shifting the supplied fuse data OUT1 to OUTn in units of bits. The second register unit 1500 can be implemented as a shift register in which a plurality of registers are connected in series to sequentially deliver signals. The number of registers included in the second register unit 1500 can be equal to the number of the plurality of antifuse 1110a included in the antifuse array 1100a. The fuse data OUT1 to OUTn stored in the second register unit 1500 can be used as information for setting the operating environment of the non-volatile storage element 1000. For example, some of the fuse data OUT1 to OUTn stored in the second register unit 1500 can be used to replace the memory cells (not shown) included in the non-volatile storage element 1000 with redundant memories. Cell information Info_FA, and some of the fuse data OUT1 to OUTn are available The trimming information Info_DC for adjusting the voltage generated in the non-volatile storage element 1000.

In order to store the fuse data OUT1 to OUTn from the anti-fuse array 1100a, a register is required: a register connected to the sense amplifier 1300 to temporarily store the fuse data OUT1 to OUTn; and adjacent to the fuse information OUT1 Various circuit blocks to the non-volatile storage element 1000 of OUTn (eg, a column decoder and a row decoder or a direct current (DC) voltage generator) are disposed to provide the fuse data OUT1 to OUTn to the circuit block. Save.

According to an exemplary embodiment of the inventive concept, the first register unit 1400 receives the fuse data OUT1 to OUTn from the sense amplifier 1300, and transmits the fuse data OUT1 to OUTn to be disposed adjacent to the circuit blocks. The second register unit 1500. In particular, the anti-fuse array 1100a has an array structure, and the first register unit 1400 includes a register, the number of which corresponds to the number of rows included in the anti-fuse array 1100a. Therefore, the number of registers included in the first register unit 1400 is smaller than the number of the plurality of anti-fuse 1110a included in the anti-fuse array 1100a. For example, when one sense amplifier circuit is configured corresponding to each bit line, the first register unit 1400 includes n sense amplifier circuits. Therefore, the number of registers in the first register unit 1400 associated with the fuse data OUT1 to OUTn need not be m×n, and thus may be n. In particular, even if a large number of antifuse 1110a is included in the antifuse array 1100a, the number of registers included in the first register unit 1400 may be limited to n according to the structure of the antifuse array 1100a. . Therefore, the number of registers included in the first register unit 1400 can be prevented. Increase proportionally.

FIG. 9 illustrates the structure of a module 2200 in accordance with an embodiment of the inventive concept.

Referring to Figure 9, module 2200 includes a memory that includes a memory component in accordance with an illustrative embodiment of the inventive concept. For example, module 2200 includes eight DRAMs. Each of the DRAMs includes an anti-fuse array (which is a non-volatile storage element). When the invalidation address is stored in the DRAM 5, the memory controller can select the DRAM 5 by transmitting the data "0" only to the DRAM 5. An antifuse array included in each of the DRAMs is used to store the generated invalidation address in the DRAM. The command and address are shared by eight DRAMs.

10 and 11 are timing diagrams illustrating timings when transmitting a failed address in accordance with an embodiment of the inventive concept.

Referring to FIG. 10, a mode register setting command MRS, an action command ACT, a read command RD, and a write command WR are received via a command line CMD. The column fail address F-RA and the row fail address F-CA are received via the address line ADD. In the module 2200 of FIG. 9, the DRAM 5 can be selected among the eight DRAMs by receiving only the material "0" (logic low) via the data pin DQ. Since the data received via the data pins DQ0 to DQ7 all become logical "low", the failed address is stored in the anti-fuse array (which is a non-volatile storage element included in the DRAM 5). After sequentially inputting the mode register setting command MRS, the action command ACT, and the write command WR, and inputting the column fail address F-RA and the row fail address F-CA, the data "0" is used as the data pin DQ. The final wafer selection data is supplied and the failed address is stored in the antifuse array. This section is a failed address transfer section. Test The certificate section is a section between when the programmed invalidation address is read according to the read command RD and when another mode register setting command MRS is received. When another mode register setting command MRS is input after receiving the read command, the verification process is completed.

The timing diagram of FIG. 11 is similar to the timing diagram of FIG. 10 except that the memory cells corresponding to the failed address are repaired by receiving only the column fail address F-RA via the address line ADD. Moreover, when the verification procedure is executed to read the invalidation address again, the verification procedure is completed according to the precharge command, and the current mode is exited.

FIG. 12 is a timing diagram illustrating timings when side-by-side transmission of verification results, according to an exemplary embodiment of the inventive concept.

Referring to FIG. 12, when the mode register setting command MRS, the action command ACT, and the write command WR are input via the command line CMD, the column fail address F-RA and the row fail address F-CA are stored in the anti-fuse. Array (which is a non-volatile memory element). Then, by checking the column fail address F-RA and the row fail address F-CA, the stored column fail address F-RA and the row fail address F-CA are checked to verify the state, and The resulting verification results are transmitted to the test element 100 via data pins DQ0, DQ1, and DQ2. For example, the logic low ("L") verification result is transmitted in parallel via data pins DQ0, DQ1, and DQ2. The values transferred to other data pins DQ3, ..., DQ7 are not recognized by the memory controller.

FIG. 13 is a table illustrating a result of be transmitted in parallel verification according to an exemplary embodiment of the inventive concept.

Referring to Figure 13, the storage is stored in an anti-fuse array (which is non-volatile) Check the result of the verification result in the memory). The verification results transmitted via data pins DQ0, DQ1, and DQ2 are all logic low (status 1), meaning that the stylization is normally completed and the failed bit is replaced with a column redundant memory cell. The verification results transmitted via data pins DQ0, DQ1, and DQ2 are logic low, low, and high, respectively (status 2), meaning that the stylization is normally completed and the failed bit is replaced with a row redundant memory cell. The verification results transmitted via data pins DQ0, DQ1, and DQ2 are logic low, high, and low, respectively (status 3), meaning that the stylization is normally completed and the failed bit is replaced with a single redundant memory cell. The verification results transmitted via data pins DQ0, DQ1, and DQ2 are logic low, high, and high (state 4), respectively, meaning that no specific meaning is given for future use. The conditions 5 to 8 each indicate that the stylization is not completely performed. The verification results transmitted via data pins DQ0, DQ1, and DQ2 are logic high, low, and low (condition 5), respectively, indicating a problem with the rupture procedure performed on the memory cell. The verification results transmitted via data pins DQ0, DQ1, and DQ2 are logic high, low, and high, respectively (status 6), meaning that the rupture procedure is still in progress. In this case, the verification can be temporarily delayed, and then the verification is requested according to the read command RD. The verification results transmitted via data pins DQ0, DQ1, and DQ2 are logic high, high, and low (status 7), meaning that no redundant memory cells are available. Therefore, the failing bit cannot be repaired and should therefore be replaced with another memory cell. The verification results transmitted via data pins DQ0, DQ1, and DQ2 are all logic high (state 8) meaning that the current wafer is not selected. The verification results are transmitted side by side to the test element 100 via data pins DQ0, DQ1, and DQ2.

FIG. 14 is a diagram illustrating transmission verification in accordance with an exemplary embodiment of the inventive concept Timing diagram of the timing at the time of the result.

Referring to Figure 14, the verification results illustrated in Figure 13 are transmitted in series. For example, the 3-bit verification result is transmitted in series via the data pin DQ0. The same 3-bit verification result can be transmitted to the test element 100 via the data pin DQ7.

15 is a table illustrating a be transmitted in series verification result in accordance with an exemplary embodiment of the inventive concept.

Referring to Figure 15, Condition 1 (LLL) indicates that the failed bit is replaced with a column redundant memory cell. For example, the 3-bit verification result is serially transmitted to the test component 100 via a data pin DQ. Condition 6 (HLH) indicates that the rupture procedure is still in progress, with the 3-bit verification result serially transmitted to test element 100 via data pins DQ0, DQ1, DQ2, and DQ3.

16 and 17 are timing diagrams illustrating a method of operating a test element in accordance with an illustrative embodiment of the inventive concept.

Referring to Figure 16, the test elements perform fail address detection and transmission as described below. First, the ECC engine or the BIST unit is used to detect the invalidation address (operation S100). Next, the detected invalidation address is stored in the failed address memory (FAM) (operation S105). Next, the fail address transmission mode is entered in accordance with the test command given from the CPU (operation S110). The test command includes a test start command, a test exit command, a command indicating the start of transmission of the invalidation address, and a command indicating the end of the transmission of the invalidation address. Next, the mode register setting command, the wafer selection signal, and the fail address are transmitted (operation S120).

Referring to FIG. 17, the memory component receives the mode register setting command and writes. The command, the wafer selection signal, and the failed address (operation S130). Next, the failed address is stored in the temporary invalidated address storage (operation S140). Next, the mode of programming the non-volatile storage element is entered (operation S150). Next, the storage space of the anti-fuse array, which is a non-volatile storage element, is inspected (operation S160). Next, the antifuse array, which is a non-volatile storage element, is programmed (operation S170). Next, the stylized data is read to verify the stored invalidation address (operation S180). Next, the status of the stored material is checked, and then the verification result is transmitted to the outside (operation S190). Finally, the invalid bit is replaced with another memory cell (operation S200).

FIG. 18 is a conceptual diagram of a memory system in accordance with another exemplary embodiment of the inventive concept.

Referring to Figure 18, the memory system includes test component 100 and memory component 200. Test component 100 transmits a failed address, a control signal, and a data DQ. Memory component 200 includes a BIST cell and an anti-fuse array (which is a non-volatile memory component). The BIST unit tests the memory element 200 via the test element 100 based on test commands received from the test element 100 and stores the failed address in an anti-fuse array (which is a non-volatile memory element).

FIG. 19 illustrates a circuit block diagram of a memory device 300 in accordance with another exemplary embodiment of the inventive concept.

Referring to FIG. 19, the memory component 300 includes: a fuse array 340, which is a non-volatile memory constructed to store the failed address as stylized data; a temporary fail address memory (FAM) 330; a fuse Array information storage 350, Configuring to store information about the fuse; control unit 360 configured to control fuse array 340 and fuse array information store 350; BIST unit 310 configured to detect a failed address; Memory cell array 320. The BIST unit 310 receives the test command Control and the test data DQ from the test component, and detects the invalidation address by writing the test data DQ to the memory cell array 320 and then reading the test data DQ from the memory cell array 320. . When a fail bit occurs, the failure flag corresponding to the failed bit and the failed address are transmitted to the FAM 330. The FAM 330 can be implemented as a register containing a plurality of failed address arrays FAM1, ..., FAMn. Control unit 360 may use fuse array information store 350 to check the space of fuse array 340. Control unit 360 can also control the stylized commands and programmatic addresses to be stored in fuse array 340, which is a non-volatile storage element. The test command is supplied to the test component in accordance with the control signal, and thus the BIST unit 310 is activated. And, the failed address stored in the FAM 330 is transmitted to the fuse array 340 according to the control signal.

20 and 21 are timing diagrams illustrating the operation of a memory element in accordance with an illustrative embodiment of the inventive concept.

Referring to Fig. 20, an action command ACT and a read command RD are input via a command line CMD. The test data EDQ is input via the data pin DQ. The test data EDQ is written to the memory cell array, and the read data RDQ is generated by reading the test data EDQ stored in the memory cell array according to the read command RD. When the failure flag signal changes from logic high to logic low, the Nth column address is written to the failed address memory FAM #1. When the failure flag occurs again, the address of the N+1th column is written to Failed address memory FAM #2. The command and the data are input in synchronization with the clock signal CLK, and the clock enable signal CKE and the wafer selection signal are also input in synchronization with the clock signal CLK.

Referring to FIG. 21, an action command ACT, a read command RD, and a precharge command Pre are input via the command line CMD. The timing diagram of FIG. 21 is substantially similar to the timing diagram of FIG. 20, except that when the precharge command Pre is input, the Nth column address is transferred to the failed address memory FAM #1, and the pre-input is again input. When the charging command Pre is performed, the N+1th column address is transmitted to the failed address memory FAM #2. The FAM 330 of Figure 19 can be implemented as a scratchpad, SRAM, or the like.

FIG. 22 is a flowchart illustrating a method of operating a memory element in accordance with an exemplary embodiment of the inventive concept.

Referring to FIG. 22, the memory element receives an action command, a write command, and a read command from the test component (operation S300). Next, the BIST unit of the memory element is activated in accordance with the command (operation S310). Next, the failed address is detected, a failure flag is generated, or a precharge command is received (operation S320). Next, the failed address is stored in the failed address memory according to the failure flag or the precharge command (operation S330). Next, the fuse array enters a stylized mode that stylizes the failed address (operation S340). Next, the capacity of the fuse memory is checked (operation S350). Next, the fuse array is programmed (operation S360). Thereafter, the invalidation bit is repaired (operation S370).

23 is a diagram illustrating an optical link of a memory system in accordance with an illustrative embodiment of the inventive concept.

Referring to Figure 23, the memory system includes a controller 8100 and a memory component. 8200. The controller 8100 includes a control unit 8110, a controller transmitter 8121, and a controller receiver 8122. Control unit 8110 includes an ECC engine or a BIST unit. The controller transmitter 8121 includes an element E/O that converts an electrical signal into an optical signal. Controller receiver 8122 includes an element O/E that converts the optical signal into an electrical signal. The memory element 8200 includes an anti-fuse array 8221 (which is a non-volatile storage element), a BIST unit 8222, a DRAM core 8223, a transmitter 8312, and a receiver 8211. Transmitter 8312 includes an element E/O that converts an electrical signal into an optical signal. The receiver 8211 includes an element O/E that converts an optical signal into an electrical signal. Controller 8100 and memory element 8200 are coupled via optical link 8500 and optical link 8501 to transmit and receive data. According to another exemplary embodiment of the inventive concept, data may be transmitted and received via an optical link. The I/O circuit 8120 of the controller 8100 and the I/O circuit 8210 of the memory element 8200 are connected via an optical link 8500 and an optical link 8501.

24 illustrates a through-silicon-via (TSV) stacked wafer to which a memory system is applied, in accordance with an illustrative embodiment of the inventive concept.

Referring to FIG. 24, the interface wafer 3100 is disposed as the lowermost layer, and the memory wafers 3200, 3300, 3400, and 3500 are sequentially disposed on the interface wafer 3100. The interface chip 3100 can include an ECC engine or BIST unit, a memory controller, and a CPU. Memory wafers 3200, 3300, 3400, and 3500 include antifuse arrays 3601, 3602, 3603, and 3604, which are non-volatile storage elements, and BIST units 3801, 3802, 3803, and 3804. The failure address of the memory chip is detected by using a test component (not shown) of the interface chip 3100, and is stored in the memory. In the antifuse array of the wafer. These wafers are connected via microbumps uBump and TSVs (3701, 3702, 3703, and 3704) formed therein. For example, the number of stacked wafers can be one or more.

25(a) to 25(d) illustrate various interfaces of a memory system in accordance with an exemplary embodiment of the inventive concept.

Referring to Figure 25(a), the memory system includes a controller 4000 and a memory component 5000. The controller 4000 includes a control unit 4100 and an I/O circuit 4200. Control unit 4100 can include an ECC engine or a BIST unit. The memory component 5000 includes a DRAM core 5300, an antifuse array 5100 (which is a non-volatile storage element), a BIST cell 5400, and an I/O circuit 5200. The I/O circuit 4200 of the controller 4000 includes a command, control signal, address and data strobe DQS for transferring to the memory device 5000 and transferring the data DQ to the memory device 5000 and receiving the data DQ from the memory device 5000. interface. The failed address is transmitted via the interface.

Referring to FIG. 25(b), the I/O circuit 4200 of the controller 4000 includes a wafer selection signal CS and an address transferred to the memory device 5000 and a data DQ to the memory device 5000 and self-memory using a packet. Element 5000 receives the interface of the material DQ. The failed address is transmitted via the interface.

Referring to FIG. 25(c), the I/O circuit 4200 of the controller 4000 includes a wafer selection signal CS, an address and a write data wData transmitted to the memory device 5000 and received from the memory device 5000 using a packet. The interface of the data rData. The failed address is transmitted via the interface.

Referring to FIG. 25(d), the I/O circuit 4200 of the controller 4000 includes a command, address and data DQ for transmitting to the memory device 5000 and receiving commands, addresses and data DQ from the memory device 5000 and self-memory. Element 5000 receives the interface of wafer select signal CS. The failed address is transmitted via the interface.

26 and 27 are diagrams illustrating system connections of a memory system in accordance with an illustrative embodiment of the inventive concept.

Referring to Figure 26, memory 7300 includes an anti-fuse array 7301, which is a non-volatile memory, and a BIST unit 730. The CPU 7100 includes a BIST unit or an ECC engine 7101. The memory 7300, the CPU 7100, and the user interface 7200 are connected via the system bus 7110.

Referring to Figure 27, memory system 6500 includes a memory 6520 (which includes an anti-fuse array and a BIST unit) and a memory controller 6510 (which includes a BIST or ECC engine). The memory system 6500, the CPU 6100, the random access memory (RAM) 6200, the user interface 6300, and the data machine 6400 are connected via the system bus 6110.

A memory test component, method, and system according to an exemplary embodiment of the inventive concept may detect a failed address of a failed memory cell included in a memory component and repair the failed memory by repairing the failed memory cell Cell. Test elements can be used to test and repair memory components even during operation of the wafer or after wafer encapsulation. Therefore, the failure of the memory element due to the failed memory cell can be reduced, thereby improving the operational reliability of the memory element.

The foregoing is illustrative of embodiments and is not to be construed as limiting. although, Having described several embodiments, it will be readily apparent to those skilled in the art that many modifications may be made to the embodiments without departing from the novel teachings and advantages. Accordingly, all such modifications are intended to be included within the scope of the inventive concepts as defined by the appended claims. In the context of the patent application, the component plus function clause is intended to cover the structures described herein as performing the described functions, and not only the structural equivalents but also equivalent structures. Therefore, the present invention is to be understood as being limited to the specific embodiments of the invention, and the modifications and other embodiments of the disclosed embodiments are intended to be included within the scope of the appended claims.

100‧‧‧Test components

200‧‧‧ memory components

Control‧‧‧ test order

DQ‧‧‧ test data

Claims (20)

A method of operating a dynamic random access memory (DRAM) device having a memory cell array, a non-volatile memory (NVM) memory array, and a failed address memory (FAM), The method includes receiving a first mode register setting command to enter a repair mode, receiving an enable command and a column fail address, the column invalidation address indicating a column of the memory cell array including at least one defective memory cell Storing the column invalidation address in the invalidation address memory; staging the column failure address in the non-volatile memory storage array; after staging the column invalidation address, Receiving a precharge command; and after performing the precharge operation, receiving a second mode register setting command according to the precharge command to exit the repair mode. The method of claim 1, wherein the non-volatile memory storage array comprises an anti-fuse array, the anti-fuse array is an M×N array, wherein N and M each represent equal to or greater than 2 The integer. The method of claim 1, wherein the DRAM device further comprises a control unit configured to control storing the column invalidation address in the failed address memory and from the failed address memory The column fail address is output to the DRAM device to program the column fail address in the non-volatile memory storage array. The method of claim 1, wherein the method further comprises It is checked whether the stylized column fail address is properly programmed in the non-volatile memory storage array. The method of claim 4, wherein the checking the stylized column fail address comprises reading the stylized column fail address from the non-volatile memory storage array and comparing The stylized column fail address and the received column fail address. The method of claim 5, wherein performing the checking of the stylized column fail address is after staging the column fail address and before receiving the precharge command. A method of operating a dynamic random access memory (DRAM) device having a memory cell array, a non-volatile memory (NVM) memory array, and a failed address memory (FAM), The method includes receiving a first mode register setting command to enter a repair mode, receiving an enable command and a column fail address, the column invalidation address indicating a column of the memory cell array including at least one defective memory cell Receiving a write command and a row invalidation address, the row invalidation address indicating a row of the memory cell array including at least one defective memory cell; storing the column failure address and the row failure address In the failed address memory; staging the column fail address and the row invalidation address in the non-volatile memory bank array; staging the column fail address and the row Receive pre-charge after the invalid address An electric command; and after performing the pre-charging operation, receiving the second mode register setting command according to the pre-charge command to exit the repair mode. The method of claim 7, wherein the non-volatile memory storage array comprises an anti-fuse array, the anti-fuse array is an M×N array, wherein N and M each represent equal to or greater than 2 The integer. The method of claim 7, wherein the DRAM device further comprises: a control unit configured to control storing the column fail address in the failed address memory and from the failed address The memory outputs the column fail address to the DRAM device to program the column fail address in the non-volatile memory storage array. The method of claim 7, wherein the method further comprises checking whether the stylized column fail address and the stylized row fail address are correctly programmed in the non-volatile memory In the storage array. The method of claim 10, wherein the checking the stylized column fail address and the stylized row fail address comprises: reading from the non-volatile memory storage array Staging the column invalidation address and the stylized row invalidation address, and comparing the stylized column invalidation address and the stylized row invalidation address and the received column invalidation, respectively Address. The method of claim 11, wherein performing the checking of the stylized column fail address and the stylized row invalidation address is to program the column invalidation address and the row After the invalid address, and receiving the pre-charged life Before the order. A memory system includes: a memory controller configured to transmit a first mode register setting command and an enable command to be merged into a column fail address, a precharge command, and a second mode register setting command; and a dynamic random An access memory (DRAM) device having a memory cell array, a non-volatile memory (NVM) memory array, and a failing address memory (FAM), configured to: receive a a mode register setting command to enter a repair mode; receiving the enable command and the column fail address, the column fail address indicating a column of the memory cell array including at least one defective memory cell; storing The column failure address is located in the invalid address memory; the column invalidation address is programmed in the non-volatile memory storage array; after the column invalidation address is programmed, the receiving station And pre-charging the command; and after performing the pre-charging operation, receiving the second mode register setting command according to the pre-charge command to exit the repair mode. The memory system of claim 13, wherein the non-volatile memory storage array comprises an anti-fuse array, and the anti-fuse array is an M×N array, wherein N and M each represent equal to or An integer greater than 2. The memory system of claim 13, wherein the The DRAM device further includes a control unit configured to control storage of the column fail address in the failed address memory and output the column fail address from the failed address memory to the DRAM device, The column invalidation address is stylized in the non-volatile memory storage array. The memory system of claim 13, wherein the DRAM device is further configured to check whether the stylized column fail address is properly programmed in the non-volatile memory storage array. The memory system of claim 16, wherein the DRAM device is configured to read the non-volatile memory storage array during inspection of the stylized column fail address A stylized column invalidation address and comparing the stylized column invalidation address with the received column invalidation address. The memory system of claim 17, wherein the DRAM device is configured to perform the checking of the stylized column fail address after staging the column invalidation address, and at a receiving station Before the precharge command. The memory system of claim 13, wherein the memory controller is further included in a built-in self-test (BIST) unit in the memory device to detect the column invalidation address. The memory system of claim 13, wherein the memory controller further comprises an error correction code (ECC) circuit to determine the column failure address.