TWI503892B - High voltage device and manufacturing method thereof - Google Patents

Description

High voltage component and method of manufacturing same

The present invention relates to a high voltage component and a method of manufacturing the same, and more particularly to a high voltage component using a low voltage component process and a method of fabricating the same.

1 shows a schematic cross-sectional view of a prior art lateral double diffused metal oxide semiconductor (LDMOS) device 100. As shown in FIG. 1, an insulating region 12 is formed in the P-type substrate 11 to electrically isolate the LDMOS device 100 from other components in the substrate 11. The insulating region 12 is, for example, a shallow trench isolation (STI) structure. Or as shown in the local oxidation of silicon (LOCOS) structure. The LDMOS device 100 includes a gate 13, an N-type drift region 14, an N-type source 15, an N-type drain 16, a P-type body region 17, and a P-type body electrode 18. Wherein, the N-type drift region 14, the N-type source 15 and the N-type drain 16 are masked by lithography and/or part or all of the gate 13 and the insulating region 12 to define regions, and The ion implantation technique is used to implant N-type impurities in the form of accelerated ions in a defined region; and the P-type body region 17 and the P-type body electrode 18 are formed by lithography and/or Or all of the gates 13 and the insulating regions 12 are masks, which are defined by ion implantation techniques, and P-type impurities are formed in the defined regions by accelerating ions. The source 15 and the drain 16 are respectively located below the two sides of the gate 13 . Further, in the LDMOS device, a part of the gate 13 is located on the field oxide region 12a.

2 is a schematic cross-sectional view showing a prior art double diffused drain metal oxide semiconductor (DDDMOS) device 200. The main difference from the aforementioned LDMOS device is that the gate 23 of the DDDMOS device is entirely on the surface of the P-type substrate 11. As shown, in the P-type substrate 11, an insulating region 22 is formed to electrically isolate the DDDMOS device 200 from other components in the substrate 11. The insulating region 22 is, for example, a LOCOS structure or an STI structure as shown. The DDDMOS device 200 includes a gate 23, an N-type drift region 24, an N-type source 25, an N-type drain 26, an N-type isolation region 29, a P-type well region 27, and a P-type body electrode 28. The N-type drift region 24, the N-type source 25, the N-type drain 26, and the N-type isolation region 29 are masked by lithography technology and/or with some or all of the gate 23 and the insulating region 22. To define the regions, and to form N-type impurities in the form of accelerated ions in the defined region by ion implantation technology; while the P-type well region 27 and the P-type body pole 28 are formed by lithography. The technique and/or part or all of the gate 23 and the insulating region 22 are masked, the region is defined, and the P-type impurity is implanted into the defined region in the form of accelerated ions by ion implantation technology. . The source 25 and the drain 26 are respectively located below the two sides of the gate 23 .

The LDMOS and DDDMOS components are high voltage components, that is, they are designed to supply higher operating voltages, but when the high voltage components need to be integrated on the same substrate as the generally lower operating voltage components, they are used for components with lower operating voltage. The process requires high-voltage components and low-voltage components to be fabricated with the same ion implantation parameters, so that the ion implantation parameters of the high-voltage components are limited, thereby reducing the breakdown voltage of the high-voltage components and limiting the application range of the components. If the high voltage component collapse protection voltage is not sacrificed, the process step must be added, and the high voltage component is separately fabricated by the steps of different ion implantation parameters, but this will increase the manufacturing cost to achieve the desired collapse protection voltage.

In view of the above, the present invention is directed to the above-mentioned deficiencies of the prior art, and provides a high-voltage component and a manufacturing method thereof, which can improve the breakdown protection voltage of the component operation, increase the application range of the component, and can be integrated in the process without increasing the process steps. Process of low voltage components.

It is an object of the present invention to provide a high voltage component and a method of manufacturing the same.

In order to achieve the above object, the present invention provides a high voltage component formed in a first conductivity type substrate, and another low voltage component formed in the substrate, the substrate having an upper surface, the high voltage component comprising: a drift region Formed under the upper surface, having a second conductivity type; a gate formed over the upper surface, and at least a portion of the drift region being located below the gate; a source and a drain having a second Conductive types are respectively formed under the upper surface of the two sides of the gate, and the drain is located in the drift region, and the drain and the gate are separated by the drift region; and a relaxation region has a second a conductive type formed in the drift region below the upper surface, and the relaxation region is between the gate and the drain, and the relaxation region and one of the low voltage components are lightly doped (lightly doped Region, LDD), formed using the same process steps.

In another aspect, the present invention also provides a method for manufacturing a high voltage component, comprising: providing a first conductive type substrate having an upper surface, and another low voltage component is formed in the substrate; forming a drift region thereon Below the surface, it has a second conductivity type; a gate is formed above the upper surface, and at least a portion of the drift region is located below the gate; respectively, a source and a drain are formed below the upper surface of the gate Having a second conductivity type, and the drain is located in the drift region, and the drain is separated from the gate by the drift region; and a relaxation region is formed in the drift region below the upper surface Having a second conductivity type, and the relaxation region is between the gate and the wave, and the relaxation region and the lightly doped region (LDD) region of the low voltage component are the same The process steps are formed.

In a preferred embodiment, in the high voltage component, the low voltage component further includes a low voltage gate formed over the upper surface; and a low voltage source and a low voltage drain having a second conductivity type, respectively Formed on the upper surface of the lower surface of the low voltage gate, and viewed from above, the low voltage source or/and the low voltage drain is located in the lightly doped drain region; wherein the lightly doped drain The zone is used to mitigate the hot carrier effect of the low voltage component during operation.

In another preferred embodiment, the high voltage component further includes a second conductive type isolation region formed under the upper surface, and the drift region, the source, the drain, and the mitigation region are located in the isolation region. And a first conductive type well region formed in the isolation region below the upper surface, and the isolation region and the drift region, the source, the drain, and the mitigation region are Separating; wherein the high voltage component is a double diffused drain metal oxide semiconductor (DDDMOS) device.

In still another preferred embodiment, the high voltage component further includes: a first conductive type body region formed under the upper surface, wherein the source is located in the body region, and a portion of the body region and the drift region are And a first conductive type body electrode is formed in the body region below the upper surface; wherein the high voltage component is a lateral double diffused metal oxide semiconductor (LDMOS) )element.

In the above high-voltage component, wherein the lightly doped drain region is completed by an ion implantation technique, and the process parameters are different according to whether the second conductivity type is N-type or P-type: when the second conductivity type is N-type The implanted ions are phosphorus-containing ions, the accelerating voltage is 30-120 kV, the implantation dose is 1*10 ¹³ to 6*10 ¹³ ions/cm ² ; and the second conductivity type is P-type: implanted ions For boron-containing ions, the accelerating voltage is 10~100 kV, the implantation dose is 1*10 ¹³ to 6*10 ¹³ ions/cm ² or the implanted ions are boron difluoride ions, and the accelerating voltage is 30~140 The kilovolt is implanted at a dose of 1*10 ¹³ to 6*10 ¹³ ions/cm ² .

The purpose, technical content, features and effects achieved by the present invention will be more readily understood by the detailed description of the embodiments.

The drawings in the present invention are schematic and are mainly intended to represent the process steps and the relationship between the layers, and the shapes, thicknesses, and widths are not drawn to scale.

Referring to Figure 3, there is shown a first embodiment of the present invention. This embodiment shows a schematic cross-sectional view of the present invention applied to the DDDMOS device 300. As shown, the DDDMOS device 300 is formed in the substrate 11, and the substrate 11 has an upper surface 111 and an insulating region 32; wherein the insulating region 32 is used to electrically isolate the DDDMOS device 300 from other components in the substrate 11. The insulating region 32 is, for example, a LOCOS structure or an STI structure as shown. The substrate 11 is, for example, a P type but is not limited to a P type. The DDDMOS device 300 includes a gate 33, an N-type drift region 34, an N-type source 35, an N-type drain 36, an N-type isolation region 39, an N-type mitigation region 31, a P-type well region 37, and a P-type body electrode 38. . The gate 33 is formed above the upper surface 111. The N-type drift region 34, the N-type source 35, the N-type drain 36, the N-type isolation region 39, and the N-type relaxation region 31 are formed under the upper surface 111 by lithography and/or in part or in whole The gate 33 and the insulating region 32 are masks to define regions, and are respectively formed by implanting N-type impurities in the form of accelerated ions in a defined region by ion implantation technology; and the P-type well region 37 And the P-type body electrode 38 is formed under the upper surface 111, and is defined by lithography technology and/or with some or all of the gate 33 and the insulating region 32 as a mask, and the region is defined, and the P-type is performed by ion implantation technology. Impurities, formed in the form of accelerated ions, are implanted within defined areas. The source 35 and the drain 36 are respectively located below the two sides of the gate 33. The drain 36 is located in the drift region 34, and the drain 36 and the gate 33 are separated by a drift region 34, and at least a portion of the drift region 34 is located below the gate 33. The drift region 34, the source 35, the drain 36, and the relaxation region 31 are located in the isolation region 39. In addition, the isolation region 39 is separated from the drift region 34, the source 35, the drain 36, and the relaxation region 31 by the well region 37.

Different from the prior art, in the present embodiment, the DDDMOS device 300 has a relaxation region 31 formed in the drift region 34 below the upper surface of the substrate 11, and the relaxation region 31 is interposed between the gate 33 and the drain 36. The relaxation region 31 and the lightly doped region (LDD) region of the low voltage device also formed in the substrate 11 are formed by the same process steps. Further, the DDDMOS device may have or omit the N-type isolation region 39, the P-type well region 37, and the P-type body electrode 38.

The advantage of this arrangement is that the process can be, but is not limited to, the same process steps using the low voltage components formed in the same substrate 11, without the need for an additional mask or process step, thereby reducing manufacturing costs.

Figures 4A-4F show a second embodiment of the invention. This embodiment exemplifies a method of manufacturing the DDDMOS device 300 of the first embodiment of the present invention. It is also explained how to use the low voltage component process in the substrate 11 to complete the high voltage component of the present invention. For convenience of description, in FIGS. 4A-4F, two different elements, which are separated by a horizontal dashed line but are formed on the substrate 11 from left to right; respectively, are a low voltage NMOS element 400, and a high voltage element of the present invention, such as but not limited to The DDDMOS device 300 is shown. As shown in FIG. 4A, first, for example, but not limited to, a P-type substrate 11 having an upper surface 111 is provided. Next, in the P-type substrate 11, a P-type well region 47 is formed under the upper surface 111 of the low-voltage NMOS device 400, and in the DDDMOS device 300, an insulating region 32, an N-type isolation region 39, and a P-type well are formed under the upper surface 111. Zone 37, and an N-type drift zone 34.

Next, in the P-type substrate 11, as shown in FIG. 4B, a gate electrode 43 is formed in the low voltage NMOS device 400 on the upper surface 111, and a gate electrode 33 is formed in the DDDMOS device 300.

Next, as shown in FIG. 4C, the photoresist 31b or other mask formed by the same mask simultaneously defines the mitigation region 31 of the LDD region 41 of the low voltage NMOS device 400 and the high voltage device DDDMOS device 300, and Accelerated ions of the illustrated N-type impurity are implanted into the P-type substrate 11 to form the LDD region 41 in the low voltage NMOS device 400, and simultaneously form the relaxation region 31 in the high voltage device DDDMOS device 300. The N-type source 45 and the N-type drain 46 are respectively formed under the upper surface 111 of the two sides of the gate 43 and are viewed from a top view (not shown), the source 45 or/and the low-voltage drain 46. Located in the lightly doped drain region 41; the lightly doped drain region 41 serves to mitigate the hot carrier effect of the low voltage NMOS device 400 during operation.

Next, as shown in FIG. 4D, N-type sources 45 and 35 and N-type drains 46 and 36 are formed in the low voltage NMOS device 400 and the high voltage DDDMOS device 300 by the same or different process steps. Therein, the source 45 or/and the drain 46 is located in the lightly doped drain region 41 as viewed from a top view (not shown).

Next, as shown in FIG. 4E, a P-type body electrode 38 is formed in the high voltage DDDMOS device 300. Finally, please refer to FIG. 4F to complete the low voltage NMOS device 400 and the high voltage DDDMOS device 300, respectively.

It should be noted that the lightly doped bungee region 41 and the mitigation region 31 are completed by the same ion implantation process step, and the process parameters are different according to the lightly doped bungee region 41 and the mitigation region 31 being N-type or P-type: N Type: implanted ions are phosphorus-containing ions, accelerating voltage is 30~120 kV, implant dose is 1*10 ¹³ to 6*10 ¹³ ions/cm ² ; and P type: implanted ions are boron The ion has an accelerating voltage of 10 to 100 kV, an implantation dose of 1*10 ¹³ to 6*10 ¹³ ions/cm ² or an implanted ion containing boron difluoride ions, and an acceleration voltage of 30 to 140 kV. The implantation dose is 1*10 ¹³ to 6*10 ¹³ ions/cm ² .

Fig. 5 shows a third embodiment of the present invention. Unlike the first embodiment, this embodiment applies the present invention to a high voltage LDMOS device. As shown, the LDMOS device 500 is formed in the substrate 11, and the substrate 11 has an upper surface 111 and an insulating region 52. The insulating region 32 is used to electrically isolate the LDMOS device 500 from other components in the substrate 11. The insulating region 52 is, for example, STI structure or LOCOS structure as shown. The substrate 11 is, for example, a P type but is not limited to a P type. The LDMOS device 500 includes a gate 53, an N-type drift region 54, an N-type source 55, an N-type drain 56, an N-type relaxation region 51, a P-type body region 57, and a P-type body electrode 58. Wherein, the N-type drift region 54, the N-type source 55, the N-type drain 56, and the N-type relaxation region 51 are formed under the upper surface 111 by lithography and/or with some or all of the gates 53, The insulating region 52 is a mask to define each region, and is formed by ion implantation technology to implant N-type impurities in a defined region in the form of accelerated ions; and the P-type body region 57 and the P-type body The pole 58 is formed under the upper surface 111, and is defined by lithography technology and/or with some or all of the gate 53 and the insulating region 52 as a mask, and the region is defined, and the P-type impurity is ion-implanted. Formed in the defined area of the implant in the form of accelerated ions. The source 55 and the drain 56 are respectively located below the two sides of the gate 53. The drain 56 and the gate 53 are separated by a drift region 54. The source 55 and the body pole 58 are formed in the body region 57 below the upper surface 111. The relaxation region 51 is formed in the drift region 54 below the upper surface 111, and the relaxation region 51 is interposed between the gate 53 and the drain 56, and the relaxation region 51 is formed in the low voltage component also formed in the substrate 11. The lightly doped bungee region is formed using the same process steps.

The present invention has been described with reference to the preferred embodiments thereof, and the present invention is not intended to limit the scope of the present invention. In the same spirit of the invention, various equivalent changes can be conceived by those skilled in the art. For example, other process steps or structures, such as deep well areas, may be added without affecting the main characteristics of the components; for example, lithography is not limited to reticle technology, and may include electron beam lithography; In all the embodiments, the isolation region, the drift region, the source, the drain, the relaxation region, and the like are not limited to the N-type, and the well region, the body region, the body electrode, and the like are not limited to the P-type, but may be interchanged as long as other doping. The area can be adjusted accordingly; for example, the invention is not limited to application to DDDMOS elements and LDMOS elements, and can also be applied to other high voltage elements. The above and other equivalent variations are intended to be covered by the scope of the invention.

11. . . Substrate

12,22,32,52. . . Insulating area

12a. . . Field oxidation zone

13,23,33,43,53. . . Gate

14,24,34,54. . . Drift zone

15,25,35,45,55. . . Source

16,26,36,46,56. . . Bungee

17. . . Body area

18, 28, 38, 58. . . Body pole

29,39. . . quarantine area

31,51. . . Mitigation zone

37. . . Well area

41. . . LDD area

100,200,300,500. . . High voltage component

111. . . Upper surface

400. . . Low voltage component

Figure 1 shows a schematic cross-sectional view of a prior art LDMOS device 100.

Figure 2 shows a schematic cross-sectional view of a prior art DDDMOS device 200.

Figure 3 shows a first embodiment of the invention.

Figures 4A-4F show a second embodiment of the invention.

Fig. 5 shows a third embodiment of the present invention.

11. . . Substrate

31. . . Mitigation zone

32. . . Insulating area

33. . . Gate

34. . . Drift zone

35. . . Source

36. . . Bungee

37. . . Well area

38. . . Body pole

39. . . quarantine area

300. . . High voltage component

Claims (10)

a high voltage component formed in a first conductive type substrate, and another low voltage component formed in the substrate, the substrate having an upper surface, the high voltage component comprising: a drift region formed under the upper surface, having a second conductivity type; a gate formed over the upper surface, and at least a portion of the drift region is located below the gate; a source and a drain, both having a second conductivity type, respectively formed on both sides of the gate Below the upper surface, and the drain is located in the drift region, and the drain and the gate are separated by the drift region; and a relaxation region having a second conductivity type formed under the upper surface In the drift region, the relaxation region is between the gate and the drain, and the relaxation region and a lightly doped region (LDD) region of the low voltage component utilize the same process step Formed. The high voltage component of claim 1, wherein the low voltage component further comprises: a low voltage gate formed over the upper surface; and a low voltage source and a low voltage drain having a second conductivity type, respectively Formed on the upper surface of the lower surface of the low voltage gate, and viewed from above, the low voltage source or/and the low voltage drain is located in the lightly doped drain region; wherein the lightly doped drain The zone is used to mitigate the hot carrier effect of the low voltage component during operation. The high voltage component of claim 1, further comprising: a second conductivity type isolation region formed under the upper surface, wherein the drift region, the source, the drain, and the mitigation region are located And a first conductive type well region formed in the isolation region below the upper surface, and the isolation region and the drift region, the source, the drain, and the mitigation region are The well regions are separated; wherein the high voltage component is a double diffused drain metal oxide semiconductor (DDDMOS) component. The high voltage component of claim 1, further comprising: a first conductive type body region formed under the upper surface, wherein the source is located in the body region; and a first conductive type body pole, Formed in the body region below the upper surface; wherein the high voltage component is a lateral double diffused metal oxide semiconductor (LDMOS) device. The high voltage component according to claim 2, wherein the relaxation region and the lightly doped drain region are completed by the same ion implantation process step, and the process parameter is based on the second conductivity type being N-type or P-type. Different: when the second conductivity type is N type: the implanted ions are phosphorus ions, the accelerating voltage is 30~120 kV, the implantation dose is 1*10 ¹³ to 6*10 ¹³ ions/cm ² ; and the second When the conductivity type is P type: the implanted ions are boron-containing ions, the accelerating voltage is 10~100 kV, the implantation dose is 1*10 ¹³ to 6*10 ¹³ ions/cm ² or the implanted ions are difluoride. The boron ion has an accelerating voltage of 30 to 140 kV and an implantation dose of 1*10 ¹³ to 6*10 ¹³ ions/cm ² . A method for manufacturing a high voltage component, comprising: providing a first conductive type substrate having an upper surface, and another low voltage component is formed in the substrate; forming a drift region below the upper surface, having a second conductivity type; Forming a gate above the upper surface, and at least a portion of the drift region is located below the gate; respectively forming a source and a drain under the upper surface of the gate on both sides, each having a second conductivity type, and the a drain is located in the drift region, and the drain is separated from the gate by the drift region; and a relaxation region is formed in the drift region below the upper surface, having a second conductivity type, and the mitigation The region is between the gate and the drain, and the relaxation region and a lightly doped region (LDD) region of the low voltage component are formed by the same process step. The method of manufacturing the high voltage component of claim 6, wherein the low voltage component further comprises: a low voltage gate formed over the upper surface; and a low voltage source and a low voltage drain having a second conductivity type Formed on the upper surface of the lower surface of the low voltage gate respectively, and viewed from above, the low voltage source or/and the low voltage drain is located in the lightly doped drain region; wherein the light doping The drain region is used to mitigate the hot carrier effect of the low voltage component during operation. The method for manufacturing a high voltage component according to claim 6, further comprising: forming a second conductivity type isolation region below the upper surface, and the drift region, the source, the drain, and the mitigation region are located In the isolation region; and forming a first conductivity type well region in the isolation region below the upper surface, and between the isolation region and the drift region, the source, the drain, and the mitigation region, The well regions are separated; wherein the high voltage component is a double diffused drain metal oxide semiconductor (DDDMOS) component. The method for manufacturing a high voltage component according to claim 6, further comprising: forming a first conductive type body region under the upper surface, wherein the source is located in the body region; and forming a first conductive type body The body region is located below the upper surface; wherein the high voltage component is a lateral double diffused metal oxide semiconductor (LDMOS) device. The method for manufacturing a high voltage component according to claim 7, wherein the relaxation region and the lightly doped drain region are completed by the same ion implantation process step, and the process parameter is N-type or P according to the second conductivity type. Type: different: when the second conductivity type is N type: the implanted ions are phosphorus ions, the accelerating voltage is 30~120 kV, and the implantation dose is 1*10 ¹³ to 6*10 ¹³ ions/cm ² ; When the second conductivity type is P type: the implanted ions are boron-containing ions, the accelerating voltage is 10 to 100 kV, the implantation dose is 1*10 ¹³ to 6*10 ¹³ ions/cm ² or the implanted ions are included. The boron difluoride ion has an accelerating voltage of 30 to 140 kV and an implantation dose of 1*10 ¹³ to 6*10 ¹³ ions/cm ² .