TWI459472B - 半導體裝置及其製造方法 - Google Patents

半導體裝置及其製造方法 Download PDF

Info

Publication number
TWI459472B
TWI459472B TW097127794A TW97127794A TWI459472B TW I459472 B TWI459472 B TW I459472B TW 097127794 A TW097127794 A TW 097127794A TW 97127794 A TW97127794 A TW 97127794A TW I459472 B TWI459472 B TW I459472B
Authority
TW
Taiwan
Prior art keywords
region
drain region
gate electrode
source region
conductivity type
Prior art date
Application number
TW097127794A
Other languages
English (en)
Other versions
TW200924071A (en
Inventor
Masayuki Hashitani
Original Assignee
Seiko Instr Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Seiko Instr Inc filed Critical Seiko Instr Inc
Publication of TW200924071A publication Critical patent/TW200924071A/zh
Application granted granted Critical
Publication of TWI459472B publication Critical patent/TWI459472B/zh

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/08Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/0843Source or drain regions of field-effect devices
    • H01L29/0847Source or drain regions of field-effect devices of field-effect transistors with insulated gate
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/1025Channel region of field-effect devices
    • H01L29/1029Channel region of field-effect devices of field-effect transistors
    • H01L29/1033Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure
    • H01L29/1037Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure and non-planar channel
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312Gate electrodes for field effect devices
    • H01L29/42316Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42372Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out
    • H01L29/4238Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out characterised by the surface lay-out
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007Multistep manufacturing processes
    • H01L29/66075Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409Unipolar field-effect transistors
    • H01L29/66477Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66568Lateral single gate silicon transistors
    • H01L29/66575Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007Multistep manufacturing processes
    • H01L29/66075Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409Unipolar field-effect transistors
    • H01L29/66477Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66568Lateral single gate silicon transistors
    • H01L29/66613Lateral single gate silicon transistors with a gate recessing step, e.g. using local oxidation
    • H01L29/66621Lateral single gate silicon transistors with a gate recessing step, e.g. using local oxidation using etching to form a recess at the gate location
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76Unipolar devices, e.g. field effect transistors
    • H01L29/772Field effect transistors
    • H01L29/78Field effect transistors with field effect produced by an insulated gate
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76Unipolar devices, e.g. field effect transistors
    • H01L29/772Field effect transistors
    • H01L29/78Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7816Lateral DMOS transistors, i.e. LDMOS transistors
    • H01L29/7825Lateral DMOS transistors, i.e. LDMOS transistors with trench gate electrode

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Electrodes Of Semiconductors (AREA)

Description

半導體裝置及其製造方法
本發明關於需要高驅動性能之包括金屬氧化物半導體(MOS)電晶體的半導體裝置,及關於製造該半導體裝置之方法。
MOS電晶體為電子學中核心電子元件。重要的是達成MOS電晶體之小型化及其高驅動性能。賦予高驅動性能與MOS電晶體的方法之一為擴充閘極寬度以降低開啟(ON)阻抗。然而,有一項問題即大的閘極寬度需要MOS電晶體的寬佔用區。解決之道為提出一種技術,藉此提供大的閘極寬度同時抑制MOS電晶體之佔用區增加。(例如,參照JP 2006-49826 A)。
以下,將參照圖4A至4D描述習知半導體裝置。如圖4A之透視圖中所示,習知半導體裝置包括設於井17中之溝部8及設於溝部8中和閘極絕緣膜9之頂面上之閘極電極10。在井17之表面部中,閘極電極10的一側配置源極區12及另一側配置汲極區13。圖4B為沿圖4A之切割面A-A之平面部的截面圖,及圖4C為沿圖4A之切割面B-B的截面圖。如圖4C中所示,由於閘極電極10係設於溝部8中,沿閘極電極10之B-B方向延伸至與閘極絕緣膜9接觸之曲線的總長度提供閘極寬度。
如上述,由於閘極部具有包括凸部和凹部之溝結構,實際閘極寬度可大於簡單地於平坦面上製造之閘極電極的寬度。因此,可減少每單位區域之ON阻抗而不降低MOS電晶體之承受電壓。
本發明之發明者已發現一問題,即在上述半導體裝置之結構中,實際驅動性能無法達到預期之驅動性能。亦發現到驅動性能隨著閘極長度而改變並傾向於在短閘極長度裝置中較低。
假設此現象係由源極及汲極之間所產生之通道中不均勻的電流所造成:如圖4D中所示,大部分電流係沿未形成溝部8之平面部的路徑A流動;少數電流係沿平行於連接源極及汲極之方向的通道之溝部8之側面的路徑B及溝部8之底面的路徑C流動。因此,電流傾向於集中在短閘極長度裝置中之路徑A,咸信此係短閘極長度裝置中驅動性能較低的原因。
本發明的一個目標為改進具有溝結構之半導體裝置的驅動性能。
為解決上述問題,本發明使用下列機構:
(1)一種半導體裝置包括:一第一傳導性型半導體基底;一溝部,其設於該第一傳導性型半導體基底之上,並於閘極寬度方向具有一側面及一底面;一閘極電極,其經由閘極絕緣膜而形成於該溝部之內及平面部之頂面上;一第二傳導性型之源極區,其設於該閘極電極之一側;及一該第二傳導性型之汲極區,其設於該閘極電極之另一側,其中該源極區及該汲極區包括該閘極電極附近之其表面之至少一部分,所包含該部分係配置於較該表面之其他部分低的位置,該源極區及該汲極區並具有該表面之該部分的向下部中較深的擴散深度,該表面之該部分的向下部係配置於較該表面之其他部分的向下部低的位置;
(2)一種半導體裝置包括:一第一傳導性型半導體基底;一第二傳導性型之源極區及一該第二傳導性型之汲極區,其於該第一傳導性型半導體基底之表面附近彼此相離地配置;一平面部,其係平坦並設於該源極區與該汲極區之間以成為第一通道區;一具有固定深度之溝部,其連同該平面部配置並具有一側面及一底面做為第二通道區;一閘極絕緣膜,其係提供予該平面部之表面及該溝部之表面;及一閘極電極,其設於該閘極絕緣膜之上,其中該源極區與該汲極區經由該溝部而於其表面上包括面對另一側之一部分的一部分,該部分係配置於較該表面之其他部分低的位置,該源極區及該汲極區並經由該溝部而具有面對另一側之該部分的該部分中較該表面之其他部分深的擴散深度;及
(3)一種製造半導體裝置之方法,包括:準備一第一傳導性型半導體基底;從該半導體基底之表面移除將成為源極區之區域的一部分及將成為汲極區之區域的一部分,以形成一凹部;於將成為通道之區域中形成具有一側面及一底面之溝,以配置一平面部及一溝部;於該溝部之側面及底面上及於該平面部之表面上形成一閘極絕緣膜;於該閘極絕緣膜上形成一閘極電極;及形成第二傳導性型之該源極區及該第二傳導性型之該汲極區,以環繞該凹部將該閘極電極夾於其間。
依據本發明,至少在閘極電極附近之一部分,經由矽之局部氧化(LOCOS)法移除所形成之厚氧化物膜,上述半導體裝置之源極區及汲極區之表面的一部分可低於該表面的其他部分。由於致能相對於電晶體之溝部的閘極電極之較深位置的源極區及汲極區之形成,沿閘極寬度方向之凹部頂端之電流的濃度可因而降低,且電流可分散至凹部內部而沿深的路徑流動,此可增強半導體裝置之驅動性能。
以下將參照圖式描述本發明之實施例。
圖1A至1J為顯示製造依據本發明之第一實施例之半導體裝置之方法的處理序列流程之示意截面圖。
在圖1A中,在第一傳導性型半導體基底上,例如p型半導體基底1或因添加硼而具有介於20Ωcm至30Ωcm範圍之電阻率的雜質濃度之半導體基底,形成具有數百埃()厚度之例如熱氧化物膜之氧化物膜2。之後,形成例如數千埃厚度之氮化物膜3。請注意,本實施例之基底具有p型傳導性,但基底之傳導性與本發明之本質無關。如圖1B中所示,以抗蝕劑膜4在氮化物膜3之上實施定型,並以LOCOS法移除氮化物膜3以形成氧化物膜。本狀況之氮化物膜係用於在後續程序中以LOCOS法形成厚氧化物膜。之後,形成抗蝕劑膜5同時保持抗蝕劑膜4,並添加雜質以於通道切割區中形成低濃度擴散層。例如,磷係較佳地以1×1011 atoms/cm2 至1×1013 atoms/cm2 之劑量而離子注入。在此狀況下,砷可用做雜質。
接著,如圖1C中所示,抗蝕劑膜4及5被移除,並經由LOCOS法形成LOCOS氧化物膜。在此狀況下,氧化物膜在1,000至1,200℃的溫度下達數小時,並經由熱氧化成長而具有500nm至1μm之厚度。此時,於通道切割區中形成低濃度擴散層6。隨後,如圖1D中所示,在氮化物膜3移除後,便以抗蝕劑膜7實施定型以移除LOCOS氧化物膜。除了抗蝕劑膜7外,氮化物或多晶矽之膜可用做定型之遮罩。在抗蝕劑膜7及氧化物膜2移除之後,接著獲得圖1E中所示之結構。該結構具有凹部而使得將成為源極區或汲極區之區的表面部分低於其他部分。隨後,如圖1F中所示,於第一傳導性型半導體基底中形成溝結構8,具有例如數百nm至數μm之深度。
如圖1G中所示,在形成數百至數千埃之厚度的例如熱氧化膜之閘極絕緣膜9之後,多晶矽閘極膜便沈積於閘極絕緣膜9上並較佳地具有100nm至500nm之厚度,及經由預先沈積或離子注入而導入雜質以降低電阻率而獲得閘極電極10。在此狀況下,傳導性可為第一傳導性型或第二傳導性型。此外,以抗蝕劑膜11定型閘極電極10,而提供圖1H中所示之結構。如上述,實質上決定將成為MOS電晶體之通道的區。圖1H僅顯示將成為溝部之通道的區,但將成為平面部之通道的區亦同步地經由於閘極電極10上定型而予形成。
隨後,如圖1I中所示,添加雜質而以自我校準的方式形成源極區及汲極區。在添加至源極區及汲極區的雜質中,例如砷係較佳地以1×1015 atoms/cm2 至1×1016 atoms/cm2 之劑量而離子注入。此外,將雜質導入至源極區及汲極區可在與相同晶片中不具有溝結構8之MOS電晶體之狀況的相同狀況下同步實施。經由上述程序,便組成具有溝結構8之MOS電晶體。如圖1J中所示,在800℃至1,000℃之溫度下實施熱處理達數小時,接著形成源極區12及汲極區13。在本實施例中,閘極電極10附近之源極區12及汲極區13具有一部分表面上之較低部。因此,用以形成源極區12及汲極區13之雜質亦較之前分佈於更深之部分,允許流經溝部之側面及底面的電流量增加。
將參照圖2A至2C更詳細地描述經由包括上述程序之方法而製造之具有溝結構之MOS電晶體的結構。
圖2A為本發明之第一實施例之MOS電晶體的平面圖,圖2B為沿圖2A之線A-A的截面圖,及圖2C為沿圖2A之線B-B的截面圖。
本發明之半導體裝置具有包括沿閘極寬度方向配置之複數個溝部8的閘極電極,及於構成除溝部外之一部分通道區的平面部上形成之閘極電極。圖2B為沿圖2A之線A-A的截面圖,顯示溝部電晶體18。圖2C為沿圖2A之線B-B的截面圖,顯示平面部電晶體19。圖2A顯示閘極絕緣膜9,其經配置而依循閘極電極10下之溝部的形狀。
圖2A顯示本發明之第一實施例,其中區14連續地及共同地存在於源極區12及汲極區13中,自此由LOCOS法製造之厚氧化物膜被移除以使源極區12及汲極區13之表面的至少一部分位於低於其他部分之閘極電極10的附近,並經配置而環繞溝部電晶體18之閘極電極10沿閘極長度方向的兩端。此外,在本實施例中,做為配線接點之溝部接點15及平面部接點16配置於閘極電極10附近之其表面上的較低部,其係位於源極區12及汲極區13中。
圖3為一平面圖,顯示依據本發明之第二實施例的半導體裝置。在圖3中,厚氧化物膜移除區14具有源極區12及汲極區13之表面上的至少一部分,其較其他部分低,並選擇性地於溝部電晶體18之閘極電極10沿閘極長度方向之延伸部分上形成。基此,對配線接點而言,溝部接點15或平面部接點16係配置於不同位置。例如,為了降低寄生阻抗,平面部接點16經配置而與閘極電極10之距離少於與溝部接點15之距離。亦在圖3中,閘極絕緣膜9經配置以便依循閘極電極10下之溝部的形狀。
1...半導體基底
2...氧化物膜
3...氮化物膜
4、5、7、11...抗蝕劑膜
6...低濃度擴散層
8...溝部
9...閘極絕緣膜
10...閘極電極
12...源極區
13...汲極區
14...厚氧化物膜移除區
15...溝部接點
16...平面部接點
17...井
18...溝部電晶體
19...平面部電晶體
A、B、C...路徑
在各圖式中:
圖1A至1J為顯示製造依據本發明之第一實施例之半導體裝置之方法的處理序列流程之示意截面圖;
圖2A為平面圖及圖2B和2C為截面圖,顯示具有依據本發明之第一實施例之溝結構的MOS電晶體之細節;
圖3為平面圖,顯示具有依據本發明之第二實施例之溝結構的MOS電晶體之細節;及
圖4A為透視圖及圖4B和4C為截面圖,各顯示具有習知技藝之溝結構的MOS電晶體,圖4D為示意圖,顯示流經具有相關技藝之溝結構的MOS電晶體之通道的電流路徑。
8...溝部
9...閘極絕緣膜
10...閘極電極
12...源極區
13...汲極區
14...厚氧化物膜移除區
15...溝部接點
16...平面部接點
18...溝部電晶體
19...平面部電晶體
A、B...路徑

Claims (7)

  1. 一種半導體裝置,包含:一第一傳導性型半導體基底;一溝部,其置於該第一傳導性型半導體基底之上,並於閘極寬度方向具有一側面及一底面;一閘極電極,其置於該溝部之內,並經由閘極絕緣膜而位於平面部之頂面上;一第二傳導性型之源極區,其置於該閘極電極之一側;及一該第二傳導性型之汲極區,其置於該閘極電極之另一側,其中該源極區及該汲極區包含該閘極電極附近之其表面之至少一部分,該部分係配置於較該表面之其他部分低的位置,該源極區及該汲極區並具有該表面之該部分的向下部中較深的擴散深度,該表面之該部分的向下部係配置於較該表面之其他部分的向下部低的位置,其中該平面部之每一該源極區之該表面上之接點和該汲極區之該表面上之接點與該閘極電極之間之距離,較該溝部之每一該源極區之該表面上之接點和該汲極區之該表面上之接點與該閘極電極之間之距離短。
  2. 一種半導體裝置,包含:一第一傳導性型半導體基底;一第二傳導性型之源極區及一該第二傳導性型之汲極區,其於該第一傳導性型半導體基底之表面附近彼此相離 地配置;一平面部,其係平坦並置於該源極區與該汲極區之間以成為第一通道區;一具有固定深度之溝部,其連同該平面部配置並具有一側面及一底面做為第二通道區;一閘極絕緣膜,其係提供予該平面部之表面及該溝部之表面;及一閘極電極,其設於該閘極絕緣膜之上,其中該源極區與該汲極區經由該溝部而於其表面上包含面對另一側之一部分的一部分,該部分係配置於較該表面之其他部分低的位置,該源極區及該汲極區並經由該溝部而具有面對該另一側之該部分的該部分中較該表面之其他部分深的擴散深度,其中該平面部之每一該源極區之該表面上之接點和該汲極區之該表面上之接點與該閘極電極之間之距離,較該溝部之每一該源極區之該表面上之接點和該汲極區之該表面上之接點與該閘極電極之間之距離短。
  3. 如申請專利範圍第2項之半導體裝置,進一步包含一接點,用以於配置於較低位置之每一該源極區及該汲極區之該表面上佈線。
  4. 一種製造半導體裝置之方法,包含:準備一第一傳導性型半導體基底;從該半導體基底之表面移除將成為源極區之區域的一部分及將成為汲極區之區域的一部分,以形成一凹部; 於將成為通道之區域中形成具有一側面及一底面之溝,以配置一平面部及一溝部,其中該溝部沿著該表面與該凹部分隔;於該溝部之側面及底面上及於該平面部之表面上形成一閘極絕緣膜;於該閘極絕緣膜上形成一閘極電極;及形成第二傳導性型之該源極區及該第二傳導性型之該汲極區,以環繞該凹部將該閘極電極夾於其間。
  5. 如申請專利範圍第4項之製造半導體裝置之方法,其中從該半導體基底之表面移除將成為源極區之區域的一部分及將成為汲極區之區域的一部分以形成一凹部,係經由使用矽之局部氧化(LOCOS)法形成一厚氧化物膜並移除該厚氧化物膜而實施。
  6. 如申請專利範圍第4項之製造半導體裝置之方法,其中形成第二傳導性型之該源極區及該第二傳導性型之該汲極區,進一步包含在與將雜質導入於該相同半導體基底上形成之另一電晶體之源極區及汲極區之狀況相同的狀況下導入雜質。
  7. 如申請專利範圍第4項之製造半導體裝置之方法,其中形成第二傳導性型之該源極區及該第二傳導性型之該汲極區,進一步包含與將雜質導入於該相同半導體基底上形成之另一電晶體之源極區及汲極區同步地導入雜質。
TW097127794A 2007-07-27 2008-07-22 半導體裝置及其製造方法 TWI459472B (zh)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2007195492A JP5165954B2 (ja) 2007-07-27 2007-07-27 半導体装置

Publications (2)

Publication Number Publication Date
TW200924071A TW200924071A (en) 2009-06-01
TWI459472B true TWI459472B (zh) 2014-11-01

Family

ID=40294497

Family Applications (1)

Application Number Title Priority Date Filing Date
TW097127794A TWI459472B (zh) 2007-07-27 2008-07-22 半導體裝置及其製造方法

Country Status (5)

Country Link
US (2) US8716142B2 (zh)
JP (1) JP5165954B2 (zh)
KR (1) KR101520485B1 (zh)
CN (1) CN101355105B (zh)
TW (1) TWI459472B (zh)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP5738094B2 (ja) * 2010-09-14 2015-06-17 セイコーインスツル株式会社 半導体装置の製造方法
JP5881100B2 (ja) * 2011-12-22 2016-03-09 エスアイアイ・セミコンダクタ株式会社 半導体装置の製造方法
DE102015106688B4 (de) 2015-04-29 2020-03-12 Infineon Technologies Ag Schalter mit einem feldeffekttransistor, insbesondere in einer integrierten schaltung zur verwendung in systemen mit lasten
JP2018089845A (ja) * 2016-12-02 2018-06-14 大日本印刷株式会社 個体認証用半導体チップ、個体認証媒体及び個体認証方法

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH08264764A (ja) * 1995-03-22 1996-10-11 Toshiba Corp 半導体装置
JPH1065150A (ja) * 1996-08-14 1998-03-06 Yokogawa Electric Corp Dmos fet

Family Cites Families (25)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3405681B2 (ja) * 1997-07-31 2003-05-12 株式会社東芝 半導体装置
JP3461277B2 (ja) * 1998-01-23 2003-10-27 株式会社東芝 半導体装置及びその製造方法
US6066533A (en) * 1998-09-29 2000-05-23 Advanced Micro Devices, Inc. MOS transistor with dual metal gate structure
US6956263B1 (en) 1999-12-28 2005-10-18 Intel Corporation Field effect transistor structure with self-aligned raised source/drain extensions
US6531347B1 (en) * 2000-02-08 2003-03-11 Advanced Micro Devices, Inc. Method of making recessed source drains to reduce fringing capacitance
JP4780818B2 (ja) * 2000-03-03 2011-09-28 ルネサスエレクトロニクス株式会社 半導体装置の製造方法
JP3651802B2 (ja) * 2002-09-12 2005-05-25 株式会社東芝 半導体装置の製造方法
KR100521369B1 (ko) * 2002-12-18 2005-10-12 삼성전자주식회사 고속도 및 저전력 소모 반도체 소자 및 그 제조 방법
JP2005136150A (ja) * 2003-10-30 2005-05-26 Oki Electric Ind Co Ltd 半導体装置及びその製造方法
JP4837902B2 (ja) * 2004-06-24 2011-12-14 富士通セミコンダクター株式会社 半導体装置
JP5110776B2 (ja) * 2004-07-01 2012-12-26 セイコーインスツル株式会社 半導体装置の製造方法
JP2006019518A (ja) * 2004-07-01 2006-01-19 Seiko Instruments Inc 横型トレンチmosfet
US7102201B2 (en) * 2004-07-15 2006-09-05 International Business Machines Corporation Strained semiconductor device structures
JP4515305B2 (ja) * 2005-03-29 2010-07-28 富士通セミコンダクター株式会社 pチャネルMOSトランジスタおよびその製造方法、半導体集積回路装置の製造方法
JP4976658B2 (ja) * 2005-04-05 2012-07-18 セイコーインスツル株式会社 半導体装置の製造方法
US7569443B2 (en) * 2005-06-21 2009-08-04 Intel Corporation Complementary metal oxide semiconductor integrated circuit using raised source drain and replacement metal gate
KR100714307B1 (ko) * 2005-08-05 2007-05-02 삼성전자주식회사 활성영역 가장자리에 리세스영역을 갖는 반도체 장치 및 그형성방법
JP4410195B2 (ja) * 2006-01-06 2010-02-03 株式会社東芝 半導体装置及びその製造方法
DE102006015077B4 (de) * 2006-03-31 2010-12-23 Advanced Micro Devices, Inc., Sunnyvale Transistor mit abgesenkten Drain- und Source-Gebieten und Verfahren zur Herstellung desselben
US7410875B2 (en) * 2006-04-06 2008-08-12 United Microelectronics Corp. Semiconductor structure and fabrication thereof
US7719062B2 (en) * 2006-12-29 2010-05-18 Intel Corporation Tuned tensile stress low resistivity slot contact structure for n-type transistor performance enhancement
JP2008192985A (ja) * 2007-02-07 2008-08-21 Seiko Instruments Inc 半導体装置、及び半導体装置の製造方法
JP2009152394A (ja) * 2007-12-20 2009-07-09 Toshiba Corp 半導体装置及びその製造方法
JP5442951B2 (ja) * 2008-02-26 2014-03-19 セイコーインスツル株式会社 半導体装置の製造方法
JP4770885B2 (ja) * 2008-06-30 2011-09-14 ソニー株式会社 半導体装置

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH08264764A (ja) * 1995-03-22 1996-10-11 Toshiba Corp 半導体装置
JPH1065150A (ja) * 1996-08-14 1998-03-06 Yokogawa Electric Corp Dmos fet

Also Published As

Publication number Publication date
CN101355105B (zh) 2012-06-27
KR101520485B1 (ko) 2015-05-14
KR20090012159A (ko) 2009-02-02
CN101355105A (zh) 2009-01-28
JP5165954B2 (ja) 2013-03-21
US8716142B2 (en) 2014-05-06
TW200924071A (en) 2009-06-01
JP2009032905A (ja) 2009-02-12
US20140191313A1 (en) 2014-07-10
US9276065B2 (en) 2016-03-01
US20090026537A1 (en) 2009-01-29

Similar Documents

Publication Publication Date Title
JP5307973B2 (ja) 半導体装置
WO2012144271A1 (ja) 半導体装置およびその製造方法
TWI451526B (zh) 半導體元件及其製造方法
TWI515893B (zh) 垂直式功率金氧半場效電晶體與其形成方法
US8598026B2 (en) Semiconductor device and method of manufacturing the same
JP5567711B2 (ja) 半導体装置
TW200845391A (en) Semiconductor device and method of manufacturing the same
US9178055B2 (en) Semiconductor device
TWI459472B (zh) 半導體裝置及其製造方法
JP5616720B2 (ja) 半導体装置およびその製造方法
US8236648B2 (en) Trench MOS transistor and method of manufacturing the same
JP2014508409A (ja) 半導体素子及び関連する形成方法
CN112005349B (zh) 半导体装置及半导体装置的制造方法
JP5743246B2 (ja) 半導体装置及び関連する製造方法
JP2021007129A (ja) 半導体装置
JP2016526804A (ja) 複数の注入層をもつ高電圧電界効果トランジスタ
JP6243748B2 (ja) 半導体素子及びその製造方法
KR20230114160A (ko) 수직 컨택 구조를 갖는 반도체 소자 및 그의 제조방법
JP2006332232A (ja) 半導体装置およびその製造方法
JP2022073551A (ja) 半導体装置およびその製造方法
JP2010182820A (ja) 半導体装置およびその製造方法
JP2011199195A (ja) 半導体装置およびその製造方法

Legal Events

Date Code Title Description
MM4A Annulment or lapse of patent due to non-payment of fees