TWI395306B - Heat-dissipating modularized structure of a semiconductor package and method of forming the same - Google Patents
Heat-dissipating modularized structure of a semiconductor package and method of forming the same Download PDFInfo
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- TWI395306B TWI395306B TW097104496A TW97104496A TWI395306B TW I395306 B TWI395306 B TW I395306B TW 097104496 A TW097104496 A TW 097104496A TW 97104496 A TW97104496 A TW 97104496A TW I395306 B TWI395306 B TW I395306B
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/50—Tape automated bonding [TAB] connectors, i.e. film carriers; Manufacturing methods related thereto
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73253—Bump and layer connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/93—Batch processes
- H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
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Description
本發明係有關於一種散熱模組化結構及其製法,尤指一種半導體封裝件之散熱模組化結構及其製法。The invention relates to a heat dissipation modular structure and a manufacturing method thereof, in particular to a heat dissipation modular structure of a semiconductor package and a manufacturing method thereof.
目前運用軟質承載板作為封裝晶片載體以將晶片與軟性基板電性連接之習知技術中,其可大約分為捲帶承載封裝(Tape Carrier Package,TCP)以及覆晶薄膜(Chip on Film,COF)等技術,其中顯示器的驅動IC封裝製程,以TCP載板與COF軟板作為驅動IC的封裝承載體,是目前相關技術最大的應用。In the prior art, a flexible carrier board is used as a package wafer carrier to electrically connect a wafer to a flexible substrate, which can be roughly classified into a Tape Carrier Package (TCP) and a Chip on Film (COF). Technology, such as the driver IC packaging process of the display, with the TCP carrier board and the COF soft board as the package carrier of the driver IC, is the largest application of the related technology at present.
然而高積集化(Integration)的半導體晶片運作時將伴隨產生大量的熱量,如不及時將半導體晶片產生之熱量有效逸散,將嚴重縮短半導體晶片之性能及壽命。However, the integration of the semiconductor wafer operation will be accompanied by a large amount of heat, such as the heat generated by the semiconductor wafer is not effectively dissipated, which will seriously shorten the performance and life of the semiconductor wafer.
因此,為提高半導體封裝件之散熱效率,遂有於封裝件中增設散熱結構之構想應運而生。Therefore, in order to improve the heat dissipation efficiency of the semiconductor package, the concept of adding a heat dissipation structure to the package has emerged.
鑑此,如第1圖所示,即為美國專利US6,238,954所揭露一種整合有散熱件之覆晶薄膜半導體封裝結構,其主要係將一半導體晶片11接置於晶片承載件10上,且形成有封裝膠體(molding compound)12以包覆該半導體晶片11之二側,再將一體成型之散熱件(dissipation member)13貼附於該半導體晶片11之表面,藉以逸散半導體晶片11之熱量。In this regard, as shown in FIG. 1 , a flip-chip thin film semiconductor package structure incorporating a heat dissipating member is disclosed in US Pat. No. 6,238,954, which is mainly to attach a semiconductor wafer 11 to the wafer carrier 10, and A molding compound 12 is formed to cover both sides of the semiconductor wafer 11, and an integrally formed dissipating member 13 is attached to the surface of the semiconductor wafer 11 to dissipate heat of the semiconductor wafer 11. .
惟該種封裝結構中,散熱件之貼附方式受限於封裝結 構尺寸大小,因而限制其散熱能力。However, in this package structure, the way the heat sink is attached is limited by the package junction. The size of the structure limits its ability to dissipate heat.
另一美國專利US5,866,953係揭露一種具有散熱膠材之半導體封裝結構,如第2圖所示,其主要結構係以覆晶方式於晶片承載件20上先接置一半導體晶片21,且形成有底部填體(under-fill encapsulant)22填充於該半導體晶片21及晶片承載件20間,於該半導體晶片21之周圍形成有凹槽之阻障膠材(barrier glob top)23以封住及保護該半導體晶片21,再於該阻障膠材23之凹槽中置入一散熱膠材(heat-dissipating glob top)24,藉以逸散半導體晶片21之熱量。Another US Patent No. 5,866,953 discloses a semiconductor package structure having a heat-dissipating adhesive material. As shown in FIG. 2, the main structure is to first connect a semiconductor wafer 21 on the wafer carrier 20 in a flip chip manner, and form An under-fill encapsulant 22 is filled between the semiconductor wafer 21 and the wafer carrier 20, and a barrier glob top 23 is formed around the semiconductor wafer 21 to seal and The semiconductor wafer 21 is protected, and a heat-dissipating glob top 24 is placed in the recess of the barrier rubber 23 to dissipate the heat of the semiconductor wafer 21.
惟在前述封裝結構中,該散熱膠材24係接置於半導體晶片21之背面,其散熱效果仍受限於半導體晶片21之尺寸,無法有效大幅提昇散熱效率,且實施方式複雜。However, in the package structure, the heat dissipation adhesive 24 is attached to the back surface of the semiconductor wafer 21, and the heat dissipation effect is still limited by the size of the semiconductor wafer 21, and the heat dissipation efficiency cannot be effectively improved, and the implementation manner is complicated.
另請參閱第3圖,為日本專利JP11-251483中所揭露之另一種半導體封裝結構,主要係在半導體晶片31之背面貼附具有開口320之薄膜散熱片(thin heat sink)32,該開口320外露出該半導體晶片31背面,藉由該薄膜散熱片32及開口320以逸散該半導體晶片31所產生之熱量。Referring to FIG. 3, another semiconductor package structure disclosed in Japanese Patent No. 11-251483 is mainly provided with a thin heat sink 32 having an opening 320 on the back side of the semiconductor wafer 31, the opening 320. The back surface of the semiconductor wafer 31 is exposed, and the heat generated by the semiconductor wafer 31 is dissipated by the film heat sink 32 and the opening 320.
惟此種半導體封裝結構,散熱能力仍明顯受限於封裝尺寸大小,且半導體晶片31所產生的熱量並非直接自該半導體晶片31帶走,而係大部分以熱傳導之方式,間接透過封裝結構中之金屬強化件(metal stiffener)33而傳導逸散,其散熱效率明顯不佳。However, in such a semiconductor package structure, the heat dissipation capability is still significantly limited by the package size, and the heat generated by the semiconductor wafer 31 is not directly taken away from the semiconductor wafer 31, but is mostly indirectly transmitted through the package structure by heat conduction. The metal stiffener 33 is conductively dissipated, and its heat dissipation efficiency is obviously poor.
上述半導體封裝結構中所結合之散熱元件,其尺寸皆受限於本身封裝結構之尺寸大小,而對於應用於捲帶承載封裝或覆晶薄膜技術之半導體封裝結構而言,皆具有小尺寸、高功率之特性,往往會受限於封裝結構本身之散熱元件面積過小,而無法達到有效散熱之效果。The heat dissipating component combined in the above semiconductor package structure is limited in size by the size of the package structure itself, and is small in size and high in the semiconductor package structure applied to the tape carrier package or the flip chip technology. The characteristics of power are often limited by the fact that the heat dissipating component area of the package structure itself is too small to achieve effective heat dissipation.
因此,如何提出一種半導體封裝件之散熱模組化結構,以克服習知受限於封裝結構尺寸而導致散熱件面積過小、散熱不佳之問題實已成為目前業界亟待解決之課題。Therefore, how to propose a heat dissipation modular structure of a semiconductor package to overcome the conventional problem that the heat sink area is too small and the heat dissipation is poor due to the size of the package structure has become an urgent problem to be solved in the industry.
鑒於上述習知技術之缺失,本發明之一目的在於提供一種半導體封裝件之散熱模組化結構及其製法,以提升半導體封裝件之散熱效率。In view of the above-mentioned shortcomings of the prior art, it is an object of the present invention to provide a heat dissipation modular structure of a semiconductor package and a method of fabricating the same to improve heat dissipation efficiency of the semiconductor package.
本發明之另一目的在於提供一種半導體封裝件之散熱模組化結構及其製法,以增進半導體晶片效能。Another object of the present invention is to provide a heat dissipation modular structure of a semiconductor package and a method of fabricating the same to enhance the performance of the semiconductor wafer.
本發明之再一目的在於提供一種半導體封裝件之散熱模組化結構及其製法,以簡化製程並利於模組化。A further object of the present invention is to provide a heat dissipation modular structure of a semiconductor package and a method of manufacturing the same to simplify the process and facilitate modularization.
本發明之又一目的在於提供一種半導體封裝件之散熱模組化結構及其製法,可不限於封裝件之尺寸而加大散熱面積。Another object of the present invention is to provide a heat dissipation modular structure of a semiconductor package and a method of fabricating the same, which can be increased by not limited to the size of the package.
本發明之復一目的在於提供一種半導體封裝件之散熱模組化結構及其製法,可採用簡易方式組合封裝件及外部電子裝置,同時提升散熱效能。A further object of the present invention is to provide a heat dissipation modular structure of a semiconductor package and a manufacturing method thereof, which can combine a package and an external electronic device in a simple manner, and at the same time improve heat dissipation performance.
為達上述目的,本發明之半導體封裝件之散熱模組化結構,係包括:一外部電子裝置;至少一半導體封裝件, 該半導體封裝件包含有晶片承載件、接置於該晶片承載件上之半導體晶片、以及接置於該半導體晶片上之第一散熱件,該第一散熱件具有第一容置槽及環繞連接於該第一容置槽之第一結合部,該第一容置槽用以容裝該半導體晶片,且該半導體封裝件係藉由其晶片承載件而電性連接至該外部電子裝置;以及至少一第二散熱件,係組設於該半導體封裝件之第一散熱件上,該第二散熱件具有第二容置槽及環繞連接於該第二容置槽之第二結合部,該第二容置槽用以容裝該第一容置槽,該第二散熱件係藉由其第二結合部與該第一散熱件之第一結合部結合而組設於該半導體封裝件之第一散熱件上,其中該第二散熱件之尺寸係大於該第一散熱件之尺寸。To achieve the above objective, the heat dissipation modular structure of the semiconductor package of the present invention comprises: an external electronic device; at least one semiconductor package, The semiconductor package includes a wafer carrier, a semiconductor wafer attached to the wafer carrier, and a first heat sink attached to the semiconductor wafer, the first heat sink having a first receiving groove and a surrounding connection The first accommodating groove is configured to receive the semiconductor wafer, and the semiconductor package is electrically connected to the external electronic device by a wafer carrier thereof; The at least one second heat dissipating member is disposed on the first heat dissipating member of the semiconductor package, and the second heat dissipating member has a second receiving groove and a second joint portion connected to the second receiving groove. The second accommodating groove is configured to receive the first accommodating groove, and the second heat dissipating member is assembled in the semiconductor package by combining the second bonding portion with the first bonding portion of the first heat dissipating member The first heat dissipating member has a size larger than a size of the first heat dissipating member.
本發明復揭示一種半導體封裝件之散熱模組化結構,係包括:一外部電子裝置;至少一半導體封裝件,該半導體封裝件包含有晶片承載件、接置於該晶片承載件上之半導體晶片、以及接置於該半導體晶片上之第一散熱件,且該半導體封裝件係藉由其晶片承載件而電性連接至該外部電子裝置;以及至少一第二散熱件,係組設於該半導體封裝件之第一散熱件上,其中,該第二散熱件之尺寸係大於該第一散熱件之尺寸,且該第二散熱件係以一對多方式接置在該半導體封裝件之第一散熱件上。The present invention discloses a heat dissipation modular structure of a semiconductor package, comprising: an external electronic device; at least one semiconductor package, the semiconductor package comprising a wafer carrier and a semiconductor wafer attached to the wafer carrier And a first heat sink attached to the semiconductor wafer, and the semiconductor package is electrically connected to the external electronic device by a wafer carrier; and at least one second heat sink is disposed on the semiconductor heat sink a first heat sink of the semiconductor package, wherein the second heat sink is larger in size than the first heat sink, and the second heat sink is connected to the semiconductor package in a one-to-multiple manner On a heat sink.
本發明復揭示一種半導體封裝件之散熱模組化結構之製法,係包括:提供至少一包含有晶片承載件、接置於該晶片承載件上之半導體晶片、以及接置於該半導體晶片 上之第一散熱件的半導體封裝件,其中,該第一散熱件具有用以容裝該半導體晶片之第一容置槽及環繞連接於該第一容置槽之第一結合部;將該半導體封裝件藉由其晶片承載件而電性連接至一外部電子裝置上;將至少一第二散熱件組設於該半導體封裝件之第一散熱件,其中,該第二散熱件具有用以容裝該第一容置槽之第二容置槽及環繞連接於該第二容置槽之第二結合部,該第二散熱件藉由其第二結合部與該第一散熱件之第一結合部結合而組設於該半導體封裝件之第一散熱件上,其中該第二散熱件之尺寸係大於該第一散熱件之尺寸。俾透過模組化方式結合該半導體封裝件、第一散熱件、外部電子裝置及第二散熱件,以提升半導體封裝件之散熱效率。The invention discloses a method for fabricating a heat dissipation modular structure of a semiconductor package, comprising: providing at least one semiconductor wafer including a wafer carrier, attached to the wafer carrier, and being attached to the semiconductor wafer a semiconductor package of the first heat sink, wherein the first heat sink has a first receiving groove for receiving the semiconductor chip and a first joint surrounding the first receiving groove; The semiconductor package is electrically connected to an external electronic device by the chip carrier; the at least one second heat sink is disposed on the first heat sink of the semiconductor package, wherein the second heat sink has a second receiving groove for receiving the first receiving groove and a second connecting portion surrounding the second receiving groove, wherein the second heat sink is connected to the first heat sink by the second joint portion thereof A bonding portion is combined and disposed on the first heat dissipating member of the semiconductor package, wherein the second heat dissipating member has a size larger than a size of the first heat dissipating member. The semiconductor package, the first heat sink, the external electronic device and the second heat sink are combined in a modular manner to improve the heat dissipation efficiency of the semiconductor package.
該外部電子裝置係例如為一液晶顯示(LCD)面板;該半導體封裝件例如為捲帶承載封裝或覆晶薄膜半導體封裝件。The external electronic device is, for example, a liquid crystal display (LCD) panel; the semiconductor package is, for example, a tape carrier package or a flip chip semiconductor package.
該第一及第二散熱件可由散熱能力佳之金屬或合金製程,且該第一及第二散熱件可採用例如相對凹凸之嵌合結構方便組合,亦或於該第一及第二散熱件間加入一具散熱效果之散熱膠進行黏合;另該第二散熱件可結合至複數半導體封裝件之第一散熱件上而形成一強化散熱效能之散熱模組結構,且該第二散熱件之數量不限於單一個,可視實際空間限制而分割成複數個,當然該第二散熱件亦可一對一對應於接置在半導體封裝件之第一散熱件上,且該第二散熱件之尺寸係大於第一散熱件之尺寸,以提升散熱 效能。The first and second heat dissipating members may be made of a metal or alloy with good heat dissipation capability, and the first and second heat dissipating members may be conveniently combined by, for example, a fitting structure with respect to the concavities and convexities, or between the first and second heat dissipating members. Adding a heat-dissipating heat-dissipating adhesive for bonding; the second heat-dissipating member can be coupled to the first heat-dissipating member of the plurality of semiconductor packages to form a heat-dissipating module structure for enhancing heat dissipation performance, and the number of the second heat-dissipating members It is not limited to a single one, and may be divided into a plurality of parts according to the actual space limitation. Of course, the second heat dissipating member may also be correspondingly connected to the first heat dissipating member of the semiconductor package, and the size of the second heat dissipating member is Greater than the size of the first heat sink to enhance heat dissipation efficacy.
因此,本發明之半導體封裝件之散熱模組化結構及其製法,係提供至少一半導體封裝件,該半導體封裝件包含有晶片承載件、接置於該晶片承載件上之半導體晶片、以及接置於該半導體晶片上之第一散熱件,以將該半導體封裝件藉由其晶片承載件而電性連接至一外部電子裝置上,且將至少一第二散熱件組設至該半導體封裝件之第一散熱件上,其中該第二散熱件之尺寸係大於該第一散熱件之尺寸,俾透過模組化方式結合該半導體封裝件、第一散熱件、外部電子裝置及第二散熱件,以提升半導體封裝件之散熱效率,同時確保其散熱能力不會侷限於半導體封裝件之尺寸大小,進而增進半導體晶片效能。Therefore, the heat dissipation modular structure of the semiconductor package of the present invention and the method for manufacturing the same are provided, at least one semiconductor package comprising a wafer carrier, a semiconductor wafer attached to the wafer carrier, and a connection a first heat sink disposed on the semiconductor wafer to electrically connect the semiconductor package to an external electronic device by using the wafer carrier, and at least one second heat sink is disposed to the semiconductor package The first heat dissipating member has a size larger than a size of the first heat dissipating member, and is coupled to the semiconductor package, the first heat dissipating member, the external electronic device, and the second heat dissipating member through a modular manner In order to improve the heat dissipation efficiency of the semiconductor package, and to ensure that its heat dissipation capability is not limited to the size of the semiconductor package, thereby improving the performance of the semiconductor wafer.
再者,透過本發明之半導體封裝件之散熱模組化結構及其製法,將可使其散熱能力不會侷限於半導體封裝件之尺寸,而可透過該第二散熱件,以結合外部空間而加大散熱面積。Furthermore, the heat dissipation modular structure of the semiconductor package of the present invention and the method of manufacturing the same can reduce the heat dissipation capability of the semiconductor package without being limited to the size of the semiconductor package, and can be coupled to the external space through the second heat dissipation member. Increase the heat dissipation area.
此外,於該半導體封裝件之散熱模組化結構中,第二散熱件之尺寸大小可視整體散熱模組化結構之散熱需求而設定,並可在欲電性連接至該外部電子裝置之半導體封裝件中接置標準化之第一散熱件,如此即可將一個甚至多個具有不同晶片尺寸之半導體封裝件藉由該第一散熱件與第二散熱件結合,而不用因不同晶片大小而一一客製化,如此將可加大第一散熱件之共用性及相容性,以及降低半導體封裝件之生產成本及製程複雜度,俾以模組化生 產目的。另散熱模組化結構之散熱能力係於組合半導體封裝件與外部電子裝置後,才由加入之第二散熱件決定,如此可避免先在半導體封裝件上接置一尺寸大於該半導體封裝件之第二散熱件,所導致包裝及搬運不便及製程複雜化之問題。In addition, in the heat dissipation modular structure of the semiconductor package, the size of the second heat dissipation component may be set according to the heat dissipation requirement of the overall heat dissipation modular structure, and may be electrically connected to the semiconductor package of the external electronic device. The standard first heat sink is connected to the device, so that one or more semiconductor packages having different chip sizes can be combined by the first heat sink and the second heat sink without different wafer sizes. Customized, this will increase the sharing and compatibility of the first heat sink, and reduce the production cost and process complexity of the semiconductor package. Product purpose. The heat dissipation capability of the heat dissipation module structure is determined by the combination of the second heat sink after the combination of the semiconductor package and the external electronic device, so as to avoid first attaching a size larger than the semiconductor package on the semiconductor package. The second heat sink causes problems such as inconvenient packaging and handling and complicated process.
以下係藉由特定的具體實例說明本發明之實施方式,熟悉此技藝之人士可由本說明書所揭示之內容輕易地瞭解本發明之其他優點與功效。本發明亦可藉由其他不同的具體實施例加以施行或應用,本說明書中的各項細節亦可基於不同觀點與應用,在不悖離本發明之精神下進行各種修飾與變更。The embodiments of the present invention are described below by way of specific examples, and those skilled in the art can readily appreciate other advantages and functions of the present invention from the disclosure herein. The present invention may be embodied or applied in various other specific embodiments, and various modifications and changes can be made without departing from the spirit and scope of the invention.
請參閱第4A至4C圖,係為本發明半導體封裝件之散熱模組化結構及其製法之剖面示意圖。Please refer to FIGS. 4A-4C , which are schematic cross-sectional views showing a heat dissipation modular structure of a semiconductor package of the present invention and a manufacturing method thereof.
如第4A圖所示,係提供至少一半導體封裝件4,該半導體封裝件4係包括:一晶片承載件40;至少一半導體晶片41,係接置並電性連接該晶片承載件40;第一散熱件42,係接置於該半導體晶片41上且具有用以容裝該半導體晶片41之第一容置槽420及環繞連接於該第一容置槽420之第一結合部421。As shown in FIG. 4A, at least one semiconductor package 4 is provided, the semiconductor package 4 includes: a wafer carrier 40; at least one semiconductor wafer 41 is connected and electrically connected to the wafer carrier 40; A heat sink 42 is attached to the semiconductor wafer 41 and has a first receiving groove 420 for receiving the semiconductor wafer 41 and a first joint portion 421 surrounding the first receiving groove 420.
該半導體封裝件4之製法係提供一例如為軟板或膠片之晶片承載件40,其中該晶片承載件40表面係設有複數銲墊401,以供半導體晶片41以覆晶方式藉由銲錫凸塊44而電性連接至該晶片承載件40。該半導體晶片41 具有一主動面411及相對之非主動面412,該半導體晶片41係以其主動面411上之銲錫凸塊44而接置於該晶片承載件40,並電性連接至該晶片承載件40表面之銲墊401。The semiconductor package 4 is provided with a wafer carrier 40 such as a flexible board or a film, wherein the surface of the wafer carrier 40 is provided with a plurality of pads 401 for the semiconductor wafer 41 to be flip-chip soldered by solder bumps. Block 44 is electrically coupled to the wafer carrier 40. The semiconductor wafer 41 An active surface 411 and an opposite non-active surface 412 are attached to the wafer carrier 40 by solder bumps 44 on the active surface 411 thereof, and are electrically connected to the surface of the wafer carrier 40. Solder pad 401.
復可於該半導體晶片41以及該晶片承載件40間的間隙中則填入覆晶底部填膠(underfill)45,以抑制該半導體晶片41以及該晶片承載件40間的熱膨脹差並降低該銲錫凸塊44的應力。A gap-on-fill underfill 45 is filled in the gap between the semiconductor wafer 41 and the wafer carrier 40 to suppress a difference in thermal expansion between the semiconductor wafer 41 and the wafer carrier 40 and to reduce the solder. The stress of the bumps 44.
接著將第一散熱件42透過一導熱黏著層46而接置於該半導體晶片41之非主動面412上,其中,該第一散熱件42之材質為如銅或鋁之散熱能力佳之金屬或合金,且該第一散熱件42係設有第一結合部421。The first heat sink 42 is then placed on the inactive surface 412 of the semiconductor wafer 41 through a thermally conductive adhesive layer 46. The first heat sink 42 is made of a metal or alloy having a heat dissipation capability such as copper or aluminum. And the first heat sink 42 is provided with a first joint portion 421.
如第4B圖所示,將至少一該半導體封裝件4透過其例如為軟板或膠片之晶片承載件40而接置並電性連接至一外部電子裝置51上,該外部電子裝置51例如為液晶顯示面板。As shown in FIG. 4B, at least one of the semiconductor package 4 is connected and electrically connected to an external electronic device 51 through a wafer carrier 40 such as a flexible board or a film. The external electronic device 51 is, for example, LCD panel.
如第4C圖所示,提供至少一第二散熱件52,以將該第二散熱件52接置於該半導體封裝件4之第一散熱件42上。As shown in FIG. 4C, at least one second heat sink 52 is provided to connect the second heat sink 52 to the first heat sink 42 of the semiconductor package 4.
該第二散熱件52係為銅及鋁之金屬或其合金之其中一者,其具有用以容裝該第一容置槽420之第二容置槽520及環繞連接於該第二容置槽520之第二結合部521,該第二散熱件52藉由其第二結合部521與該第一散熱件42之第一結合部420結合而組設於該半導體封裝件4之第一散熱件42上,且該第二結合部521係相對於該第一 散熱件42之第一結合部421而設置,本實施例中,該第一散熱件42之第一結合部421與該第二散熱件52之第二結合部521係為相對之凹凸嵌合結構,以使該第二散熱件52組合至該半導體封裝件4之第一散熱件42上,亦或可於該第一散熱件42與第二散熱件52間設置一導熱膠(未圖示)以供相互黏合。The second heat dissipating member 52 is one of a metal of copper and aluminum or an alloy thereof, and has a second accommodating groove 520 for accommodating the first accommodating groove 420 and is connected to the second accommodating portion. The second heat sink 52 is coupled to the first joint portion 420 of the first heat sink 42 to form a first heat dissipation of the semiconductor package 4 by the second joint portion 521 of the slot 520. On the member 42, and the second joint portion 521 is opposite to the first In the embodiment, the first joint portion 421 of the first heat sink 42 and the second joint portion 521 of the second heat sink 52 are opposite concave and convex fitting structures. The second heat sink 52 is combined with the first heat sink 42 of the semiconductor package 4, or a thermal adhesive (not shown) may be disposed between the first heat sink 42 and the second heat sink 52. For bonding to each other.
另外,該第二散熱件52之尺寸係大於該第一散熱件42尺寸,故該第二散熱件52可設計結合一個或複數個第一散熱件42。In addition, the size of the second heat sink 52 is greater than the size of the first heat sink 42 , so the second heat sink 52 can be designed to combine one or a plurality of first heat sinks 42 .
復請配合參閱第5A及5B圖,係為本發明半導體封裝件之散熱模組化結構之平面示意圖,係包括有一外部電子裝置51;半導體封裝件4,該半導體封裝件4係藉由其晶片承載件40而電性連接至該外部電子裝置51;以及第二散熱件52,係組設於該半導體封裝件4之第一散熱件42上,其中該第二散熱件52之尺寸係大於該第一散熱件42之尺寸。Referring to FIGS. 5A and 5B, which are schematic plan views of a heat dissipation modular structure of a semiconductor package of the present invention, including an external electronic device 51; a semiconductor package 4, the semiconductor package 4 is formed by a wafer thereof The carrier 40 is electrically connected to the external electronic device 51; and the second heat sink 52 is disposed on the first heat sink 42 of the semiconductor package 4, wherein the second heat sink 52 is larger than the size The size of the first heat sink 42.
本實施例中該外部電子裝置51係例如為一液晶顯示面板,另提供複數組具第一散熱件42之半導體封裝件4(本實施例中設有4個半導體封裝件,但非以此為限),以供該些半導體封裝件4藉由例如為軟板或膠片之晶片承載件40而接置並電性連接至該外部電子裝置51,並將第二散熱件52組設於該半導體封裝件4之第一散熱件42上。In this embodiment, the external electronic device 51 is, for example, a liquid crystal display panel, and further provides a plurality of semiconductor packages 4 having a first heat sink 42 (in this embodiment, four semiconductor packages are provided, but not The semiconductor package 4 is connected and electrically connected to the external electronic device 51 by a wafer carrier 40 such as a flexible board or a film, and the second heat sink 52 is assembled to the semiconductor. The first heat sink 42 of the package 4 is on the cover.
該第二散熱件52可結合至複數半導體封裝件4之第 一散熱件42上而形成一強化散熱效能之散熱模組結構,且該第二散熱件52之數量不限於單一個,該第二散熱件52係可視實際空間配置而僅設單一個(如第5A圖所示)或設置複數個(如第5B圖所示),當然該第二散熱件52亦可一對一接置在半導體封裝件4之第一散熱件42上,且該第二散熱件52之尺寸係大於第一散熱件42之尺寸,以提升散熱效能。The second heat sink 52 can be coupled to the plurality of semiconductor packages 4 A heat dissipating module structure is formed on a heat dissipating member 42, and the number of the second heat dissipating members 52 is not limited to a single one. The second heat dissipating member 52 can be set to a single one according to the actual space configuration (eg, 5A is shown or a plurality of (as shown in FIG. 5B), of course, the second heat sink 52 can also be connected one-to-one to the first heat sink 42 of the semiconductor package 4, and the second heat sink The size of the member 52 is larger than the size of the first heat sink 42 to improve heat dissipation performance.
此外,該第二散熱件52之尺寸大小可視整體散熱模組化結構之散熱需求而設定,並可在欲電性連接至該外部電子裝置51之半導體封裝件4中接置標準化之第一散熱件42(不論各該半導體封裝件中之半導體晶片規格是否相同),如此即可將一個甚至多個具有不同晶片尺寸之半導體封裝件4藉由該第一散熱件42與第二散熱件52結合,而不用因不同晶片大小而一一客製化,藉以增加該第一散熱件42之共用性及相容性,以及降低半導體封裝件4之生產成本及製程複雜度,俾達模組化生產目的。In addition, the size of the second heat sink 52 can be set according to the heat dissipation requirement of the overall heat dissipation module structure, and the first heat dissipation can be connected to the semiconductor package 4 to be electrically connected to the external electronic device 51. The component 42 (whether or not the semiconductor wafer specifications in the semiconductor package are the same), so that one or more semiconductor packages 4 having different wafer sizes can be combined by the first heat sink 42 and the second heat sink 52 Instead of being customized for different wafer sizes, the sharing and compatibility of the first heat sink 42 is increased, and the production cost and process complexity of the semiconductor package 4 are reduced, and the modular production is achieved. purpose.
再者,於本發明中,散熱模組化結構之散熱能力係於組合半導體封裝件4與外部電子裝置51後,才由加入之第二散熱件52決定,如此可避免先在半導體封裝件4上接置一尺寸大於該半導體封裝件4之第二散熱件,所導致包裝及搬運不便及製程複雜化之問題。Furthermore, in the present invention, the heat dissipation capability of the heat dissipation modular structure is determined by the combination of the second heat sink 52 after the combination of the semiconductor package 4 and the external electronic device 51, so that the semiconductor package 4 can be avoided. The second heat sink having a size larger than that of the semiconductor package 4 is connected to the second heat sink, which causes inconvenience in packaging and handling, and complicated process.
因此,本發明之半導體封裝件之散熱模組化結構及其製法,係提供至少一半導體封裝件,該半導體封裝件包含有晶片承載件、接置於該晶片承載件上之半導體晶片、以 及接置於該半導體晶片上之第一散熱件,以將該半導體封裝件藉由其晶片承載件而電性連接至一外部電子裝置上,且將至少一第二散熱件組設至該半導體封裝件之第一散熱件上,其中該第二散熱件之尺寸係大於該第一散熱件之尺寸,俾透過模組化方式結合該半導體封裝件、第一散熱件、外部電子裝置及第二散熱件,以提升半導體封裝件之散熱效率,同時確保其散熱能力不會侷限於半導體封裝件之尺寸大小,進而增進半導體晶片效能。Therefore, the heat dissipation modular structure of the semiconductor package of the present invention and the method for manufacturing the same are provided, wherein the semiconductor package comprises a wafer carrier, a semiconductor wafer attached to the wafer carrier, And a first heat sink disposed on the semiconductor wafer to electrically connect the semiconductor package to an external electronic device by using the wafer carrier, and at least one second heat sink is disposed to the semiconductor a first heat sink of the package, wherein the second heat sink has a size larger than a size of the first heat sink, and is coupled to the semiconductor package, the first heat sink, the external electronic device, and the second through a modular manner The heat sink is used to improve the heat dissipation efficiency of the semiconductor package while ensuring that the heat dissipation capability is not limited to the size of the semiconductor package, thereby improving the performance of the semiconductor wafer.
另外,透過本發明之半導體封裝件之散熱模組化結構及其製法,將可使其散熱能力不會侷限於半導體封裝件之尺寸,而可結合外部裝置空間加大散熱面積。In addition, the heat dissipation modular structure and the manufacturing method thereof of the semiconductor package of the present invention can reduce the heat dissipation capability of the semiconductor package without being limited to the size of the semiconductor package, and can increase the heat dissipation area by combining the external device space.
再者,由於本發明係在半導體封裝件之第一散熱件上及第二散熱件上設置例如嵌合結構之第一接合部及第二接合部,如此將可方便使用者輕易將該第二散熱件組合至該半導體封裝件之第一散熱件上。Furthermore, since the present invention provides a first bonding portion and a second bonding portion, for example, a fitting structure on the first heat sink of the semiconductor package and the second heat sink, the user can easily use the second The heat sink is assembled to the first heat sink of the semiconductor package.
上述實施例僅例示性說明本發明之原理及其功效,而非用於限制本發明。任何熟習此項技藝之人士均可在不違背本發明之精神及範疇下,對上述實施例進行修飾與改變。因此,本發明之權利保護範圍,應如後述之申請專利範圍所列。The above-described embodiments are merely illustrative of the principles of the invention and its effects, and are not intended to limit the invention. Modifications and variations of the above-described embodiments can be made by those skilled in the art without departing from the spirit and scope of the invention. Therefore, the scope of protection of the present invention should be as set forth in the scope of the claims described below.
10,20,40‧‧‧晶片承載件10,20,40‧‧‧ wafer carrier
11,21,31,41‧‧‧半導體晶片11,21,31,41‧‧‧ semiconductor wafer
22‧‧‧底部填體22‧‧‧Bottom fill
23‧‧‧阻障膠材23‧‧‧Resistance adhesive
24‧‧‧散熱膠材24‧‧‧heating adhesive
32‧‧‧薄膜散熱片32‧‧‧film heat sink
320‧‧‧開口320‧‧‧ openings
33‧‧‧金屬強化件33‧‧‧Metal reinforcement
4‧‧‧半導體封裝件4‧‧‧Semiconductor package
401‧‧‧銲墊401‧‧‧ solder pads
411‧‧‧主動面411‧‧‧ active face
412‧‧‧非主動面412‧‧‧Inactive surface
42‧‧‧第一散熱件42‧‧‧First heat sink
420‧‧‧第一容置槽420‧‧‧First accommodating slot
421‧‧‧第一結合部421‧‧‧ First Joint Department
44‧‧‧銲錫凸塊44‧‧‧ solder bumps
45‧‧‧覆晶底部填膠45‧‧‧Fladding bottom filling
46‧‧‧導熱黏著層46‧‧‧ Thermal adhesive layer
51‧‧‧外部電子裝置51‧‧‧External electronic devices
52‧‧‧第二散熱件52‧‧‧second heat sink
520‧‧‧第二容置槽520‧‧‧Second accommodating slot
521‧‧‧第二結合部521‧‧‧Second junction
第1圖係為美國專利US6,258,954所揭露之整合有散熱件之半導體裝置剖面示意圖;第2圖係為美國專利US5,866,953所揭露之具有散熱 膠材之封裝半導體裝置剖面示意圖;第3圖係為日本專利JP11-251483所揭露之半導體裝置剖面示意圖;第4A至4C圖係為本發明之半導體封裝件之散熱模組化結構及其製法剖面示意圖;以及第5A及5B圖係為本發明之半導體封裝件之散熱模組化結構平面示意圖。Figure 1 is a schematic cross-sectional view of a semiconductor device incorporating a heat sink disclosed in U.S. Patent No. 6,258,954, the disclosure of which is incorporated herein by reference. FIG. 3 is a schematic cross-sectional view of a semiconductor device disclosed in Japanese Patent No. 11-221483; and FIGS. 4A to 4C are a heat dissipating modular structure of a semiconductor package of the present invention and a method for manufacturing the same FIG. 5A and FIG. 5B are schematic plan views showing the heat dissipation modular structure of the semiconductor package of the present invention.
4‧‧‧半導體封裝件4‧‧‧Semiconductor package
40‧‧‧晶片承載件40‧‧‧ wafer carrier
401‧‧‧銲墊401‧‧‧ solder pads
41‧‧‧半導體晶片41‧‧‧Semiconductor wafer
42‧‧‧第一散熱件42‧‧‧First heat sink
420‧‧‧第一容置槽420‧‧‧First accommodating slot
421‧‧‧第一結合部421‧‧‧ First Joint Department
44‧‧‧銲錫凸塊44‧‧‧ solder bumps
45‧‧‧覆晶底部填膠45‧‧‧Fladding bottom filling
51‧‧‧外部電子裝置51‧‧‧External electronic devices
52‧‧‧第二散熱件52‧‧‧second heat sink
520‧‧‧第二容置槽520‧‧‧Second accommodating slot
521‧‧‧第二結合部521‧‧‧Second junction
Claims (22)
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TWI224846B (en) * | 2003-08-12 | 2004-12-01 | Siliconware Precision Industries Co Ltd | Semiconductor package with heat dissipating structure |
TW200620710A (en) * | 2004-10-22 | 2006-06-16 | Koninkl Philips Electronics Nv | Light-emitting device with improved heatsinking |
TW200807668A (en) * | 2006-07-26 | 2008-02-01 | Chipmos Technologies Inc | Pluggable tape type IC package |
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TWI224846B (en) * | 2003-08-12 | 2004-12-01 | Siliconware Precision Industries Co Ltd | Semiconductor package with heat dissipating structure |
TW200620710A (en) * | 2004-10-22 | 2006-06-16 | Koninkl Philips Electronics Nv | Light-emitting device with improved heatsinking |
TW200807668A (en) * | 2006-07-26 | 2008-02-01 | Chipmos Technologies Inc | Pluggable tape type IC package |
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