TWI267855B - System and method for controlling the access and refresh of a memory - Google Patents

Abstract

The present invention provides a memory and memory control system wherein, except for one case noted below, the main memory gives priority to read or write operations over refresh operations. On the other hand, the cache memory give priority to the refresh operations over read or write operations. The exceptional case is when a memory read signal is received when the cache refresh is enabled and the data in the cache memory is valid. In the exceptional case, the refresh of the cache memory is delayed. During certain read operations the data in the particular memory block is also written to the cache and no write back from the cache is performed. This reduces the number of write back operations and it eliminates a delay due to the refresh operation.

Description

1267855', 17728pif.doc IX. Description of the invention: [Technical field to which the invention pertains] (4) ^ Ming is related to the memory system, especially the control circuit for the memory system. [Prior Art] Random access memory (dram) is a commonly used memory, = two, an important feature of RAM is that the data stored in DRAM ',,, week = 11 update, otherwise the data will I lost. External access requests are usually random. Therefore, external storage and update access requests may be generated at the same time. Access to the DRAM is delayed when some memory systems occur. Towards some gas: ^ variable potential ij prime' thus increases the complexity of (10) must also increase the frequency. Other memory systems are designed with cycle times, and binary access and updates can occur within the allowed cycle time. Such updates will not be disturbed by external access requests. Access S fetch = the time required to store in the memory (SRAMM ^ week will take a high-speed, static random access memory to take time to capture the memory and reduce the average memory of the i- Owe: The data of the worker is stored in the high-speed cache memory, because...&_ makes the amount of the information #j, = the percentage of the data, thus avoiding the completion of the access request = "zhongzhong body Must be accessed. The actual memory of the memory system, to remember the memory usage. $ depends on the fast 1268785-, 17728pif.doc The present invention focuses on a method and system for accessing DRAM memory, where the update cycle There is generally no delay in memory. [Invention] The present invention provides a memory and memory control system in which, in addition to the cases specifically noted below, the primary memory will be prioritized, fetched or written to Higher than the update operation. On the other hand, the cache = body will be better, the right to update operation, so that it is higher than the read or g human operation. The exception is when the memory read signal is received while fast Take the update of the memory Enable, and cache the data in the memory is valid. In this exception, the update of the cache memory is delayed. In the update operation: if the read request is correct - the discount 1 ^ in the cache In the memory, the data in the cache memory is invalid. In the read operation, the poor material in the memory block is also in the cache. After the read operation is completed, the special memory block is updated. In this case, 'there is no operation written back from the cache. This reduces the number of writeback operations, thus eliminating the delay caused by the update." [Embodiment] The following will describe and discuss this Preferred Embodiments of the Invention, and with reference to FIG. 3, although the present invention has been described as a preferred embodiment, it is not intended to limit the invention to any of the skilled artisans, and The following examples (4) illustrate preferred embodiments and illustrated embodiments of the present invention. In these figures, the size of the box does not represent the size of the natural reading. The reference numbers are shown in all figures 丨1267855- 17 728pif.doc-like components. Only those parts related to the explanation of the present invention are illustrated and described herein. It should be understood that in addition to the descriptions in the drawings and the description herein, some of the elements have some other conventional parts. Many of the conventional knives of the present embodiment, as well as many of the conventional operations performed by the present embodiments, are not illustrated and described herein, and such portions are known to those skilled in the art. Therefore, the following description is comprehensive and clear. The succinct terminology is used by those skilled in the art to teach how to make and use the method of the invention. In the following description, the symbol "~" is used to mean "to". For example, the signals RFSE1 to RFSEn represent the signals RFSE1 to RFSEn. The target record, block" is used here to refer to read and write operations. The block of the write operation is the memory block to which the data is written. The destination block of the read operation is a memory block from which the data material is read. BRIEF DESCRIPTION OF THE DRAWINGS Figure 1 is a diagram showing a general block diagram of four DRAM memory blocks of the first preferred embodiment of the present invention, M1, M2, M3 and Μη as shown in Fig. 1. The diagram should be understood as a memory that may have as many as many such memory blocks as traditional. The other early elementary update state detectors 1 1 〇, controller list 120, 120 (as indicated by the dashed box), the address buffer 13 〇 and the input/output drive 140 are shown in FIG. The controller unit ΐ2〇 (shown in detail in FIGS. 3, 4, 5 and 6) includes a main controller 121, an update controller 122, a cache memory 123 (details are shown in FIG. 7), and a multiplexer 124. , 125. The memory blocks M1, M2, M3 and Μη are given in detail in FIG. Figure 3 is a block diagram of the main control person 121. Figure 7 is a block 1267855 17728pif.doc of cache memory 123. The blocks M1 and Mn are updated in response to the update start signal rfss and the update address minus the RFA. The memory block rotates and updates the status signal. The RFSJEn/k block responds to the memory read control signals MRi~MRn and does the I. The memory block performs a write operation in response to the memory write control signals Mwl to MWn and the response memory rewrite control signals CWB1 to CWBn. • (4) The state detector (4) is a logic circuit that updates the information signal RFSE in response to any of the update status signals RFSE1 to RFSEn. When all update status messages are initiated, the update status detector 11 also initiates an update of the information signal RFSE. The main control 121 receives a number of inputs, including the read signal Ren or the write signal Wen. The main controller 121 generates a memory control signal including a rewrite address CWBRC, a memory read control signal MR1~MRn, a memory write control signal MW1~]VTWn, a memory rewrite control signal #CWB1~CWBn, and a fast The memory read control signal cr, the cache memory write control signal CW, the cache memory rewrite control signal CWB, the cache memory write hit signal (CWH), the cache memory hit signal CH, read control signal REN and write control signal WEN. The update controller 22 periodically generates the update control signal CRFS and the update address signal RFA in response to the clock signal CLK. The precise timing of these signals depends on the physical properties of the memory, which is a matter of traditional engineering. 1267855· ‘ 17728pif.doc The cacheback 123 (shown in detail in Figure 7) is updated in response to the update control signal CRFS and the update address signal RFA, and generates an update start signal RFSS. The cache memory 123 outputs the cache memory read data CD AT when the cache memory read control signal CR is activated. The cache memory 123 writes the round entry ID AT or the memory read data MD AT (read from the memory block) when the cache memory write control signal cw is activated. The multiplexer 124 outputs the input φ data IDAT when the write control signal WEN is activated, and outputs the memory read data MDAT when the write control signal WEN is disabled. The multiplexer 125 outputs the cache memory read data CD AT when the cache memory hit signal CH is activated, and outputs the memory read data MD Ατ when the cache memory hit signal is disabled. The address buffer 130 receives an external address signal £:^-ADD and a clock signal CLK. The address buffer 丨3〇 outputs the memory address (bank 汛唬BA to the main controller 121 and a row/column address signal ^^^ go to the controller 120. This row/column address signal scale ( :ADD will also •memory U3 and memory block (M1~Mn).—Day output to ^ The flowcharts in Figures 2A-1 to 2F-1 and 2A-2 to 2F-2 explain the system in different situations. The completed operation. Figures 2A-1 through 2F-2 illustrate some of the important actions that occur in the system and the conditions under which they occur. Figures 2A-1 and 2A-2 show both when the RFSS update signal is initiated and the main control The action that occurs when the device 121 receives the read signal Ren. Figure 2A also shows the action that occurs when the RFSS update signal is disabled and the main controller m receives the read signal Ren. Figure 2A-1 is a flow chart The form of 11 _7855· 17728pii Figure 2 Α 2 is a logical block diagram. The two figures show the same thing in different ways. 'Port 7 Figure 2B-1 and 2B-2 show when the RFSS update signal is activated and the main Controls the action that occurs when 121 is written to the signal Wen. Figure 2b also does not show 'RFSS update chaos is disabled and the main controller 121 receives the write The action that occurs when the signal is Wen. Figure 2B-1 is the form of the flowchart and Figure 2B-2 is the logical block diagram. The two diagrams show the same thing in different ways. Figure 2C shows when the CRFS update signal is activated And the action that occurs when the main controller κι receives the read signal Ren. Figure 2c also shows the action that occurs when the CRFS update signal is disabled and the main controller 121 receives the read signal Ren. Figure 2D shows The action that occurs when the main controller 121 receives the write signal Wen and the C RF S cache memory update signal is activated or disabled. The operation shown in Figures 2A through 2F will be described in detail below. 1 and 2A-2: Both figures explain what happens when a Ren signal (read signal) is received. More precisely, the two figures show the same thing; due to the complexity of the operation, To ensure clarity, the information is expressed in two different ways. The two figures describe the actions that took place. The actual circuit that completes the operations in these two figures is shown in Figure 3 to Figure. What happens after receiving the Ren signal The specific operation depends on several factors. (1) RFSS State number, (2) whether the requested data in the cache memory 12

Whether the data in the I26H body and (3) the cache memory is valid data. From the 1st, the square tearing indication receives the Ren signal. This particular operation that occurs when the Ren signal is received depends on whether the RJP% update signal is activated or disabled as indicated by block 902. In Figures 2A-2, the AND blocks 961 and 962 indicate this. When the Ren signal is received and the RFSS update is initiated, the operation also depends on whether the data φ of the requested memory block in the cache memory 123 is valid. This is indicated by block 907 in Figure 2A_1. This is indicated in Figures 2A-2 and blocks 963, 964, 966 and 967. If the data of the requested memory block in the cache memory 123 is valid, the main controller 121 controls the read operation of the cache memory 123 and the memory block is updated. This is indicated by block 905 in Figure 2A-1 and by the output of block 967 in Figure 2A-2. If the data of the requested memory block in the cache memory 123 is invalid data, the action taken depends on whether some of the other memory data in the memory memory indicated by block 906 is valid data. If the data of other memory blocks in the cache memory is valid, the operations indicated by blocks 908, 911, and 913 in Figure 2A-1 occur. The following are some of the operations listed to the right of the 966 block in Figure 2A-2: L The main controller 121 holds (8) updates to the redundant blocks associated with the cache memory 123 and (b) the requested memory blocks. The main controller 121 controls the update of other memory blocks. 2. The data in the cache memory 123 is written back to the memory block to match the data in the cache memory. 13 1267855, 17728pif.doc 3. The read operation is completed from the requested memory block. 4. The requested data is written to the cache memory. 5. After the above operation, the matching memory block and the requested memory block are updated. If the test of the 906 block indicates that the data in the cache memory 123 is invalid, the operations indicated by blocks 909, 912, and 924 in Fig. 2Α-1 occur. The following are some of the operations listed at the output of block 968 in Figure 2Α-2: $1· The main controller 121 keeps the update and control of the requested memory block and updates other memory blocks. 2. The read operation is completed from the requested memory block and the requested memory block is written to the cache memory 123. τ' 2 3. After the above operation, the requested memory block is updated. If the test of block 902 indicates that the update was not initiated, the operations in Figure 2Α-1 indicated by blocks 904, 907, and 910 (indicated by blocks 960, 962, and 969 in Figure 2Α-2) are completed. As indicated by block 904, the use of different actions depends on whether the data of the requested memory block in the cache memory is valid. If the data of the requested memory block in the cache memory is valid, the main control 121 controls the read operation of the cache memory 123. If the data of the requested memory block in the cache memory is invalid, the main controller 121 controls the read operation of the requested memory block. The end result of the operations explained above is that the DRAM memory effectively circumvents other operations during the memory read operation. In addition, for example, the data in the cache memory is invalid, the read operation is completed in the requested memory block, and the requested memory block is simultaneously written to the cache 14 1467855;, 17728pif.doc . In this case there is no write back operation. Both j_B-l diagrams explain what happens when a Wen signal (write signal) is received. Rather, the two _ show ^ the same thing; due to the complexity of the operation, to ensure clarity, the information is expressed in two different ways. The two figures describe the actions that have taken place. The actual circuit for performing the operations in these two figures is shown in Figures 3 through 1〇. The specific operation that occurs after receiving the Wen apostrophe (write signal) depends on (1) the status of the RFSS signal, and (2) whether the data in the cache memory matches the target block of the write signal. As indicated by block 921, the process begins when a write signal is received. As shown in Figure 2B_1, this operation depends on whether the update signal RFSS is enabled or disabled as indicated by block 923. In Figure 2B-2, sum circuits 971 and 972 indicate this. When the RFSS update signal is initiated, the operations indicated by blocks 922, 925, 928, 931, and 932 occur. The occurrence of different operations depends on whether the #write request is for a memory block and the data from it is in the cache memory 123. This is indicated by block 922. Blocks 973, 974, and 975 in Figure 2B-2 illustrate the same decision process. If the write operation is for a memory block, the data from it is in the cache memory 123, as indicated by block 925, the main controller 121 controls the write operation to the cache memory 123, and correspondingly in the main memory The block is updated. After the write operation, the valid data bits in the cache memory are set. 15 1267855: 17728pif.doc

If the data in the cache memory is not the data recorded in the write operation, the operations indicated by blocks 928, 93i, and 932 occur. As indicated by Na, the main controller m strips the temple to be requested to update the memory block and controls the write operation of the memory block. The update operation is done in other hate blocks (except for the requested memory block). After the write operation, as indicated by ^931, the requested memory block is updated. A

If the data in the cache memory 123 is valid for other memory blocks, the data in the cache memory 123 is written back to the matching memory block and the data in the cache memory 123 is marked as invalid. Because this material is marked as invalid, it can accept other information. This is indicated by block 932. If the update is disabled when the write signal is received, the block

The operations indicated by 927, 929, and 930 occur. As indicated by block 924, operations 927 and 929 occur if the data in the cache memory is the data in the memory block specified by the write operation. If the material in the cache memory is the data in the memory block designated by the write operation, the main controller 121 controls the write operation of the requested memory block. The valid bit in the cache body 123 is turned off, so the memory controller shows that the data in the cache memory 123 is invalid. This is indicated by block 929. This is indicated in Figure 2Β-2 as indicated by block 978. If the data in the cache memory is not the data in the memory block specified by the write operation, the main controller 121 controls the write operation of the requested memory block, as shown in block 930 in FIG. 2Β_1 and the block in FIG. 2Β-2. 979 indicates 0. Therefore, as indicated above, the update operation does not interfere with the write operation. As for 16 1267855' 17728pifcioc, the write operation was not delayed by the update operation. 8 2'—Μ 2C refers to operations that depend on whether the CRFS update signal is activated or disabled when the Ren signal is received. Block 943 divides the operation into operations that occur when CRFS is initiated and when CRFS is disabled. If CRFS is enabled, the operation is further dependent on whether the data in the memory is valid data in the memory block specified by the read request, as indicated by block 942. If the data in the cache memory is the valid data in the ticker block specified by the read request, the operation indicated by block 945 occurs. That is, the main controller 121 holds (or delays) the update of the cache memory 123 and the read operation of the cache memory 123. After the read operation is completed, the cache entity 123 is updated, and the data in the cache memory 123 is written back to the memory block of ^. If the data in the cache memory is not a valid material in the memory block specified by the read request, the operation indicated by block 949 occurs. That is, the control Φ controller 121 controls the read operation of the requested memory block. If (10) is disabled, the operations indicated by the two squares (10), 947, and 948 are described. However, in order to avoid this, in this special case, it must be noted that there may be two types of valid data in the cache memory, which may be "read valid," or "write valid." The resource in the cache memory may be the read valid data in the memory block specified by the read request. However, considering the real P green memory block in the main memory, because the main memory block may be different from the data in the cache memory, the data in the cache memory can be 17

Can not be written effectively. One thing to note is that in some instances, when it comes to cache material in the cache, the term "valid data is used. In other instances, it will be used, 5 I will write the data effectively, and "Effective reading of data". In the case of using the term "pair: material", there is no description of "effectively writing data, or "effective reading of data", there is no need to distinguish between reading data and writing data. In the case illustrated in Figure 2C, the square The occurrence of the operation shown in 944, 947, and 948 depends on whether the data in the cache memory is a valid data written in the shirt specified by the read request. This decision is indicated by block 944. If the memory is cached The data in the memory is the write valid data in the memory block specified by the read request, as indicated by the operation indicated by block 947. That is, the main control state 121 controls the read operation of the cache memory 123. If the cache is hidden The data in the volume is not the write valid data in the memory block specified by the read request, as indicated by the operation indicated by block 948. That is, the main control is 121 to control the read operation of the requested memory block. Figures 2B and 2D both illustrate the operation that occurs when the system receives a write Λ唬Wen 守守. Figure 2D shows the operation that occurs when the operation CRFS update signal is activated or disabled. ^ Block 952 indicates that occurred The operation depends on the material in the memory of the cache (2) is not the data in the memory block specified by the writer. 'If the data in the cache memory 123 is the poor material in the blank block specified by the write request, The operation described in block 955 occurs. ~ The main controller 121 controls the write operation of the memory block specified for the write request. 18 1267855 · 17728pif.doc caches the "valid bit" in the memory block 123 because it is fast The data in the memory is no longer valid and is closed. After the writing operation is completed, the cache memory 123 is updated. If the data in the cache memory 123 is not the data in the same memory block specified by the write request, the block The operation described in 959 occurs. That is, the main controller 121 controls the write operation of the requested memory block. _ The general operation of the system will now be described. The description will refer to the unit and signal shown in Fig. 1. Update control signal The CRFS and the update address signal RFA are periodic apostrophes. In the particular preferred embodiment described herein, there are 2 字 word lines, and the pre-determined update time is 1 〇〇 microsecond. That is, the first The word line is 5 microseconds. The second word line is 5 microseconds, the third word line is 5 microseconds, etc., for a total of 100 microseconds. The update sequence is as follows: in response to update control signal CRFS and update address signal RFA, cache memory The body 123 updates the memory unit connected to the word line wi and starts the update start signal RFSS. In response to the update start signal RFSS and the update address signal ^^, the memory blocks M1 to Μη simultaneously update the record connected to the word line W1. In response to the update control signal CRFS and the update address signal RFA, the cache memory is updated in the memory unit of the word line W2, and the update start signal RFSS is activated. In response to the update start signal RFSS and the update address signal The RFA 'memory blocks M1 to Mn simultaneously update the memory cells connected to the word line W2, and so on. 19 1267855 I7728pif.doc The information in the fegu memory is updated when there is an accident: when the RFSS is started, the following action occurs: the data in the cache memory is valid, and the main controller 121 receives the read signal Ren or the write signal. Wen. The main controller 121 determines that the memory bank address signal BA is the same as the previous memory address signal BA_P and that the data in the cache memory 123 is valid. If the memory address signal BA is the same as the previous memory address signal φ ΒΑ Ρ 且 and the data in the cache memory 123 is valid, the cache memory information controller 200 activates the cache memory address hit signal CAH, cache. The memory reads or writes the hit signal CRH or C WH and the cache memory hits the signal CH. The cache memory controller 400 initiates a cache read/fetch or write control signal CR or CW, 1 and 2 strobe signals CASB, RASB, precharge control signal PRCB, and a read or write control. Signal REN or WEN. As a result, the cache memory is read or written and the memory block can be updated. Update when the data in the ® & memory is invalid: if the memory address signal BA is different from the previous memory address signal ba_P, the cache memory information controller 200 disables the cache memory address hit signal The CAH, cache memory reads or writes the hit signal CRH or CWH and the cache memory hits the signal CH. The cache memory controller 400 starts the cache memory read control signal CR, the cache memory rewrite control signal CWB, 1 or 2 selects the communication number CASB, RASB, the sense amplification control signal SENB, and the precharge control signal 20 1267855· 17728pif; doc number PRCB and read control signal REN and output rewrite address signal. CWBRC. In response to rewriting the address signal CWBRC, the memory block controller 300 activates one of the memory rewrite control signals CWB1 to CWBn. In response to the memory address signal BA, the memory block controller 300 activates one of the memory read control signals MR1 MRMRn or one of the memory write control signals *5 MW 1 ^ . φ By example A ·· The following is an example of an operation that occurs when the data in the cache memory is equal to the data in the memory block M2 and the target of the read signal Ren is equal to the memory block Μι. The memory block controller 300 activates the memory rewrite control signal memory read control signal MR1. The cache memory 123 performs a read operation in response to the cache memory read control signal CR. In response to the memory station write control δίΐ5 tiger CWB2, the memory block M2 keeps updating and writes to the cache memory to read the data CDAT. 1 In response to the memory read control signal MR1, the memory block M1 remains more new and performs a read operation, and the memory read data MDAT is output through the input/round drive to 140. The other memory blocks m3~Μη are updated in response to the update start signal RFSS. σ When the memory block M2 finishes rewriting or the cache memory 123 performs the next read operation, the memory block controller 300 disables the memory overwrite control signal CWB2 and controls the update of the memory block M2. After the rewriting process of the cache memory 123, the cache memory controller 400 starts the cache memory write control signal CW, and the cache memory 123 writes the memory read data 21 7728pif.doc MDAT § § 忆 忆 一个 M M M M M M M M M M M M M M M M M M M M M M 一个 一个 一个 一个 一个 一个 一个 一个 § § § § § § § § § § § § § § § § § § § And control the update of the memory block M1. The following is an example of an operation that occurs when the data in the cache memory is equal to the data in the memory block M2 and the target of the write signal Wen is equal to the memory block M1. The memory block M2 holds the update operation until the memory block m2 finishes rewriting or the cache memory 123 writes the input data IDAT in response to the next write signal. The other memory blocks M3 to Μη are updated. In response to the memory write _ control signal WR1, the memory block M1 maintains the update operation and performs the read operation. When one of the memory blocks M3 to Μn and the cache memory 123 are in the write operation, when the next write signal Wen or when the input data]; DAT is written to the cache memory, the memory block controller The 300 disable memory writes the control signal WR1 and controls the update of the memory block M1. After the rewriting of the cache memory _ 123, the cache memory controller 400 starts the cache memory write control signal CW and the cache memory 123 writes the input data]: DAT. When the RFSS is disabled, the memory block Ml~Μn will not be updated if the RFSS signal is disabled. If the rFSS signal is disabled and the main controller 121 receives the capture signal Ren or the write signal Wen, the memory block controller 300 will control the reading or writing of the memory blocks M1 to Μn. 22 1267855, n728pif.doc CR£gj skin start time ^ Zhao Feng and 丄 If the CRFS signal is activated, the cache memory 123 is updated. If the read signal scale is received when the CRFS signal is activated, and the data in the cache memory is valid, the following operation occurs: Cache § 忆 资讯 资讯 资讯 资讯 〇〇 〇〇 快 快 资讯 资讯 资讯 〇〇 〇〇 〇〇 China Signal CWH. The cache memory controller 4 starts the read control signal. The REN cache selects the read control signal cr and the cache memory rewrite control number CWB and the output rewrite address signal cWBRc. In response to the update control signal CRFS, the cache memory write hit signal C=H, and the read control signal REN, the cache memory 123 remains updated to perform a read operation in response to the cache memory read control signal CR. The read data CDAT in the memory 123 is finely outputted through the input/output driver and simultaneously written back to the memory block. After the cache memory 123 completes the read operation, the cache memory information control state 200 disables the cache memory write hit signal CWH and the cache memory controller 400 disables the read control signal REN, cache The memory reads the control signal CR and the cache memory rewrite control signal CWB. As a result, the memory 123 is updated. In addition to the special case, the main memory will be read or written to make it face the update operation. On the other hand, the cache memory will give the update operation higher than the read or write operation. The exception is when the memory signal is received, while the cache memory is activated, and the data in the memory is valid. In this exceptional case, the update of the cache memory is delayed. 23 1267855

i fast j a cache to record the basket diameter controller 400. Please note that the input and output of block 400 have REN and wen signals. As shown in Figure 6, the read and write signals Ren and Wen are the inputs to the instruction staging " REN and WEN are the output signals of the instruction register 41〇. REN and WEN are used as inputs to the circuit 4, 444 and 447 in the memory controller 4A. Displaying these connections makes the map too crowded. Thus, REN and WEN are shown as input to circuits 443, 444, and 447 such that REN and signals are present in the clock input and output signals of memory controller 400. The function performed by the controller 200 is to exchange the memory information control 200 to store information indicating which memory block matches the data in the cache memory 123. The cache memory information controller 2 also stores information indicating whether the data in the cache memory 23 is valid. When the data in the cache memory is the same as the data in the memory block having the read request, the cache memory information controller 200 activates the cache memory address hit signal CAH. When the data in the cache memory 123 is valid data, the cache memory information controller 200 activates the cache memory read hit signal CRH and the cache memory hit signal CH. When the data in the cache memory 123 is the data in the memory block 24 1267855· 17728pif.doc specified by the write request, the cache memory information controller 2 starts the cache memory address hit signal CAH. When the data in the cache memory 123 is valid, the cache memory information controller 2 (8) activates the cache memory write hit signal CWH and the cache memory hit signal CH. When the data MDAT and the input material ID AT in the memory block are written to the cache memory 123, the information in the cache memory information controller 2 is updated. The memory information controller receives a cache memory rewrite control signal CWB, a cache memory rewrite address signal cwBRC, a memory address signal BA, an update control signal CRFS, and a clock signal CLK. . The cache memory information controller outputs a rewrite memory address signal CBA and a second significant bit signal VW. The cache memory controller is reset in response to the reset signal RST. The memory controller 300: the memory controller 300 generates the memory read control signals MR1 to MRn, the memory write control signals MW1 to MWn, and the memory rewrite control signals CWB1 to CWBn. The above signal is generated when the read control signal REN or the write control signal WEN is activated. The above signals also depend on (or in response to) the clock signal CLK, the cache memory rewrite control signal CWB, the update start signal RFSS, and the update information signal RFSE. The cache memory controller 4 (10): the cache memory controller 400 starts the read control signal ren 25 1267855 ' 17728pii; a 〇 c or writes the control signal WEN when receiving the item number Ren or the write signal Wen. The cache memory controller 4 输出 outputs the first and second selection communication numbers CASB, RASB, the sense amplification control 7 tiger SENB, and the precharge control signal prcb in response to the clock signal CLK. When the read control signal REN or the write control signal WEN is activated, the defensive $fe body control is 400 output cache memory read control signal CR, cache δ 丨 丨 写入 写入 write control signal CW or fast Take the memory rewrite control signal CWB. These signals are in response to the update control signal crfs, the update start 7 tiger RFSS and the update tribute signal RFSE. A detailed description of the memory resource controller 200 (Fig. 4) is shown: Fig. 4 is a logic circuit diagram of the cache 5 own negative controller 200. The cache memory information controller 200 includes an address comparison circuit 21, 1 and 2 effective bit detection circuits 220, 230 and an output logic circuit 240. The address comparison circuit 210 includes an address register 211, an address comparator 212, and a logic circuit 213 including an inverter 214 and a AND gate 215. When the cache memory address hit signal CAH is disabled and the cache memory write control signal CW is enabled, the logic circuit 213 activates a scratchpad control signal CTL, and the cache memory address register 211 stores The current memory address signal BA and the stored memory address signal BA are output as the previous memory address signal BAJP. The address comparator 212 compares the previous memory address signal BAJP with the current memory address signal BA. If the previous memory address signal BA_P is the same as the current memory address signal BA, the address comparator 26 12戦: Pifdoc number ^ activates the cache memory address hit signal CAH. If these two messages are different, the cache memory address hit CAH will be disabled. Dotted lines L 220 and 230 represent elements forming a valid bit inspection circuit. These memories store information about the data stored in the cache memory 123. They are called 1 and 2 effective bit check circuits. The memory read data signal MDat of the block M1~Μn is used to store the memory to the cache memory 123. 1 Valid check circuit 220 • The storage of the memory indicates that the data of the cache memory 123 is valid. Or a logic circuit 223 of gate 226. When the control signal REN* is read, the cache 5 write control signal CW is activated, and the gate 224 is activated and the 1 update signal VBR is rotated. The reset control signal RES is activated when the cache memory address hit signal cAH |^ is disabled or the reset signal RST is activated. When the 1 update signal VBR is activated, the valid bit check circuit 1 valid bit check circuit includes an i valid bit register 221, a 1 selector 222, and a containing gate 224, inverters 225 and 220. The 1 update signal VBR is stored in the 1 valid bit register 221 in response to the clock signal CLK and the row/column address signal rc_ADD. That is, the logical 1 is stored in the 1 valid bit register 221 . When the reset control signal RES is activated, all data stored in the 1 valid only meta-register is reset. The selector selects the bit stored in the i-enabled bit register 221 and outputs a 1-bit bit signal VR. ~ When the input data IDAT is stored in the cache memory 123, the information valid in the cache memory 123 is stored in the 2 effective bit check. 27 I267855: fd 17728pif.doc Road 23〇2 Valid bit check The circuit 230 effective bit check circuit includes a 2-bit bit register 231, a 2 selector 232, a 2 logic circuit 233, and a change bit decision unit 238. The 2 logic circuit 233 includes: a multiplexer 234, Gates 235, 230 and non-gate 237. When the cache memory rewrite control signal CWB is enabled or disabled, the multi-work 234 outputs a rewrite address signal CWBRC or a row/column address signal RC_ADD, respectively. When the cache read control signal cR and the cache call rewrite control signal CWB are both activated, the gate 235 activates the logic signal A1. When the read control signal REN, the cache memory write hit signal CWH, and the update control signal CRFS are all activated, the AND gate 236 activates the logic signal A2. __ When the logic signals A1, A2 are disabled, the NAND gate 237 activates the 2 update signal VBW. When the 2 update signal VBW is activated, the 2 valid cells are temporarily stored as 231 to store the 2 update signal VBW in response to the clock signal CLK and the row/column address signal rC_ADD. Therefore, the bits of the 2 significant bit register 231 are all logic 1. • When the 2 update signal VBW is disabled, the 2 valid bit buffer 231 stores the 2 update signal VBW as a logical buffer in the 2 significant bit register 231 in response to the clock signal CLK and the rewrite address signal CWBRC. . When the reset signal RST is activated, the bits of the 2 significant bit register 231 are reset. If the bits of the 2 significant bit register are both logic 1, the data in the cache memory 123 is valid 'and if the bits of the 2 significant bit register are logical, the cache 123 The information in it is invalid. 2 28 I267855pifd〇c The valid bit το register 231 outputs all bits of the 2 significant bit register 231 as information bits SR1 to SRM. The selector 232 selects the bit stored in the 2 significant bit buffer and outputs a 2 significant bit signal VW. The change bit decision unit 238 receives the information signals SR1 to SRM and decides whether or not there is a change bit in the information signals SR1 to SRM. It outputs a change in the signal MDF. If there is a change bit, the change bit decision unit 238 will initiate the change bit signal MDF. Output logic circuit 24 includes and gates 241, 242 and or gate 243. The gate 241 outputs a cache memory read hit signal CRH in response to the i valid bit signal VR and the cache memory address hit signal caH. The gate 242 outputs a cache memory write hit signal CWH in response to the 2 valid bit signal VW and the cache memory address hit signal cah. Field introduction (Figure 5) ···憧揄捻憧揄捻# The detailed logic of the device 300 is shown in Figure 5. The memory block controller 3A includes a control logic circuit 310, a 1 decoding circuit 320, and a 2 decoding circuit 330 (shown in the figure as a dashed block). Control logic circuit 310 includes inverters 311-314, NAND gate 315, and gates 316, 317 and or gates 318, 319. When the update information signal RFSE or the cache memory rewrite control signal CWB is activated or the update start signal RFSS and the cache memory rewrite control signal cWB are simultaneously activated, the control logic circuit 31 starts a write selection signal WCTL. When the read control signal REN is activated and the cache memory hit signal CH is disabled, the control logic circuit 31 initiates a read select signal 29 1267 vertical RCtl. When any of the read control signal REN, the cache memory write hit signal, and the update control signal CRFS is disabled, reading the remote selection §fL RCTL is started. The decoding circuit 320 includes a decoder 32 and a gate 322 and a gate 323. The decoder 321 decodes the memory address signal ba and outputs a plurality of decoded signals BA1 to BAn. When a plurality of memory read control signals MR1 to MRn are selected, the selection signal RCTL and the plurality of 1 decoded signals BA1 to BAn are activated. When one of the memory read control signals MR1 to MRn is activated, one of the memory blocks M1 to Μn performs a read operation. The gate 323 outputs a plurality of memory write control signals MW1 MWMWn in response to the write control signal WEN, the write select signal WCTL, and the plurality of 1 decoded signals BA1 BCBAn. When the write control signal WEN, the write % selection signal WCTL, and the plurality of 1 decoded signals BA1 to BAn are activated, the AND gate 323 activates the selected plurality of memory write control signals MW1 MW MWn. When one of the memory write control signals MW1 to MWn is activated, one of the memory blocks M1 to Μn performs a write operation. The decoding circuit 330 includes a decoder 331 and a AND gate 332. The decoder 331 decodes the rewrite memory address signal CBA and outputs a plurality of 2 decoding signals CBA1 to CBAn. When the cache memory rewrite control signal CWB and the plurality of 2 decode signals CBA1 C CBAn are activated, the AND gate 332 activates the plurality of memory rewrite control signals CWB1 C CWBn. When one of the memory weight write control signals CWB1 to CWBn is activated, one of the memory blocks M1 to Μn is rewritten. 30 1267855' i7728pif.doc fe detailed description of the memory controller 400 (Fig. μ: Figure ό shows the detailed logic of the cache memory controller 400., cache § memory controller 400 includes an instruction temporary storage The controller 41, a control signal generator 420, a 1-control logic circuit 430 and a 2-control logic circuit 440. The control logic circuit 430 and the control logic circuit 440 are shown as dashed blocks in the figure. The instruction register 410 stores The signal Ren is read in response to the clock signal CLK and the read control signal is outputted. The instruction register 41 stores the write signal Wen in response to the clock signal CLK and outputs the write control signal WEN. The control signal generator 420 In response to the clock signal CLK, the 4 and 2 selection communication numbers CASB, RASB, the sense amplification control signal SENB, and the precharge control signal PRCB are transmitted. 1 The control logic circuit 430 includes a counter 431, a multiplexer 432, and a reverse 433. 450, and gates 434 to 436, or gates 437 and non-gates 438 to 439. 1 control logic circuit 430 outputs a cache memory rewrite control signal CWB and logic signal LGS in response to read control signals, write control signals, fast The memory address hits the signal CAH, changes the bit signal MDF, updates the control signal CRFS, and the information bits SR1 SSRM. 2 The control logic circuit 440 includes inverters 441, 442, and gates 443 to 446 and or gates 447 to 449. The control logic circuit 440 outputs the cached memory write control signal CW in response to the read or write control signal REN or WEN, the update start signal RFSS, and the update information signal RFSE.

2 control logic circuit 440 outputs the cache memory read control signal CR 31 I26__ = response update control signal CRFS, read control signal REN, cache record write or read hit signal CWH or CRH and logic message to LGS . ~

12?_^Detailed introduction (a_Di detailed cache memory is as shown in Fig. 7. The cache memory 123 includes a control signal generator 51A, a multiplexer 520, a memory cell array 530, a row decoder 54A, A word line driver 55A, a column decoder 560, an inductive amplifying circuit 570, a precharge circuit 58A, and a bus bar driver 590. The memory cell array 53A is a DRAM memory array that must be updated to maintain data. Whether the address selection signal CRFSS is activated or disabled. "Multiple: The device 520 outputs the update address signal RFA or the row address signal R_ADD. The row address signal R_ADD includes the row/column address signal rc_add. The low side bit (for example, if RC_ADD = 8 bit factory then ADD = 6 low side bit). When the cache memory 123 is updated, the control signal generator 51 bans the decoding control signal CASBc, so The column decoder 560 is disabled and the line rm 540 is enabled. In response to updating the address signal, the row decoder wo controls the word line driver 550 and starts the word lines W1 to W64. When the cache memory 123 is written Control signal generator 510 when entering or reading an operation The decoding control signal CASBc is started, and the column decoder 56 is also supported. The detailed logic of the device is shown in Fig. 8. The control signal generator 5i includes the detailed logic of the device 12 3267855. 17728pif.doc 510 A logic circuit (1) and a logic circuit 512, as shown by the dotted block in Fig. 8. When the 1-way communication number CASB is activated, the one of the cache memory write control signals CW is activated, and the memory is cached. The body read control signal CR is activated, and the logic circuit 511 activates the decode control signal cASBc. The logic circuit includes a radio frequency type flip-flop 531, a reverse gate 532, a gate 533 and a D-type forward and reverse. When the update control designation CRFS, the read control signal ren, the cache memory write hit signal CWH, and the clock signal CLK appear, the 2 logical channel 512 outputs the address selection signal CRFSS and the update start signal. RFSS. _ A detailed description of the example of the memory in the memory (Figure 2LL Figure 9 shows the details of the memory block Ml. The memory block includes some traditional components but with special logic. Please note that all memory blocks Ml ~Μη are the same. Memory block is The data block is composed of a control signal generator 610. The detailed logic of the control signal generator 610 is shown in Fig. 1 (). In addition to the control signal generator 610, the memory block] Νπ also includes multiplexers 620, 630, 710, memory cell array 640, row decoder 650, word line driver 660, column decoder 670, inductive amplification circuit 68A, precharge circuit 690, and bus bar driver 700. The control signal generator 610 updates the start signal in response to the 1 and 2 selection communication numbers CASB, RASB, the memory write control signal MW or the memory rewrite control signal 33 1267855' lT7j8pif.doc CWB memory read control signal MR1. RFSS, update information signal RFSE, inductive amplification control signal seNB and pre-charge control signal PRCB. The control signal generator 61 outputs the 1 and 2 decoding control signals CASB, the RASB, the update status signal rFSE1, the sense amplification control signal SENB1, and the precharge control signal pRCB1. Control signal generator 610 includes logic circuits 611-615 (shown in phantom blocks in the figure). Logic circuit 611 includes non-OR gates 721, 722 and inverting _ 732. In response to the memory write control signal MW1, the memory read control signal MR1, and the 1-select communication number CASB, the logic circuit 611 outputs a 1-decode control signal CASB1. When the 1-selection communication number CASB is activated and the memory read control signal MR1 and the memory write control signal MW1 are activated, the logic circuit 611 activates the 1-decode control signal CASBr. The control signal generator 610 outputs a precharge control signal PRCB1, an inductive amplification control signal SENB1, and a decode control signal RSAB1 through the logic circuits 612 to 615. The multiplexer 620 (Fig. 9) outputs one of the rewrite row address signal CWBR, the row address address signal R_ADD, and the update bit address signal RFA in response to the update status signal RFSE1 and the memory rewrite control signal CWB1. The multiplexer 620 operates as follows:

RFSE1 CWB1 output enable disable RFA disable start CWBR disable disable R ADD 34 1267 earn (10) address signal R_ADD is part of row/column address signal 110"^^ ώ rewrite row address signal CWBR is a rewrite bit A portion of the address signal CWBRC, the rewrite address signal CWBRC is connected to the counter 431 of the cache controller 400.

The multiplexer 630 outputs one of the column address signal C_ADD and the rewrite column address signal CWBC in response to the memory rewrite control signal CWB1. When the memory rewrite control signal CWB1 is activated, the rewrite column address signal CWBC is output, and when the memory rewrite control signal CWB1 is disabled, the column address signal C_ADD is output. The column address signal c_ADD is part of the row/column address signal RC_ADD low side bit.

The memory cell array 640 has substantially the same structure as the memory cell array 53A of the cache memory 123 of Fig. 7. When the write control signal WEN is activated or disabled, the multiplexer 71 outputs the input data IDAT or the cache memory read data CDAT, respectively. w is the response memory writer 峨 MW1, the bus driver 7 〇〇, and the multiplexer 71G outputs the memory cell array 64 (). In response to the record (four) signal intelligence network coffee · take the material MDAT. Taguchi U ghost Ml update day inch, control signal number control signal CASB1 and start 9 @成4 * 不月匕角午舲心 and start 2 decoding control signal RASB Buin = column decoder is disabled and the decoder (4) It is activated. In response to updating the address signal RFA, the line solves @4 i to start the word lines W1 to W64. Hummer 4 sub-line drive _ 660 so that when the memory block is doing a read operation or a write operation, the control signal generator 35 1267855 17728pif.doc = 10 start 1 decoding control signal casb RASB1, because the array is not decoded The control nickname is enabled, although the lack of both the solution and the row decoder 650 are enabled. To limit the present invention, any skilled person in the art can use the spirit of the present invention to make some branches and move the side trimmings, and thus the present invention (4) The attached towel shall be subject to the definition of patent scope. 4 BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a block diagram of a preferred embodiment of the present invention. Figure 2Α-1 and 2Α_2 illustrate the actions that occur during the read operation. The melons 1 and 2Β_2 illustrate the occurrence of the write operation. _ Figure and the example of the connection with the cache memory update Not all block diagrams of the main memory controller. Item 4 '5, 6 is a more detailed circuit of each unit shown in Figure 3. • ® 7 is a block diagram of the cache. Circuit Diagram Figure 8 is a control signal generator in the cache memory. Figure 9 is a block diagram of the memory block. Road map. Γ j ^ is the logic circuit diagram of the control signal generator in each memory block | [Main component symbol description] Current voltage drop 110: Update status detector 120: Controller unit 121 · Main controller as picture 36 I267855iM 〇c 122: update controller 123: cache memory 124, 125, 234, 432, 520, 620, 630, 710: multiplexer 130: address buffer 140: input/output driver M1~Μn: memory block CWBRC: Rewrite address signal MW1~MWn: Memory write control signal® MR1~MRn: Memory read control signal CWB1~CWBn: Memory weight write control signal CWB ··Cache memory rewrite control signal RFSE: Update information signal RFSE1~RFSEn: update status signal CR: cache memory read control signal CW: cache memory write control signal CWH: cache memory write hit signal ❿ CASB · · 1 select communication number RSAB : 2 select communication number SENB · · Inductive amplification control signal PRCB: pre-charge control signal REN: read control signal WEN: write control signal Ren: read signal Wen: write signal 37 I267855; d〇c CH: cache Memory hit signal RC-ADD: /column address signal RST: reset signal CLK: clock signal BA: memory address signal EX_ADD: address site signal RFA: update address signal CRFS: update control signal® MDAT: memory read capital唞CDAT: Cache Memory Read Data RFSS: Update Start Signal IDAT: Input Data 200: Cache Memory Information Controller 300: Memory Block Controller 310: Control Logic Circuit 400: Cache Memory Controller # 210: Address comparison circuit 211 ·• address register 212: address comparator 213: logic circuits 214, 225, 311 to 314, 433, 450, 441, 442, 523: inverters 215, 224, 235, 236 24 Bu 242, 316, 317, 322, 323, 332, 434~436, 443~446, 533: and gate 38 1267 obstruction pif.doc 220 : 1 effective bit check circuit 221 : 1 valid bit register 222 : 1 selector 223 : 1 logic circuit 226 , 243 , 318 , 319 , 437 , 447 ~ 449 : or gate 230 · 2 effective bit check circuit 231 : 2 valid bit register 232 : 2 selector • 233 : 2 logic circuit 237, 315, 438, 439, 521, 522 · · NOT or gate 238: change bit decision unit 240 · · lose Logic circuit 320: 1 decoding circuit 321: 1 decoder 330: 2 decoding circuit 331: 2 decoder • 410: instruction register 420, 510, 610: control signal generator 430: 1 control logic circuit 431: counter 440: 2 control logic circuit 511: 1 logic circuit 512: 2 logic circuit 530, 640: memory cell array 39 1267 vertical _ 531: RF type flip-flop 532: anti-gate 534 · D-type flip-flops 540, 650 Line decoders 550, 660: word line drivers 560, 670: column decoders 570, 680: inductive amplifier circuits 580, 690 · Precharge circuits ® 590, 700: bus bars 901 - 914, 921 - 932 , 960 ~ 969, 971 ~ 979, 941 ~ 949, 951 ~ 959 · ·

40

Claims (1)

1267855' 17728pif.doc X. Patent application scope: 1 · A kind of memory system, including · divided into blocks, which must be updated to maintain data, and stored by a cache memory, The main fabric material must be updated, and the memory has an indicator bit to refer to the dry (the current pay) mouth (3) to determine whether to update the Thunder, and the same as the information of the special information is valid information; , ^r Updating the main memory and the cache circuit to have an update start signal; the Miyagi Yasushi signal requests information from a memory block of the memory system; and the control circuit The more paid pq ^ is received, the above cache number is activated, a read signal is received, L, the body has a target block for storing the read signal, and the valid resource in the caution block in the cache memory _ starting from the new, _ the above main note { 咅 embossing (8) delay the above target block of the new target memory block and the other blocks, the standard block: the above, the cache memory does not store the read signal Go back to it and update Born not written from said cache memory and said data cache is not in addition to - the other valid data block in the block private purposes. For example, the memory system described in claim 1 of the patent scope, the upper middle circuit, when the update start signal is activated, a read signal 41 pif.doc and a vertical f: is received, the cache memory The upper block is not stored, and the target memory in the cache memory is used to implement (8) delay and update of the target block in the above cache memory=(b) delay writing of the data in the target coffee. (8) transferring the target memory block of the above read operation from the main memory to ±rst f ^(a)'(b)' (c)^(d^^^ ^ ^ the above block and the other blocks described above. = Affirmation of the memory system described in Item 1 of the patent, wherein the upper = work record 'when the update start signal is activated, -==; when the cache memory stores the target block of the read signal' All the cached memory reads the requested data and updates the memory system described in the first application of the scope of the patent application, in which the above is the factory road, ', when the above update start signal is disabled, one read Take the signal and upload the target block of the above read signal. And when the data in the memory is the valid data in the target block, a now reads the request information from the cache memory. (4): The memory system described in item 1 of the application scope , the upper received to the | 丨 circuit, the above update start signal is disabled, a read signal from the f cache memory does not store the target block of the read signal, from the main memory The above-mentioned request information is read. The control 1 applies the memory system described in item 2 of the scope of interest, wherein the upper guard circuit, when the update start signal is activated, a read signal 42 1267855 * 17728pif.doc jj - the above When the target block of the above-mentioned read signal is stored, the data of the read request in the memory is updated and all the above memory blocks are updated. The tenth, the missing item is the second item of the profit range. The memory (four) system, wherein the upper layer Γ, ', when the update start signal is disabled, a read signal ^ 'the above cache memory bribes the target block of the read signal, and When the data in the silk memory is the valid data in the target block, the request information is read from the cache memory. 8. A memory system comprising: a main memory, which must be updated to maintain data, and which is ^=cache memory, which must be updated to maintain data, and 2 main memory storage Selecting (4) the block, the cache memory has an effect indicating that the data of the cache memory is valid data, updating the circuit, and periodically updating the main memory; the input_output circuit, The response-writing command writes information to a target block in the above-mentioned system; and a control circuit, when (8) the main memory update circuit is activated, (9) is called a solid write command, and (e) When the data of the cache memory towel is the data in the target block of the write request, the data is written into the cache memory and the main memory is updated, and the control circuit is (a) The above main memory update circuit is activated, (b) a write command is received, and (c) the data in the cache memory is not in the memory block specified by the above write request 43 1267855 ' 17728pif.doc of It works, implements (A) keeps the update of the target block of the write instruction and controls the writing to the target memory block '(B) updates the memory block except the target memory block, and (c) writes to the target memory block After the operation, the target memory block is updated, (D) if the data in the cache memory is valid data in other memory blocks other than the target memory block, the data in the cache memory is written back to the other memory. Block and cache memory is disabled. ~A 9. The memory system of claim 8, wherein (a) the main 6 丨 思 思 思 思 updating circuit is not activated, (b) a write command is received, and (c) When the data in the cache memory is the data written in the target memory block, the control circuit is used to (A) control the write operation of the _ memory block (in addition to the valid bit of the cache memory) 10: The memory system according to claim 9, wherein (8) the main memory update circuit is not activated, (b) a write command is received, and (c) the cache is activated. The data in the memory is not the bedding date in the target memory block. ^ The above control circuit writes the data to the target memory block. ^, f 2:::: The memory system described in the first item of the patent scope , wherein the main money body and the silk memory include dram memory ^ a write household, a cache memory update circuit is activated, (b), ten, received 'and (e) above The data in the cache memory is effective when the above-mentioned data is written in the target memory block. , the above control 44 1267855 ' 】 772S ^ if. ci 〇 c write the above target memory block in the main memory, (8) the effective bit of the new body in the above-mentioned write - - nest MU ^ k body update circuit When the above-mentioned f' and (8) data in the above-mentioned cache memory is not valid data in the block, the data of the above-mentioned controlled entry request is written to the above-mentioned write request R as claimed in the patent scope 1 The memory system described in the item, wherein the circuit is manufactured, when (4) the silk record update is activated, (b), the write command is _, and (8) the data in the cache memory is ''' The control unit is configured to (A) write the person to the target memory in the main memory towel, and (B) disable the valid bit of the cache memory, (c) updating the cache memory after the above-mentioned write operation. The memory system of claim 1, wherein the control circuit includes when the memory read signal is received. At the same time, the cache memory update signal is activated and fast. The memory system described in claim 8 is effective when the data in the memory is valid, wherein the controller generally has priority in the main memory. Giving a read or write operation higher than the update operation, and in the cache memory, the priority is usually given to the update operation, which is higher than the read or write operation. 45 1267855 ' 17728pif.doc Once, when the memory signal is received and the above cache is the memory, the new signal is activated and the data in the memory is valid, the control is delayed. The above cache memory is updated. ^ The method of making a memory line, the memory system includes - ====;:r _ _ more master records 怏 memory - should 'heart system often receive memory write instructions to initialize the record = store _ and receive the memory read command to initialize the memory search - ΐΐΐ To: The memory usually gives priority to the read or write operation, so that the new Γ 上述 * The above-mentioned practice clock (four) f will give priority to the update Wood ^, to make it south of the read or write operation; and update the clock read signal is received and _ the above cache memory is more to remember == and record the face _f financial effect, delay the above fast method 18ί The order of the operating memory system described in item 17 of the Zhongshen 1/1 range/1 range is received, r is received, and the update of the above main memory refers to the target of the escaping of the escaping (4). The data in the memory is in the other memory block - the other data in the other memory block = = 1 = = main record =, and the target of the above read operation is stored 46 I26H then updates the above target block and the other memory blocks described above. Fang, Shen 专 full-time financial operation of the memory system: the read command was received, the above main record of the billion body = the above fetch memory is not the other memory block = ς力贝Material % 'read from the above main memory, the above-mentioned read operation is stored in the above-mentioned cache memory" ίΐίΐ block and the above other memory blocks, here is not from the above-mentioned fast number; = main memory Write back the operation memory method described in the 'Invalid Patent Range*, paragraph 17, item 17, wherein (A) when the read command is received, the update instruction of the above main memory is & the target memory block of the above-mentioned access instruction (4) not in the above cache memory cache memory is valid in other memory blocks 'AJi silk memory write _± the main memory of the above:: his memory block towel, read from the above main memory towel The above-mentioned requested memory step sub-stores the read-back operation in the cache memory, and then updates the target block and the other memory blocks, and (8) when the read command is received, the main memory Update refers to When the target memory block of the above-mentioned #彳日日 is not in the above-mentioned cache memory and the data of the upper 4 cache memory is not valid in other memory blocks, 'read from the above main memory The above-mentioned requested data, the sub-storage of the above-mentioned read operation is directed to the above-mentioned cache memory towel, and then more 47 1267 vertical _ · new target block and the above other memory blocks, (B) without write back operation, thus writing The number of back operations is minimized. 48