TWI228782B - Method of fabricating display panel - Google Patents
Method of fabricating display panel Download PDFInfo
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- TWI228782B TWI228782B TW093101413A TW93101413A TWI228782B TW I228782 B TWI228782 B TW I228782B TW 093101413 A TW093101413 A TW 093101413A TW 93101413 A TW93101413 A TW 93101413A TW I228782 B TWI228782 B TW I228782B
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- layer
- display panel
- contact hole
- flat
- protective layer
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- 238000004519 manufacturing process Methods 0.000 title claims description 23
- 238000000034 method Methods 0.000 claims abstract description 53
- 239000010409 thin film Substances 0.000 claims abstract description 22
- 239000000758 substrate Substances 0.000 claims abstract description 21
- 239000010410 layer Substances 0.000 claims description 97
- 239000011241 protective layer Substances 0.000 claims description 24
- 229920002120 photoresistant polymer Polymers 0.000 claims description 16
- 239000004973 liquid crystal related substance Substances 0.000 claims description 3
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims description 2
- 239000001301 oxygen Substances 0.000 claims description 2
- 229910052760 oxygen Inorganic materials 0.000 claims description 2
- 238000000151 deposition Methods 0.000 claims 1
- AMGQUBHHOARCQH-UHFFFAOYSA-N indium;oxotin Chemical compound [In].[Sn]=O AMGQUBHHOARCQH-UHFFFAOYSA-N 0.000 claims 1
- 238000000059 patterning Methods 0.000 claims 1
- YVTHLONGBIQYBO-UHFFFAOYSA-N zinc indium(3+) oxygen(2-) Chemical compound [O--].[Zn++].[In+3] YVTHLONGBIQYBO-UHFFFAOYSA-N 0.000 claims 1
- 238000005530 etching Methods 0.000 abstract description 5
- 238000002161 passivation Methods 0.000 abstract 2
- 238000005516 engineering process Methods 0.000 description 8
- 239000002184 metal Substances 0.000 description 4
- 230000003071 parasitic effect Effects 0.000 description 4
- 239000010408 film Substances 0.000 description 3
- 239000011159 matrix material Substances 0.000 description 3
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 2
- 239000013078 crystal Substances 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 239000002861 polymer material Substances 0.000 description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000005538 encapsulation Methods 0.000 description 1
- 238000003384 imaging method Methods 0.000 description 1
- 239000011229 interlayer Substances 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 229910052757 nitrogen Inorganic materials 0.000 description 1
- 229920000620 organic polymer Polymers 0.000 description 1
- 230000001681 protective effect Effects 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- 239000002689 soil Substances 0.000 description 1
- 239000004575 stone Substances 0.000 description 1
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 1
Classifications
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- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
- G02F1/136227—Through-hole connection of the pixel electrode to the active element through an insulation layer
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
- H01L27/1244—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits for preventing breakage, peeling or short circuiting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1248—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition or shape of the interlayer dielectric specially adapted to the circuit arrangement
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- Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- General Physics & Mathematics (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Nonlinear Science (AREA)
- Optics & Photonics (AREA)
- Crystallography & Structural Chemistry (AREA)
- Chemical & Material Sciences (AREA)
- Mathematical Physics (AREA)
- Devices For Indicating Variable Information By Combining Individual Elements (AREA)
- Electroluminescent Light Sources (AREA)
Abstract
Description
1228782 五、發明說明α) 【發明所屬之技術領域】 本發明係提供一種顯示面板的製作方法，尤指一種於一 顯示面板内製作接觸洞的方法。 【先前技術】 隨著科技的曰新月異，輕薄、省電、可攜帶式的智慧型 資訊產品已經充斥了我們的生活空間，而顯示器則在其 間扮演了相當重要的角色，不論是手機、個人數位助理 或是筆記型電腦，均需要顯示器作為人機溝通的介面。 近年來顯示器在高晝質、大畫面、低成本的需求下已有 很大進步’而在各式的顯不器中，缚膜電晶體（thin film transistor， TFT)型顯示器由於可用陣列方式主動 驅動顯示面板上的各像素電極，因此格外受到各界的重 視。 在現今的薄膜電晶體（thin film transistor， TFT)製程 中，電晶體與其上的金屬導線層間設有内層介電（interlayer dielectric, ILD) 層 ，用來 隔離並 保護液 晶顯示 器面板上的電路元件，且ILD層内設有接觸洞（contact h ο 1 e )，使該金屬導線層能填入該接觸洞而電連接至下方 之電晶體。因此’貢料訊號可措由該金屬導線層經由該 接觸洞内的金屬導線層傳送到電晶體的源/汲極，以進一1228782 V. Description of the invention α) [Technical field to which the invention belongs] The present invention provides a method for manufacturing a display panel, particularly a method for manufacturing a contact hole in a display panel. [Previous technology] With the rapid development of technology, thin, light, power-saving, and portable smart information products have flooded our living space, and displays have played a very important role in it, whether it ’s mobile phones, Personal digital assistants or laptops all need a display as a human-computer interface. In recent years, displays have made great progress under the requirements of high day quality, large screens, and low costs. And in all kinds of displays, thin film transistor (TFT) type displays are actively Each pixel electrode on the display panel is driven, so it is particularly valued by all walks of life. In the current thin film transistor (TFT) manufacturing process, an interlayer dielectric (ILD) layer is provided between the transistor and the metal wire layer thereon to isolate and protect circuit elements on the LCD panel. In addition, a contact hole (contact h ο 1 e) is provided in the ILD layer, so that the metal wire layer can fill the contact hole and be electrically connected to the transistor below. Therefore, the signal can be transmitted from the metal wire layer to the source / drain of the transistor through the metal wire layer in the contact hole.
1228782 五、發明說明（2) 步控制顯示器面板中各像素電極之運作。 請參考圖一，圖一為一習知顯示面板1 0之剖面示意圖。 如圖一所示，顯示面板1 0係包含有一基板1 2，其上設有 一包含有複數個薄膜電晶體之驅動電路1 4以及一介電層 1 6覆蓋於其上，為方便說明起見，圖一中僅以一薄膜電 晶體代表，然而事實上驅動電路1 4係包含有複數個相互 電連接之薄膜電晶體。此外，顯示面板1 0另包含有一平 坦層18形成於介電層16之上，平坦層18中並設有一接觸 洞2 2，以使形成於平坦層2 2上之導電層2 4能經由接觸洞 2 2電連接到基板1 2表面的電路元件1 4，以完成其間的電 連接。 一般而言，平坦層1 8大多係由高分子材料所構成，例如 可為一光阻層，因此僅需利用曝光顯影製程以及削光阻 技術即可形成接觸洞2 2，其功能在將顯示面板1 0的表面 平坦化，以利於後續顯示元件的製作。然而此結構雖然 製作方法簡便，但往往也會有寄生電容過高的現象以及 對下方之驅動電路1 4保護能力不佳的缺點，因此，目前 的薄膜電晶體顯示面板技術中，也提出了 一些改進的方 法，例如在介電層1 6與平坦層1 8間增設一保護層，以改 善其保護能力。 請參考圖二，圖二為另一習知顯示面板5 0之剖面示意1228782 V. Description of the invention (2) Step control the operation of each pixel electrode in the display panel. Please refer to FIG. 1, which is a schematic cross-sectional view of a conventional display panel 10. As shown in FIG. 1, the display panel 10 includes a substrate 12 on which a driving circuit 14 including a plurality of thin film transistors and a dielectric layer 16 are covered, for convenience of explanation. In FIG. 1, only a thin film transistor is used. However, the driving circuit 14 actually includes a plurality of thin film transistors which are electrically connected to each other. In addition, the display panel 10 further includes a flat layer 18 formed on the dielectric layer 16, and a contact hole 22 is provided in the flat layer 18 so that the conductive layer 24 formed on the flat layer 22 can pass through the contact. The holes 2 2 are electrically connected to the circuit elements 14 on the surface of the substrate 12 to complete the electrical connection therebetween. Generally speaking, the flat layer 18 is mostly composed of a polymer material, for example, it can be a photoresist layer. Therefore, the contact hole 22 can be formed by using only the exposure and development process and the photoresist technology. Its function is to display The surface of the panel 10 is flattened to facilitate subsequent fabrication of the display element. However, although the manufacturing method of this structure is simple, it often has the disadvantages of excessive parasitic capacitance and poor protection of the driving circuit 14 below. Therefore, some current thin-film transistor display panel technologies have also proposed some An improved method, for example, adding a protective layer between the dielectric layer 16 and the flat layer 18 to improve its protection ability. Please refer to FIG. 2, which is a schematic cross-sectional view of another conventional display panel 50.
1228782 五、發明說明（3) 圖。如圖二所示，顯示面板5 0之架構與前述之顯示面板 1 0相似，同樣具有一基板5 2、一驅動電路5 4以及一介電 層56覆蓋於其上，所不同之處在於新增一保護層58於介 電層5 6上，之後才形成平坦層6 2以及導電層6 8。此種結 構雖然可大幅強化對下方驅動電路的保護能力，並改善 寄生電容過高的現象，然而由於增加保護層5 6的關係，1228782 V. Description of the invention (3) Figure. As shown in FIG. 2, the structure of the display panel 50 is similar to the aforementioned display panel 10, and also has a substrate 5 2, a driving circuit 54, and a dielectric layer 56 covering it. The difference lies in the new A protective layer 58 is added on the dielectric layer 56 before the flat layer 62 and the conductive layer 68 are formed. Although this structure can greatly enhance the protection of the underlying drive circuit and improve the phenomenon of excessive parasitic capacitance, due to the increase of the protection layer 56,
在製程上也會相對繁複，相較於圖一之結構（顯示面板 1 0 )，顯示面板5 0必須要藉由一道額外的黃光暨蝕刻製程 來定義保護層5 6内之第一接觸洞6 4，之後方能利用上述 之曝光顯影製程或削光阻技術去形成於平坦層内的第二 接觸洞6 6，以使導電層6 8經由第一接觸洞6 4及第二接觸 洞66電連接至基板52表面之驅動電路54，因此，這種結 構雖具有功效上之優點，但卻會大幅提昇製程的複雜度 以及降低產品的生產速率。此外，在製作第一接觸洞6 4 與第二接觸洞6 6時，又存在有對位困難的問題，而易因 對位不準而造成後續電連結失敗，造成產品可靠度之下 降。 因此，要如何發展出一種新的顯示面板製作方法，以解 決習知技術中之問題，便成為當前之重要課題。The manufacturing process will also be relatively complicated. Compared to the structure of Figure 1 (display panel 10), the display panel 50 must use an additional yellow light and etching process to define the first contact hole in the protective layer 56. 64. After that, the second contact hole 6 6 formed in the flat layer can be formed by the above-mentioned exposure and development process or photoresist technology, so that the conductive layer 6 8 passes through the first contact hole 64 and the second contact hole 66. The driving circuit 54 is electrically connected to the surface of the substrate 52. Therefore, although this structure has advantages in efficiency, it will greatly increase the complexity of the process and reduce the production rate of the product. In addition, when making the first contact hole 64 and the second contact hole 66, there is also a problem of alignment difficulties, and subsequent electrical connection failures due to inaccurate alignment are likely to cause the reliability of the product to decrease. Therefore, how to develop a new display panel manufacturing method to solve the problems in the conventional technology has become an important issue at present.
【發明内容】 本發明之主要目的在於提供一種顯示面板的製作方法，[Summary] The main object of the present invention is to provide a method for manufacturing a display panel.
第11頁 1228782 五、發明說明（4) 尤指一種可減少一道黃光製程之接觸洞製作方法，以克 服習知技術之缺點。 在本 板的 薄膜 平坦 體之 下方 層内 選擇α ， 於該 分別 電晶 發明 製作 電晶 層， 上方 之保 分別 性移 而於 平坦 經由 體0 之最 方法 體， 並將 分別 護層 形成 除位 各第 層表 各第 佳實施 ，首先 接著於 平坦層 形成一 進行一 一通達 於各開 例中 提供 基板 圖案 開口 蝕刻 至薄 口周 一接觸洞上 面沉積一透 一接觸洞與 ，係 一基 上依 化， ，再 製程 膜電 圍之 方形 明導 各第 提供 板， 序形 以於 利用 ，以 晶體 部分 成一 電層 二接 一種有機發 基板表 成形成 平坦層 平坦層 於各開 之第一 平坦層 第二接 ，其中 觸洞電 面設 一保 内各 為罩 口下 接觸 ，以 觸洞 透明 連接 光顯 有至 護層 薄膜 幕層 方之 洞， 擴大 ，接 導電 至各 示面 少 與一 電晶 來對 保護 隨後 各開 著再 層係 薄膜 本發明之顯示面板製作方法係藉由圖案化之平坦層來作 為蝕刻罩幕，以於下方之保護層内形成接觸洞，因此在 可減少一道黃光製程的狀況下，有效提昇顯示面板之防 護能力以及降低寄生電容，且不至於因為多道黃光製程 而衍生出額外的對位問題。 【實施方式】Page 11 1228782 V. Description of the invention (4) Especially a method for making a contact hole that can reduce a yellow light process to overcome the shortcomings of the conventional technology. Select α in the lower layer of the flat body of the thin film of this board, and make the transistor layer in this invention. The upper part keeps the difference and moves to the flat surface. The best method is to form the body. The first layer and the second layer are best implemented. First, the formation of a flat layer is carried out one by one. In each example, a substrate pattern is provided. The opening is etched to a thin mouth. A contact hole is deposited on the contact hole on Monday. Then, the square-shaped transparent guides of the first and second providing plates of the film are formed in order to make use. The crystal part is an electric layer and then an organic hair substrate is formed to form a flat layer and a flat layer on each of the opened first flat layers. Two connections, in which the electrical surface of the contact hole is provided with a guarantee for each contact under the cover, and the transparent connection of the contact hole shows light to the square hole of the protective film curtain layer, which is enlarged and connected to each display surface and a transistor. The protection layer is then opened with a layer-by-layer film. The display panel manufacturing method of the present invention uses a patterned flat layer as an etch Screen to form a contact hole in the protective layer below, so under the condition that a yellow light process can be reduced, the display panel's protection ability and parasitic capacitance can be effectively improved, and no extra light is generated due to multiple yellow light processes. Alignment problem. [Embodiment]
第12頁 1228782 五、發明說明（5) 請參考圖三至圖八，圖三至圖八為本發明較佳實施 一顯示面板的製作方法示意圖。如圖三所示， ’j中 110包含有一基板112，且基板112表面具有—導雷面板 在本發明之較佳實施例中，顯示面板丨1()係為—=域’ 顯示面板，且基板1 12上設有一驅動電路丨18以及一彳 或 八發光 層1 1 6覆蓋於驅動電路上，而該導電區域則為 ’丨電 別 1 1 8之外露部分。為方便說明起見，圖三中僅以$電路 晶體代表驅動電路118，但事實上驅動電路u —薄膜電 複數個相互電連接之薄膜電晶體，以用來驅糸包含有 1 1 0進行影像顯示，而各薄膜電晶體係包含勒j、、員示面板 1 1 4，以及一源、汲極分別位於閘極丨丨4之閘極 藉由一接觸插塞1 1 5對外連接。 A侧’並分 保護層 塞11 5 含有厚 氣及氧 而平土j 厚度約 顯示元 ’以於 °126 之方法 由一甚§ 如圖四所示，接著於顯示面板丨丨〇上依序 122以及一平坦層124覆蓋於介電層116逝拉^ — 上’在本發明之較佳實施例中，保護居^ $觸指 5 0 0埃至5 0 0 0埃之氮石夕層或矽氧層，以加包 的抵抗能力’改善對下方電路元件的保1對水 層124則是由有機高分子材料構成之光'卩且”4 %力， 5 0 0埃至5 0 0 0埃，用來維持表面平坦，以其 之製作*如圖五所示，接著將平坦層丨24 續 坦層1 24内之各薄膜電晶體之上方分別步=*化 在本發明之較佳實施例中，將平坦層丨開 利用一曝光製程來定義平±旦層124之圖幸 案化 ^ 田茶，再藉Page 12 1228782 V. Description of the invention (5) Please refer to FIGS. 3 to 8, which are schematic diagrams of a method for manufacturing a display panel according to a preferred embodiment of the present invention. As shown in FIG. 3, 'j in 110 includes a substrate 112, and the surface of the substrate 112 has a lightning guide panel. In a preferred embodiment of the present invention, the display panel 1 () is a-= domain' display panel, and The substrate 1 12 is provided with a driving circuit 18 and one or eight light-emitting layers 1 1 6 covering the driving circuit, and the conductive area is an exposed portion of the electric circuit 1 1 8. For the convenience of explanation, the driving circuit 118 is represented by $ circuit crystal in FIG. 3, but in fact, the driving circuit u—thin-film electrical multiple thin-film transistors electrically connected to each other, is used to drive images containing 1 1 0 for imaging. It is shown that each thin film transistor system includes LEDs, display panels 1 1 4 and a gate with a source and a drain located at the gates 丨 4 and 4 are connected to each other through a contact plug 1 1 5. The side A 'is divided into protective layer plugs 11 5 containing thick air and oxygen and the flat soil j has a thickness of about the display element'. The method of ° 126 is as shown in Figure 4 and then sequentially on the display panel. 122 and a flat layer 124 cover the dielectric layer 116. In a preferred embodiment of the present invention, the protective layer ^ is made of a nitrogen stone layer of 500 to 500 angstroms or The silicon oxide layer has an increased resistance to encapsulation, which improves the protection of the circuit components below. The water layer 124 is made of organic polymer material and has a 4% force, 50 angstroms to 50 angstroms. Angstroms are used to keep the surface flat, and they are made * as shown in Fig. 5, and then the flat layers 丨 24 and the thin film transistors in the continuous layer 1 24 are respectively stepped on top of each thin film transistor in the preferred implementation of the present invention In the example, the flat layer is opened and an exposure process is used to define the image of the flat ± denier layer 124. Tiancha, then borrow
1228782 五、發明說明（6) 製程來去除接觸插塞1 1 5上方之部分平坦層1 2 4，以形成 開口 1 2 6。 如圖六所示，接著再進行一蝕刻製程，利用圖案化之平 坦層1 2 4為罩幕層，沿著開口 1 2 6向下蝕刻保護層1 2 2，以 於保護層1 2 2内形成一第一接觸洞1 2 8，並使基板1 1 2表面 之導電區域（接觸插塞1 1 5 )露出。值得注意的是在該蝕刻 製程中，將會藉由底切（undercut)的現象來加大第一接 觸洞1 2 8之開口大小，使第一接觸洞1 2 8頂部之開口大小 係大於上方開口 1 2 6底部之開口大小，以提昇後續電連接 製程之可靠度。 如圖七所示，接著將選擇性移除位於各開口 1 2 6周圍之部 分平坦層12 4，以擴大各開口 1 2 6，而於各第一接觸洞1 2 8 上方形成一第二接觸洞1 3 2。在本發明之較佳實施例中， 係藉由一削光阻（d e s c u m )製程來擴大開口 1 2 6，以形成第 二接觸洞1 3 2，然而本發明中選擇性移除平坦層1 2 4之方 法並不限於此，而可根據平坦層1 2 4之材質來採取其他適 當之製程，例如一濕餘刻製程。1228782 V. Description of the invention (6) Process to remove a part of the flat layer 1 2 4 above the contact plug 1 1 5 to form an opening 1 2 6. As shown in FIG. 6, an etching process is then performed. The patterned flat layer 1 2 4 is used as a mask layer, and the protective layer 1 2 2 is etched downward along the opening 1 2 6 so as to be within the protective layer 1 2 2. A first contact hole 1 2 8 is formed, and a conductive region (contact plug 1 1 5) on the surface of the substrate 1 12 is exposed. It is worth noting that in this etching process, the opening size of the first contact hole 1 2 8 will be increased by the undercut phenomenon, so that the opening size at the top of the first contact hole 1 2 8 is larger than the above. The size of the opening at the bottom of the opening 1 2 6 improves the reliability of subsequent electrical connection processes. As shown in FIG. 7, a part of the flat layer 12 4 located around each of the openings 1 2 6 is selectively removed to enlarge each of the openings 1 2 6, and a second contact is formed above each of the first contact holes 1 2 8. Hole 1 3 2. In a preferred embodiment of the present invention, the opening 1 2 6 is enlarged by a descum process to form a second contact hole 1 3 2. However, in the present invention, the planar layer 1 2 is selectively removed. The method of 4 is not limited to this, and other appropriate processes may be adopted according to the material of the flat layer 1 2 4, such as a wet-relief process.
第14頁 1228782 五、發明說明（7) 元件，以完成顯示面板1 1 0之製作。由於後續顯示元件之 製作應為熟習該項技藝者所熟知，且與本發明無直接之 關聯，故在此不予贅述。* 值得一提的是，在前述之較佳實施例中，雖以一有機發 光顯示面板為例來說明本發明之顯示面板製作方法，然 而本發明並不限於此，而可應用於其他類型之顯示面 板，例如一液晶顯示面板。此外，本發明所提供之顯示 面板製作方法並可應用於各式薄膜電晶體顯示面板中接 觸洞之製作，不僅可以被應用於主動式矩陣（a c t i v e m a t r i x )之顯示面板，亦可以被應用於被動式矩陣 (passive matrix)之顯示面板 。 與習知技術相較，本發明之顯示面板製作方法係利用圖 案化之平坦層為罩幕層來蝕刻下方之保護層，以於下方 之保護層内形成接觸洞，因此可在省略掉一道黃光製程 的狀況下將製程簡化，而有效提昇顯示面板之防護能力 以及降低寄生電容。此外，由於係利用圖案化之平坦層 為罩幕層來進行蝕刻製程，因此將不會因多道黃光製程 而發生所對位不準的問題，故可有效提昇顯示面板之可 靠度。 以上所述僅為本發明之較佳實施例，凡依本發明申請專 利範圍所作之均等變化與修飾，皆應屬本發明專利之涵Page 14 1228782 V. Description of the invention (7) Components to complete the production of the display panel 110. Since the production of subsequent display elements should be well known to those skilled in the art and has no direct connection with the present invention, it will not be repeated here. * It is worth mentioning that, in the aforementioned preferred embodiment, although an organic light-emitting display panel is taken as an example to illustrate the method for manufacturing the display panel of the present invention, the present invention is not limited to this, but can be applied to other types A display panel, such as a liquid crystal display panel. In addition, the display panel manufacturing method provided by the present invention can be applied to the production of contact holes in various thin-film transistor display panels, and can be applied not only to active matrix display panels, but also to passive matrix displays. (passive matrix) display panel. Compared with the conventional technology, the manufacturing method of the display panel of the present invention uses a patterned flat layer as a cover layer to etch the protective layer below to form a contact hole in the protective layer below. Therefore, a yellow layer can be omitted. Under the condition of the light manufacturing process, the manufacturing process is simplified, and the protection ability of the display panel is effectively improved and the parasitic capacitance is reduced. In addition, since the patterned flat layer is used as the mask layer for the etching process, the problem of misalignment due to multiple yellow light processes will not occur, so the reliability of the display panel can be effectively improved. The above description is only a preferred embodiment of the present invention, and any equivalent changes and modifications made in accordance with the scope of the patent application for the present invention shall all belong to the scope of the present invention patent.
第15頁 1228782 五、發明說明（8) 蓋範圍。 1I1B1Page 15 1228782 V. Description of the invention (8) Cover range. 1I1B1
04842626 τ-Η 1—π T—π L〇 L〇 CD CO04842626 τ-Η 1-π T-π L〇 L〇 CD CO
2 2 3 11 lx 1X 1228782 圖式簡單說明 圖式之簡單說明 圖一為習知一顯示面板的剖面示意圖。 圖二為習知一顯示面板的剖面示意圖。 圖三至圖八為本發明較佳實施例中一顯示面板的製作方 法示意圖。 圖式之符號說明2 2 3 11 lx 1X 1228782 Brief description of the drawings Brief description of the drawings Figure 1 is a schematic sectional view of a conventional display panel. FIG. 2 is a schematic cross-sectional view of a conventional display panel. FIG. 3 to FIG. 8 are schematic diagrams of a method for manufacturing a display panel according to a preferred embodiment of the present invention. Schematic symbol description
0 4 6 11 1X 11 顯 示 面 板 I 2 基 板 驅 動 電 路 I 6 介 電 層 平 坦 層 22 接 觸 洞 導 電 層 50 顯 示 面 板 基 板 54 驅 動 電 路 介 電 層 58 保 護 層 平 坦 層 64 第 一 接 觸 洞 第 二 接 觸 洞 68 導 電 層 顯 示 面 板 I 12 基 板 閘 極 I 15 接 觸 插 塞 介 電 層 I 18 薄 膜 電 晶 體 保 護 層 I 24 平 坦 層 第 接 觸 洞 132 第 — 接 觸 洞 導 電 層 第17頁0 4 6 11 1X 11 display panel I 2 substrate driving circuit I 6 dielectric layer flat layer 22 contact hole conductive layer 50 display panel substrate 54 driving circuit dielectric layer 58 protective layer flat layer 64 first contact hole second contact hole 68 Conductive layer display panel I 12 Substrate gate I 15 Contact plug dielectric layer I 18 Thin film transistor protective layer I 24 Flat layer No. contact hole 132 No. — Contact hole conductive layer page 17
Claims (1)
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| TW093101413A TWI228782B (en) | 2004-01-19 | 2004-01-19 | Method of fabricating display panel |
| US10/710,200 US20050158981A1 (en) | 2004-01-19 | 2004-06-25 | Method of fabricating display panel |
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| TW093101413A TWI228782B (en) | 2004-01-19 | 2004-01-19 | Method of fabricating display panel |
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| TW200525649A TW200525649A (en) | 2005-08-01 |
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| US9000353B2 (en) | 2010-06-22 | 2015-04-07 | President And Fellows Of Harvard College | Light absorption and filtering properties of vertically oriented semiconductor nano wires |
| US9054008B2 (en) | 2010-06-22 | 2015-06-09 | Zena Technologies, Inc. | Solar blind ultra violet (UV) detector and fabrication methods of the same |
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| US9406709B2 (en) | 2010-06-22 | 2016-08-02 | President And Fellows Of Harvard College | Methods for fabricating and using nanowires |
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| Publication number | Publication date |
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| US20050158981A1 (en) | 2005-07-21 |
| TW200525649A (en) | 2005-08-01 |
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