TW484228B - Non-volatile semiconductor memory device and the manufacturing method thereof - Google Patents

Abstract

The non-volatile semiconductor device according to the present invention can reduce the deviation of capacitance coupling for the layered gates and achieve the fineness for the memory cells, which is characterized in: forming the device separating insulation film, which is used to separate the device forming area formed on the semiconductor substrate; arranging the memory cells to form a memory cell array in array form, wherein the memory cells comprises: a first gate, which is formed by separating with the first gate insulation film; and, a second gate, which is on the first gate, and formed by separating with the second gate insulation film; the first gate of the memory cells are formed in a pattern with a partially overlapped manner from the device forming area to the device separating insulation film; and, allocating with the protective insulation film on the device separating insulation film adjacent to the first gate and sandwiched with the device forming area; furthermore, the non-volatile semiconductor memory device with the smaller embedded aspect ratio for the device separating insulation film, the smaller device separating space for the memory cells, and provided with excellent machining controllability, low cost, high density, which is to make the charge accumulating layer for the non-volatile semiconductor memory cell as a layered structure with at least two conductive layers, wherein the end surface position for the lowest conductive layer is consistent with the end position of the device separating area, and the upmost conductive layer has the same width as or wider than the bottom conductive layer. Because the first conductive layer is thinner, the embedded aspect ratio is lowered, and the second conductive layer is made with a necessary film thickness to make the capacitance with the control gate as the expected value. The upmost layer may be self-integrated with the device separating area and formed. Moreover, the isotropic etching can be used to widen the width of the upmost layer.

Description

484228 A7 B7 V. Description of the invention (BACKGROUND OF THE INVENTION The present invention relates to non-volatile semiconductor memory devices, and more particularly, to non-volatile semiconductor memory devices having semiconductor memory cells with a stacked structure for high density and high integration, and Its manufacturing method. Electrically rewriteable flash memory is widely used in non-volatile semiconductor memory devices (EEPROM) that are densified and high-capacity. Especially, it has a charge accumulation layer and a control gate layer. The memory cell of the Mos transistor structure of the product structure has been widely used. Figure 1 is a plan view of a NOR type EEPROM using this memory cell, and Figures 2A-2B are AA 'and BB of Figure 1, respectively. A cross-sectional view of the line. In the memory cell array region of the dream substrate 101, the element isolation insulating film 102 is buried, and the element formation region 10 that is continuous in the y direction is distinguished at a specific interval in the χ direction. In this way, the element separated substrate Then, a charge accumulation layer 105 is formed through the channel insulating film 104, and a control gate 108 is formed on the charge accumulation layer 105 via an inter-gate insulation film 107 to form a memory cell. The charge accumulation layer 105 is composed of το The insulating film 10 is separated from each other and is independent of each memory cell. The control gate 108 is continuously formed in the x direction and becomes a common word line for a plurality of memory cells. The control gate 108 and the charge accumulation layer 105 The side ends are aligned in the y direction to form a pattern of self-integration. This control gate 108 is self-integrated to form an η-type diffusion layer 6. The memory cell is covered with an interlayer insulating film 109, and is arranged thereon The bit line 11 in the y direction is rewritten. The data in this EEPROM is rewritten by adjusting the charge accumulation layer by applying a pseudo electric field between the substrate and the charge accumulation layer to allow a through current to flow between the charge accumulation layer and the substrate. The accumulative charge is carried out. The threshold of memory cells 値 -4- This paper size is applicable to Chinese National Standard (CNS) A4 (210 χ 297 mm) (Please read the precautions on the back before filling this page)

-n ϋ I l · —. ^ 1 n ϋ one OJI ϋ na ^ i ϋ I ϋ ϋ I Printed by the Intellectual Property Bureau Employee Consumer Cooperative of the Ministry of Economic Affairs 484228 A7 _______ Β7 V. Invention Description (2) (Please read the first Note: Please fill in this page again.) The more negative charge in the charge accumulation layer, the higher the charge becomes, and the more the positive charge becomes, the lower it becomes. Therefore, if electrons are injected into the charge accumulation layer, it will become a state of sadness (such as the writing state), and if electrons are pulled out of the charge accumulation layer, it will become a state of low threshold (such as the state of data deletion ). The most important parameter for the data rewriting of the memory cell is the ratio C1 / C2 of the capacitance c 1 between the charge accumulation layer 105 and the substrate 101, and the capacitance C2 between the control gate 108 and the charge accumulation layer 105. . When the substrate is set to a potential of 0 and a voltage Vcg is applied to the control gate 108, the voltage Vfg of the charge storage layer 105 becomes

Vfg = C2 · Vcg / (C1 + C2). Therefore, the coupling ratio K = C2 / (C1 + C2) = 1 / {1 + (C 1 + C 2)} determines the voltage applied to the channel insulating film 104. # Printed by the Consumer Cooperatives of the Ministry of Economic Affairs and Intellectual Property Bureau In order to generate channel current, a high electric field of several tens of MV / cm must be applied to the channel insulation film. Therefore, a high voltage of about Vfg = 10V must be applied between the charge accumulation layer and the substrate. Due to the combination of the charge accumulation layer and the control gate, the voltage Vcg = K · Vfg applied to the control gate must be a high voltage of about 20V. Even if the same voltage is applied to the control gate, if the coupling ratio K is different, the voltage applied to the channel insulation film is different, and the threshold value 値 of the memory cell becomes different. This becomes a problem because the threshold of the writing state of the memory cell is widely distributed. Therefore, it is necessary to try to set the coupling ratio K to be uniform 之. The dimensions of each part of the conventional memory cell structure are shown in Figure 3. Use it to find the capacitance ratio C 2 / C 1 as follows: C2 / C 1 = {Wa + 2. (d + T sti + Wing)} T ox / Wa · Tono Wing = (W sti-SL) / 2 -5- This paper size applies to China National Standard (CNS) A4 (210 X 297 mm) 484228 A7 B7 _ V. Description of the invention (3) ( Please read the precautions on the back before filling this page.) Capacitor C2 is determined by the relative area of charge storage layer 105 and control gate 108. Therefore, the unevenness of the film thickness of the charge accumulation layer, or the unevenness of the length (ie, the wing length) of the portion protruding outward from the element separation area of the charge accumulation layer 105, is the cause of the error in the capacitance C2. When the film thickness of the charge accumulation layer 105 is different in the height of the element formation region and the element separation region, there is a high possibility that the thickness will become uneven as shown in FIG. 3. The non-uniformity of the film thickness of the charge accumulation layer causes an error in the effective surface area of the charge accumulation layer. This is also the cause of the C 2 error. The wing length Wing is determined by the element separation width wsti and the cut width (ie, the slit width) SL of the charge accumulation layer. In order to quantify and reduce the size of the EEPROM, the cell size is miniaturized, and the component separation width Wsti or the gap width SL is often the minimum size when the memory cell is manufactured. In the previously shown memory cell, the gap width SL of the charge accumulation layer 105 is smaller than the element separation width Wsti, which is the smallest size. However, since the element separation width and the element formation area jointly determine the bit line pitch, in order to make the memory cell area smaller, it is desirable to make the element separation width Wsti as small as possible. The Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs has printed a method to achieve a wider gap than a small element with a wide range of component separation, which is used by the inventor (K. Shimizu et al., 97 IEDM) Residual sidewall technology. In this method, a mask material for gap processing is patterned on the charge accumulation layer, and an additional mask material is accumulated and left on the sidewall to obtain a narrow gap width. Figures 4A-4E show the steps of making such a memory cell. As shown in FIG. 4A, a gate material film 105a is stacked on a silicon substrate via a gate insulating film 104, and a masking material 201 is formed thereon, and the gate material film 105a is left -6. China National Standard (CNS) A4 specification (210 X 297 mm) '" 484228 A7 _ ^ B7 V. Description of the invention (4) In the component formation area, a pattern is formed. As shown in FIG. 4B, the substrate is etched to form a device separation trench using a masking material 201, and the device separation insulation film 102 is embedded therein. Next, as shown in FIG. 4C, the gate material film i05a is deposited again, and the masking material 200 for gap processing is patterned on the element separation insulating film 102 thereon. As shown in FIG. 4D, the masking material 203 is again thinly deposited and etched by anisotropic (anisotropic) dry etching to leave the masking material 203 only on the side wall of the masking material 202. In this way, preparation for clearance machining smaller than the minimum machining size is completed. Then, the gate insulating film i05b is etched by using the masking materials 202 and 203, so that the charge accumulation layer 105 formed by the laminated structure of the gate insulating films 105a and 105b is separated on the element isolation insulating film 102 to form a figure. type. Thereafter, as shown in FIG. 4E, a control gate 108 is formed via the inter-gate insulating film 107. The control gate 108 is separated from the charge accumulation layer 105 as described above, and is processed in a bit line direction. However, in the above method, the gate material film i05b is etched in the step of FIG. 4D, and after the gap processing to separate the charge accumulation layer is performed, the element separation insulating film 1 is removed in the step of removing the masking materials 202 and 203 by etching. The surface of 〇2 is etched, and as shown in FIG. 4E, a narrow trench 204 is formed in the gap separation portion of the charge storage layer 105. The groove 204 on the surface of this element separation insulating film 102 is formed not only in the cross section of FIG. 17E in which the control gate 108 is provided, but also continuously formed in the bit line direction (direction y in FIG. 14). Therefore, the trench 204 is extremely narrow. If the material of the inter-gate insulating film 107 and the control gate 108 is buried in the trench 204 and stacked, an etching residue will be generated along the trench 204 in the patterning step. This is the cause of the short circuit accident. In addition, the paper size of the components directly below the control gate 108 is subject to the Chinese National Standard (CNS) A4 (210 x 297 mm) 1 ♦ --------- Shang (please read the back first) (Notes on this page, please fill out this page) J.

-ϋ a · .— 1_1 ϋ n I Printed by the Consumers ’Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs 484228 A7 __ B7 V. Description of the invention (5) The film thickness of the insulating film 102 is reduced. 'The component is separated from the insulating film 1 〇 When the film thickness of 2 is made thin, the element separation function may be reduced. As described above, with the miniaturization of the components, the EEPROM with a memory cell composed of a charge accumulation layer and a control gate stack structure is caused by uneven thickness of the charge accumulation layer or a wide error in the processing of the gap between the charge accumulation layers. Misappropriation errors will reduce the data rewriting performance and become a problem. In order to separate the charge accumulation layer and perform gap processing on the element separation insulation film with a narrower width than the element separation width, the film thickness of the element separation insulation film will be reduced, and the element separation function will be deteriorated or the gate residue will cause a short circuit between gates An unexpected problem. Secondly, for different types of memory cells, explain the structure of the knowledge and its problems. Figures 5A and 5B show the separation of elements containing shallow grooves (ShaU〇

Isolation: STI) The i-th known example of a memory cell. Fig. 5a is a plan view, and Fig. 5B is its A-A, cross-sectional view. An element separation groove 302 is formed on the P-type chopping substrate or p # 301, and an insulation material for element separation such as silicon dioxide is buried in the groove. On the entire surface of the element region (channel region) 308 on the element separation substrate, a thin channel insulating film 304 is formed in which channel current can flow, and a charge accumulation layer 305 is formed thereon, and then a spacer is formed thereon. The inter-gate insulation film 306 forms a control gate 307. Further, it can be seen from FIG. 5 that a part 305 & under the charge accumulation layer 305 protrudes downward along the groove 302. Figs. 6A-6D are cross-sectional views of steps in the manufacturing steps of the STI cells shown in Figs. 5A and 5B. First, as shown in FIG. 6A, a dummy (dunmiy) is formed on the semiconductor substrate 301. -8-The size of this paper is Chinese National Standard (CNS) A4 (210 X 297 mm) nnn ϋ I (Please read the precautions on the back first (Fill in this page again) -J--Order -------- Printed by the Employees 'Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs Printed by the Employees' Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs Printed by 484228 A7 __ ____ B7 6-V. Description of the invention ( ) The insulating film 3 1 0 ′ is further stacked with a masking material 3 丨 1 of photoresist, etc., and is etched by light to align the masking material 311 of the element separation area, the dummy insulating film 31 and the side ends of the semiconductor substrate 301. The method is to remove the surname and form the groove 302. Secondly, the appropriate emulsifying conditions are used for thermal oxidation to oxidize the surface of the trench sidewall. At this time, the 'mask material also functions as a mask for oxidation, and the bird's peak formed on the dummy insulation film is formed to be thicker than the oxide film formed on the side wall of the trench. The corners are rounded. Then, the element isolation insulating film is deposited on the entire surface of the semiconductor substrate, and the element isolation insulating film 303 is filled in the groove 302. The element is separated by etch back of dry etching or surface polishing by chemical polishing (CMP). The upper surface of the insulating film 303 is flattened, and the upper surface of the masking material 311 is exposed (FIG. 6B). Next, the masking material 3 11 and the dummy insulating film 3 10 are etched and stripped by dry etching and wet etching of chemical treatment, and then the channel insulating film 304 and the charge accumulation layer 305 are deposited (FIG. 6C). Next, a pattern is formed by photo-etching, so that the charge accumulation layer 3007 is cut into a gap shape on the element separation area, and then the inter-gate insulation film 3 06 and the control gate 307 are stacked, and the gate processing is performed according to the pattern. Cell structure was completed (Figure 60). Next, the reason why the part 305a under the charge accumulation layer 305 is formed into a shape protruding downward along the groove 302, and the operation of the memory cell will be explained. The rewriting of the data of the memory cell having such a channel oxide film is performed according to the charge transfer between the charge storage layer 305 and the semiconductor substrate 301, and the amount of charge stored in the charge storage layer 305 is adjusted. Generally, at least one of charge injection and discharge is a channelization phenomenon using FN (Fowler_Nordheim) of the channel insulating film 304. That is, between the charge accumulation layer 305 and the semiconductor substrate 300, the size of this paper is applicable to the Chinese National Standard (CNS) A4 specification (210 X 297 mm) —j ---- Order --- ------ (Please read the precautions on the back before filling out this page); Install 7484228 A7 B7 V. Description of the invention (High electric field of more than tens m, from the semiconductor substrate to the electrical layer 305, or self-charge The accumulation layer 305 emits electrons to the semiconductor substrate. At this time, because the charge accumulation layer 305 is completely in a floating state, why the electricity in the charge accumulation layer 305 does not change without data modification. In order to accumulate this charge A high voltage is applied to the layer 3G5, and it is necessary to apply a voltage to the control room 307 to combine the control gate 3007 with the capacitance of the charge accumulation layer 305. However, if the voltage applied to the control gate 307 is high, the application voltage must be generated: (The various voltages of the booster circuit or the transistor that constitutes the output circuit of the output circuit are more important than the above, and there is a problem that the area of the element is increased. On the other hand, if the insulating film 3O4 is provided through the channel, The capacitance between the charge accumulation layer 305 and the semiconductor substrate 301 is C1, Table interval gate insulating film dove charge accumulating layer 305 and the control gate 307 capacitance C2, a voltage is applied to the insulating film 304 Vfg channels available control gate voltage Vcg of the following formula:

Vfg = C2 / (Cl + C2) That is, it can be seen that it is effective to increase the capacitance between the control gate 307 and the charge accumulation layer 305 via the gate insulating film 3006. Therefore, as long as the relative area of the control gate 307 and the charge accumulation layer 305 is increased, as described above, the shape of the charge accumulation layer 305 protruding from the element region to the element separation region can satisfy this requirement. The memory cell structure shown in this second conventional example has two major problems. The first problem is that it is very difficult to miniaturize the separation width of the device. In order to apply electricity 10- this paper size applies the Chinese National Standard (CNS) A4 specification (210 X 297 mm)

484228 V. Description of the invention () The charge accumulating layer 305 is cut into a gap shape on the element separation area, and it is necessary to perform a finer processing than the width of the element area or the element separation area. Therefore, the component separation size of Yuan Yi cell becomes The above-mentioned clearance processing is decided. Generally, although photoetching is used for gap processing, in order to perform gap processing on the element separation area, the gap pattern must be in a manner that does not overlap with the lower element area even if the gap pattern is misaligned in the photoetching step. , Forming a pattern configuration containing the involution space. Therefore, even in the case where the gap pattern itself can be made thinner than the element separation width, the element separation width becomes wider. That is, it is difficult to miniaturize the element separation width in the memory cell structure of the conventional example in which the charge accumulation layer is subjected to gap processing using photolithography. Furthermore, the second problem point is that it is very difficult to miniaturize the width of the device region. In the case of the memory cell structure shown in the conventional example, when the dummy insulating film is peeled off by wet etching, the groove-side end portion may be partially exposed. Therefore, as described above, a parasitic Mos capacitor is formed between the charge storage layers at the trench-side end via the channel insulating film. In the case where the smoothness of the parasitic MOS capacitor portion at the groove-side end is low, in the transistor characteristics of the memory cell, a paste curve characteristic occurs in the subthreshold region, which significantly deteriorates the cut-off characteristic. In addition, when a high voltage is applied to the control gate and the data is embedded according to the FN channelized electron injection, the gate electric field is concentrated on the parasitic MOS capacitor, causing the insulation damage of the channel insulation film. In order to suppress this problem, although the groove-side end must be made smoother, if a large amount of smooth oxidation is performed, it is necessary to form the bird's beak at the groove-side end. The width of the element area is significantly narrower than that when the groove is formed. . Therefore, in order to form the element area to the desired width, the smoothing oxygen on the pattern must be taken into account -11--III U ---- order --I--IIII. (Please read the precautions on the back before filling (This page) Printed by the Intellectual Property Bureau of the Ministry of Economic Affairs, Consumer Cooperatives. This paper is printed in accordance with the Chinese National Standard (CNS) A4 (210 X 297 mm) 484228 A7. 5. Description of the invention (:: Reduce Π points, widen the width. In addition, if the amount of the bird's beak is increased, the reason why the bird is large is that it is not necessary to accurately control the size of the fine element. The sti shown in the side of the brother 2 is accompanied by the connection, only 1 ~ 11. It is very difficult to miniaturize the separation width and the width of the device region. Figures 7A and 7B show one of the STI cell structures that solve the above problems, and are the first disclosed in Japanese Patent Laid-Open No. 丨 〇_ 〇! 7 9 4 8 The structure of the conventional example, Figure 7A is a plan view, Figure 7B is a B_B, and a sectional view. A trench 2 for element separation is formed on a P-type silicon substrate or a p-well 301, and an insulation material 303 for element separation is embedded in the trench. , Such as silicon dioxide. On the substrate of this component separation In the entire channel area, a thin channel insulation film 3 0 4 through which channel current can flow is formed, and a charge storage layer 312 is formed thereon. The side end portion of the charge storage layer 312 is consistent with the end portion of the element separation area. Element separation The insulating film 303 is in contact with the charge storage layer 3 12. In order to increase the capacitance between the charge storage layer 3 12 and the control gate 3 14, the side of the charge storage layer 3 12 is exposed through the inter-gate insulation film 3 13. Control gate 3 14. The control gate 14 and the charge accumulation layer 丨 2 are self-integrated in the vertical direction by aligning the position of the side ends in the vertical direction, forming an n-type diffusion layer 3 〇 between the gates. Figure 8A-8D 7A and 7B are cross-sectional views showing steps of manufacturing steps for obtaining the STI cell structure shown in Figs. 7A and 7B. On the semiconductor substrate 301, a conductive material 312 and a masking material that become a charge accumulation layer are stacked via a channel insulating film 304. 315. The trench 302 is formed by etching so that the masking material 315, the conductive material 312, the channel insulating film 304, and the side ends of the semiconductor substrate 301 in the element separation area are aligned to form the groove 302 (Figure-12-This paper applies to the standard Chinese country Standard (CNS) A4 (210 X 297 mm) II * I tL I Λ— J — — — — — — (Please read the notes on the back before filling this page) ---- Order --- I- ---- # · Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 484228 A7

Printed by the Consumers ’Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs 8A" Thermal oxidation using appropriate oxidation conditions, the surface of the trench sidewall is oxidized, and the insulating film for element separation 30 is stacked, and is etched back by dry etching. Or chemical polishing (CMp) for surface polishing to flatten the upper surface of the element separation insulating film 303 so that the upper surface of the masking material 3 15 is exposed (FIG. 8B). In this state, the element separation insulation is insulated The film 3 is etched back to expose a part of the side surface of the charge accumulation layer 3 12, and then the masking material 3 15 is peeled off (FIG. 8C). Next, the inter-gate insulating film 3 13 and the control gate 3 14 are stacked. The pattern is gated to complete the cell structure (Figure 8D). This STI cell structure shown in the third conventional example is formed by stacking the channel insulation film and the charge accumulation layer before the trench formation, and then performing the trench formation. It is different from the embedded STI cell structure shown in the i-th conventional example, and there is no need to use a dummy insulating film, and the trench side ends are not exposed. Therefore, it is suitable for the fine width of the element area. And charge storage Since the layers are completely separated in the element separation region, it is not necessary to cut the charge accumulation layer into a gap shape on the element separation region. Therefore, it is possible to miniaturize the width of the element separation region. However, on the other hand, the second conventional example The STI cell structure shown in the figure has a problem that when the insulating film for element separation is buried in a trench, the buried aspect ratio becomes high, and the width of the 7G component separation region cannot be miniaturized. As mentioned earlier, the first The well-known STI cell structure makes a part of the charge accumulation layer protrude along the element separation insulating film, so that its relative area to the control gate is relatively large. However, this section 2-13- This paper standard applies to Chinese national standards (CNS ) A4 size (210 X 297 mm) * 丨 ΓΓ ------- install ----.---- order --------- (Please read the precautions on the back before filling (This page) 484228 A7-One B7 V. Inventive cutting (11) " ^ ~ The m-cell structure of the conventional example borrows the lateral area of the charge storage layer—the area facing the control gate. Therefore, the charge storage layer The film thickness must be made the necessary thickness in the area opposite to the control gate. The vertical ratio of the buried insulating film without holes is 2. For example, consider the depth of the trench. 3 Please set the charge accumulation layer = 0.15. The thickness of the masking material is 0. In this case, the separation width of the embeddable element is 0 · 275. In contrast, in the sti cell structure shown in the i-th conventional example, the charge accumulation layer is not sandwiched during embedding. 7 The aspect ratio is low. It can be embedded up to the element separation width of 0.2 " m. In contrast, the STI cell structure of the second conventional example is not the gap processing of the charge storage layer: it is limited by the embedding of the insulating film for element separation. Element separation width. As mentioned above, the non-volatile semiconductor memory arrangement with the conventional STI cell structure makes it difficult to miniaturize the width of the element region and the element separation width, which has the problem of limiting the miniaturization of the memory cell. SUMMARY OF THE INVENTION A first object of the present invention is to provide a non-volatile semiconductor memory device and a method for manufacturing the same. Rewrite function. A second object of the present invention is to provide a non-volatile semiconductor memory device and a method for manufacturing the same, which do not cause a reduction in the thickness of the element separation insulating film caused by the separation of the charge accumulation layer, and thus do not cause a short circuit between gates. Poor or deteriorated component separation function can achieve the miniaturization of memory cells. A third object of the present invention is to provide a high-density non-volatile semiconductor memory device and a method for manufacturing the same, which can reduce the embedded aspect ratio of the element separation insulating film. -14- This paper standard is applicable to China National Standard (CNS) A4 (210 X 297 mm) --- 1 —rr ------- install (please read the precautions on the back before filling this page)-^ 1 ϋ n = -OJ I ϋ I m Intellectual Property of the Ministry of Economic Affairs Printed by the Bureau's Consumer Cooperatives 484228 Printed by the Consumers 'Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs A7 B7 Λ Ο ~ —' V. Description of the invention () Small, which can reduce the separation width of the components of the memory cell. According to the first aspect of the present invention, a non-volatile semiconductor memory device may be provided, including: an element separation insulating film formed on the semiconductor substrate to distinguish the element formation area; and a memory cell array, The memory cell is formed by arranging memory cells in an array, and the memory cell has: an i-th gate, which is formed on the semiconductor substrate, and is formed through an i-th gate insulating film; and a second gate, which is an i-th gate. On the gate, formed by a second gate insulating film; the first gate of the aforementioned memory cell is formed in a pattern from the above-mentioned element formation area to the above-mentioned element separation insulating film, and a part of the pattern is formed; and The first gate is adjacent to the element separation insulating film sandwiched between the element formation regions, and a protective insulating film is disposed. The non-volatile semiconductor memory device of the present invention is provided with a protective insulating film on the element separation insulating film sandwiched between the element formation regions, which can prevent the film thickness of the element separation insulating film from decreasing and prevent the element separation function from being reduced. Under these ten conditions, the uniformity of the capacitors can be improved by making the first gate surface slightly flat. Also, if the protective insulating film is continuously arranged on the element isolation insulating film in a direction perpendicular to the length direction of the second gate, a groove will not be formed on the element isolation insulating film across the adjacent gates, and It can prevent accidents of short circuit between gates. According to a second aspect of the present invention, a non-volatile semiconductor memory device can be provided, comprising: an element separation insulating film for distinguishing plural numbers formed on the semiconductor substrate and continuous in a direction at a specific interval; And the memory cell array, which are based on the aforementioned semiconductor-based -15- this paper size applies Chinese National Standard (CNS) A4 specifications (210 X 297 public love) I-I Γ III ------ I-- (Please read the precautions on the back before filling out this page) 484228 A7 B7 V. Description of the invention (13 Printed on the printed board of the employee consumer cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs, multiple memory cells are arranged in an array, It has two cells: a charge accumulation layer, which is formed in the aforementioned element formation area, and a formation of a h 绫 1 insulation film; and a control gate, which is arranged across the front fan-dagger 1 dry insulation film A plurality of memory cells in the direction of the cross-section are used here. ^ One, one is continuously arranged on the second layer of the animal layer through the second gate insulating film; the aforementioned memory cell # " fop layer is from the aforementioned element formation area Up to the aforementioned components ，， 刀 _ The pattern is formed on the insulating film in the form of “one-shaft overlap”, and is connected to the above-mentioned Thunderhead I and the layer Zheng 'on the component-separated insulating film sandwiched by the component-forming area. The gate insulation film and the protection cover covered by the control gate—the mantle film. ^% The structure and materials used in the various parts of the memory device of the present invention are as described: ① The element isolation insulation film is processed on the semiconductor substrate and the groove is processed. It is formed by being buried in this trench. The element isolation insulating film does not need to be an insulating film that traverses the entirety. For example, in a trench processed on a semiconductor substrate, a semiconductor such as a polycrystalline dream is placed through the insulating film. It can be buried, and its surface can be covered with an insulating film. In addition, the element isolation insulating film can also be formed according to the selective oxidation method (LOCOS). ② The element formation region is an active layer region divided by the element isolation insulating film. ③ Di 1 gate edge film is a channel insulation film. Ideally, the channel insulation film is a silicon oxide film formed by thermal oxidation, or a silicon nitride film formed by thermal nitridation or stacking method. Film (such as 0N0 film). In addition, the channel insulation film can also be a silicon nitride oxide film. Please read the note on the back? Matters before filling out this page} ading · -16- This paper size applies to Chinese national standards ( CNS) A4 specification (21 × X 297 mm) 484228 A7 B7 V. Description of the invention (14 Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs ④ Charge accumulation layer of the first gate, in other words, a floating gate. The first gate system Polycrystalline or amorphous fragments that increase conductivity due to impurity doping. ⑤ The second gate insulating film is a silicon oxide film, a silicon nitride film, a silicon oxide nitride film, or a silicon oxide film and silicon nitride. Laminated film (such as ONO film). ⑥ The second gate is a control gate. In addition to polycrystalline silicon or amorphous silicon that can raise the conductive layer by impurity doping, tungsten (w ) And other high-melting-point metals such as silicides, laminated films of silicides and silicon, and titanium (Ti) deposited on silicon to make these chemically reacted silicides, aluminum and other metals.保护 The protective insulating film disposed on the element separation insulating film must be an insulation film different from the element separation insulating film, in other words, it must be an insulation film different from the etching characteristics of the element separation insulating film. For example, in the case where the insulating film is separated from the silicon oxide film, the protective insulating film may be a silicon nitride film. According to a third aspect of the present invention, a method for providing a non-volatile semiconductor memory device can be provided, which includes the following steps: a step of "stacking a first gate insulating film on a board with a gate insulating film; On the ^ gate material film, the step of masking the element separation into a pattern is described in the mask material, which etches the aforementioned material film and semiconductor substrate: Section: Continuous element formation in: 1 direction The area is formed perpendicular to the first direction (: 2 million directions, and is distinguished by a specific interval.) The foregoing component separation groove is formed slightly from the aforementioned masking material = on the component separation insulation film, continuous in the p direction. Square ^ = The protective insulating film for protecting the element from the insulating film: the step of preserving the film to form a pattern. The steps of using the insulating film are described below, and the laminated film is used as a mask. -17- (Please read the precautions on the back before filling out this page): Packing. This paper size applies the Chinese National Standard " 7CNS) A4 Regulation (〇_ X 297 mm) 484228

Description of the invention ((Please read the precautions on the back before filling in this page) The step of etching and removing the masking material; by stacking the second gate material film and polishing its surface, the aforementioned laminated film is formed on the element separation insulating film The step of separating the charge storage layer formed by the laminated structure of the first! Gate material film and the second gate material film; removing money from the aforementioned insulation film for separation between the element separation insulating film, and accumulating the aforementioned charge. A step of depositing a third gate material film on the second insulating film and the protective insulating film; and sequentially etching the third gate material film, the second gate insulating film, and the charge accumulation layer in the second direction. The continuous control gate integrates with itself and forms a pattern of the charge accumulation layer separated in the ρ direction. The employee cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs prints a non-volatile semiconductor memory device according to the fourth aspect of the present invention. , Which is a plurality of memory cells connected to form a cell array, the memory cell has: a plurality of grooves, which are arranged on a semiconductor substrate to extend in one direction, 7G piece separation area It is a device isolation insulating film embedded in the aforementioned trench, and a plurality of semiconductor regions are electrically separated according to the aforementioned device isolation region; a charge accumulation layer is disposed on the aforementioned semiconductor region and insulated by a first gate And a control gate formed on the aforementioned charge accumulation layer through a second gate insulating film; the charge accumulation layer is a laminated structure of two or more conductive layers, wherein The position of the side end of the lowermost conductive layer is consistent with the position of the groove wall, and the width of the uppermost conductive layer is the same as or wider than the width of the lowermost conductive layer. The uppermost layer of the storage layer is the same. In this non-volatile semiconductor memory device, the charge storage layer is a laminated structure of two or more conductive layers, and the position of the side ends of the lowermost conductive layer is equal to -18- Paper size applies Chinese National Standard (CNS) A4 specification (210 X 297 mm) 484228 A7 Description of the invention (due to the consistent position of the trench wall, no parasitic Mos transistor will be formed on the upper end of the trench Therefore, the width of the device area can be reduced, and the device can be miniaturized. (Please read the precautions on the back before filling in this page.) Also, the width of the top layer of the charge storage layer is wider than the bottom layer. Control the capacitance between the gates. It is preferable that the height position of the upper surface of the insulating film for element separation is consistent with the height position of the uppermost layer of the charge storage layer. With this, the insulation film between the charge storage layers of the control gate can be formed stably. In addition, by this flattening, the error of the opposing area between the control gate and the charge accumulation layer can be suppressed, and the cell characteristics can be made uniform. The Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs printed the fifth aspect of the present invention, A non-volatile semiconductor memory device can be provided, which is composed of a plurality of memory cells connected to form a cell array, the memory cell has: a plurality of grooves, which extend in a direction on the semiconductor substrate ~ setter; component separation area, It is a device in which an element isolation insulating film is buried in the aforementioned trench; a plurality of semiconductor regions are each electrically separated according to the aforementioned element isolation region The charge storage layer is formed on the semiconductor region through a first gate insulating film; and the control gate is formed on the charge storage layer through a second gate insulating film; the control gate is characterized in that: The charge accumulation layer is a laminated structure of more than two conductive layers, wherein the position of the side ends of the lowermost conductive layer is consistent with the position of the aforementioned groove wall, and the width of the uppermost conductive layer is the same as that of the lowermost conductive layer. The width is the same or wider, and the foregoing: The upper surface of the insulating film for separating pieces is located between the lower surface and the upper surface of the uppermost layer of the charge storage layer. In this non-volatile semiconductor memory device, the charge accumulation layer is a laminated structure of two or more conductive layers, and the position of the side end of the lowermost conductive layer is equal to -19 _% 4228. Explanation of the invention (capacitors can also be formed Therefore, the overall capacitance can be increased, and the voltage applied to the control gate during data rewriting can be reduced. (Please read the note on the back? Matters before filling out this page.) The uppermost step of the charge storage layer is preferably a certain value in the cell array. This stabilizes the characteristics of the cell. The cell array includes a layered gate structure with the same layer as the memory cell. The selection transistor for switching is ideal. Thereby, the selection transistor can be formed by the manufacturing steps of the memory cell. The non-volatile semiconductor memory device further has a transistor, and the transistor preferably includes the following gate electrode: the first gate electrode, It is formed on a semiconductor substrate with a third gate insulating film interposed therebetween, and a second gate electrode is formed by contacting the first gate electrode. The surrounding transistor is made into a layered gate structure similar to the memory cell, which can reduce the step difference during gate processing. The structure of the third gate insulating film of the transistor is a layer including at least two kinds of films with different film thicknesses. # · The third gate insulation film for the high-voltage withstand voltage application in the aforementioned transistor is thicker than the first gate insulation film, and the third gate insulation film and the first gate use for the low voltage application in the transistor Those with the same or thin insulation film thickness are justified. Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs, the low-voltage drive that constitutes the sense amplifier can be driven by: The high voltage-driven high-resistance body is constructed to realize a non-volatile semiconductor memory device that can operate with a single power supply. The first gate electrode is -21-19484228 A7 which is electrically connected to the same charge storage layer as above. 2. Description of the invention (formed by the Ministry of Economics and Finance of the People's Republic of China) Consumption of two or more conductive layers; the position of the end of the side that is in contact with the lowermost layer of the third electrode: the conductive layer It is better to use the same position of the groove wall as described above: This' can make the gate electrode of the transistor into the same layered structure as the charge storage layer and control gate of the memory cell, so the manufacturing steps can be Simplification: The conductive layer forming the plurality of electrodes is composed of the same conductive layer as the conductive accumulation layer of the charge accumulation layer; the second idle electrode is composed of the same material as the control cell of the memory cell. It is better to make troubles: Cheng: The gate electrode constituting the transistor can be made into the same layered structure as that of the memory cell and the control gate of the memory cell. N 'The aforementioned memory cell array is simplified. The component isolation insulating film buried in the aforementioned trench is different from the uppermost segment of the aforementioned charge accumulation layer, compared with the aforementioned electric crystal Cong II :: Road: the insulating membrane for component isolation buried in the aforementioned trench, It is better that the uppermost step difference of the first gate electrode is smaller. In this configuration < transistor section, the step of peeling off the second gate insulating film reduces the thickness of the element from the insulating film, and can be performed when the element isolation insulating film is returned to expose the side surface of the charge storage layer. The reason for total eclipse 'can be simplified. According to the sixth aspect of the present invention, a non-volatile semiconductor memory coat can be provided, which is formed by connecting a plurality of memory cells to form a cell array: a plurality of element separation regions, which are refilled on the semiconductor substrate to the reading item Body Pack -22- Paper-like ^ Applicable to China iii ^ 7CNS) A4 size ⑽χ 挪 公 爱

I 484228 A7 ah. 20 " One or five, description of the invention () In the extended trench, the component separation insulation film is buried; a plurality of semiconductor areas, which are electrically separated by the aforementioned component separation area respectively; charge accumulation The layer 'is formed by a laminated structure of two or more conductive layers formed by interposing a second ... insulating film on the aforementioned semiconductor region; and a control gate, which is on the aforementioned charge accumulation layer and is insulated by the second gate It is characterized in that the distance between the ends of the adjacent element isolation region side is γ, and the distance between the ends of the uppermost layer side of the charge storage layer XI is γ. When the distance is X2, the following relationship is satisfied: Y > X1 > X2 or Υ > χ and X2. Accordingly, since the width of the uppermost layer of the charge storage layer is wider than that of the lowermost layer, the capacitance between the charge storage layer and the control gate can be increased. According to a seventh aspect of the present invention, a non-volatile semiconductor memory device < manufacturing method may be provided, including the following steps: a step of forming a first gate insulating film on a semiconductor substrate; and the aforementioned gate insulation A step of forming a conductive layer that becomes the lowermost layer of the charge accumulation layer on the film; a step of forming a masking material on the conductive layer; a step of forming the masking material, the first conductive layer, and the first gate insulating film And the aforementioned semiconductor substrate, so that the side end portions are etched in a uniform manner to form trenches; at least the steps of oxidizing the surfaces of the trench sidewalls and the sidewalls of the aforementioned conductive layer; and stacking element insulation films, A step of burying a trench; a step of planarizing the aforementioned insulating film for element separation to expose the upper surface of the mask material; a step of stripping the aforementioned mask material to expose the upper surface of the conductive layer; on the semiconductor substrate Step of depositing a second conductive layer that becomes the uppermost layer of the charge accumulation layer; flatten the second conductive layer to make it -23- paper size Applicable to China National Standard (CNS) A4 specification (210 X 297 mm) (Please read the note on the back? Matters before filling out this page) _ Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs 4228 A7 Employees of the Intellectual Property Bureau of the Ministry of Economic Affairs 5. Printed by the consumer cooperative. 5. Description of the invention (21) The step of forming the same plane as the above-mentioned insulating film for element separation; forming the second gate insulating film on the aforementioned second conductive layer and the aforementioned insulating film for element separation; A step of depositing a control gate material on the second gate insulating film; and a step of processing the deposited control gate material into a specific shape. According to an eighth aspect of the present invention, a method for manufacturing a nonvolatile semiconductor memory device is provided, which includes the following steps: a step of forming a first gate insulating film on a semiconductor substrate, and the aforementioned gate insulation A step of forming a first conductive layer that becomes the lowermost layer of the charge accumulation layer on the film; a step of forming a masking material on the first conductive layer; a step of forming the masking material, the first conductive layer, and the first gate The step of etching the insulating film and the semiconductor substrate so that their side ends are aligned to form a trench; at least a step of oxidizing the surface of the trench sidewall and the sidewall of the first conductive layer; insulation for separating the stacked components A step of burying a trench, a step of burying a trench; a step of flattening the insulating film for element separation to expose the upper surface of the masking material; a step of stripping the masking material to expose the upper surface of the first conductive layer; A step of depositing a second conductive layer that becomes the uppermost layer of the charge accumulation layer on the semiconductor substrate; planarizing the second conductive layer so that its upper surface is in contact with the aforementioned element A step of forming the upper surface of the insulating film for separation into the same plane; performing a selective etching step such that the upper surface of the insulating film for element separation is located between the lower surface and the upper surface of the second conductive layer; A step of forming a second gate insulating film on the side wall of the second conductive layer, the upper surface of the second conductive layer, and the upper surface of the insulating film for element separation; Steps; and a step of processing the stacked control gate material into a specific shape. -24- This paper size applies to China National Standard (CNS) A4 specification (210 X 297 public love) (Please read the note on the back? Matters before filling out this page);

According to a ninth aspect of the present invention, a method for a non-volatile semiconductor memory device can be provided, which includes the following steps: a step of forming a first gate insulating film on a semiconductor substrate; and insulating the first gate. On the film, the first layer to become the lowest layer of the charge accumulation layer is formed! A step of forming a conductive layer; a step of forming a masking material on the first conductive layer; placing the masking material, the first conductive layer, the first gate insulating film, and the semiconductor substrate at positions on the sides thereof The step of etching to form a trench in a consistent manner; at least the step of performing an oxidation treatment on the sidewall of the trench and the surface of the aforementioned first conductive layer; the step of depositing an insulating film for component separation and burying the trench; The step of flattening the insulating film for element separation and exposing the upper surface of the masking material; the step of peeling off the masking material and exposing the recesses on the i-th conductive layer; and etching isotropically to make the recesses horizontal A step of increasing the width; a step of depositing the second conductive layer which is the uppermost layer of the charge accumulation layer on the semiconductor substrate on the aforementioned insulating film for element separation and in the aforementioned recess, to planarize the second conductive layer so that A step in which the upper surface thereof is the same plane as the upper surface of the edge film for element separation; so that the upper surface of the insulating film for element separation is located below the second conductive layer; A step of selective etching is performed between the two types, and a second gate insulation is formed on the side wall of the second conductive layer, the upper surface of the second conductive layer, and the upper surface of the insulating film for element separation exposed by the etching. A film step; a step of depositing a control gate material on the aforementioned second gate insulating film; and a step of processing the deposited control gate material into a specific shape. Accordingly, the related non-volatile semiconductor memory device can be stably manufactured. According to the tenth aspect of the present invention, a non-volatile semiconductor memory can be provided. -25 · Applicable to Chinese national standard (〇NS) A4 standard (210 X 297 public love) paper size " ~-(Please read the back first Note to note? Matters should be filled out on this page again.) Order ·· # Printed by the Consumers' Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs 484228 A7 ------------- Β7 _____ V. Description of the invention (23) Device manufacturing The method is characterized in that it includes the following steps: forming a first gate insulating film on a semiconductor substrate; and forming the bottommost layer of a horse charge storage layer on the aforementioned W gate insulating film! A step of conducting layer; a step of forming a masking material on the aforementioned first conductive cladding layer; so that the aforementioned masking material, the aforementioned first conductive layer f, the aforementioned ... insulating film, and the side end portions of the aforementioned semiconductor substrate become the same: Step of etching to form a trench; at least a step of oxidizing the surface of the trench sidewall and the first conductive layer sidewall; a step of burying the trench with an insulating film for stacking part separation; and insulating the component isolation The step of flattening the film to expose the aforementioned masking material; the step of peeling the aforementioned masking material to expose the upper surface of the i-th conductive layer; and depositing on the semiconductor substrate f the second conductive layer which is the uppermost layer of the charge accumulation layer Step; ^ the step of planarizing the second conductive layer so that the upper surface thereof is on the same plane as the upper surface of the insulating film for element separation; so that the upper surface of the insulating film for element separation is located from the lower surface to the upper surface of the second conductive layer; Selective etching step; the side wall of the second conductive layer exposed above, the upper surface of the second conductive layer, and the element isolation insulation are etched accordingly. The above 'a second step of forming the gate insulating film; on the gate insulating film on the second step of stacking a control gate material; and the processing of the deposited material to a control gate of the steps in a particular shape. According to an eleventh aspect of the present invention, a method for manufacturing a non-volatile semiconductor memory device is provided, which includes the following steps: a step of forming a first gate insulating film on a semiconductor substrate; and on the first gate insulating film Form the bottom of the charge accumulation layer! The step of conducting layer; the step of forming a masking material on the aforementioned first conductive layer; making the aforementioned masking material and the aforementioned first conductive -26- This paper size applies to China National Standard (CNS) A4 (210 x 297 mm) (Please read the notes on the back before filling out this page) Printed by the Consumers ’Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs, and a description of the invention (24) -Then the position of the first gate insulating film and the side end of the semiconductor substrate At least, the step of forming a trench by etching is to at least oxidize the aforementioned trench side-from the surface of the side wall of the first guide cladding, and the trench is buried using a marginal membrane. Step of separating the aforementioned components: a step of flattening the film and exposing the upper surface of the aforementioned masking material, peeling off the first 2 masking materials, and exposing the upper surface of the β-th electrical layer to form a recess / The step of isotropic (isotropic) etching to increase the width of the recessed portion, on the semiconductor substrate, a second conductive layer, which is the uppermost layer of the charge accumulation layer, is deposited on the element isolation insulating film and the foregoing. ≪Step; in recess A step of planarizing the second conductive layer so that its upper surface is on the same plane as the upper surface of the insulating film for element cutting; so that the upper surface of the insulating film for element separation is located between the lower surface and the upper surface of the second conductive layer, A selective etching step; and a step of forming a second gate insulating film by etching to expose the side wall of the second conductive layer, the upper surface of the second conductive layer, and the upper surface of the insulating film for element isolation. A step of depositing a control gate material on the aforementioned second gate insulating film; and a step of processing the deposited control gate material into a specific shape. Description of the Drawings Figure 1 is a plan view of a memory cell array of a conventional EEPROM. 2A and 2B are cross-sectional views of A-A, B-B of FIG. 1. FIG. 3 is a diagram showing dimensions of each part of a conventional memory cell structure. Figures 4A-4E are cross-sectional views of the manufacturing steps of a conventional memory cell. 5A and 5B are a plan view and a cross-sectional view showing a structure of a nonvolatile semiconductor memory device according to a second conventional example. 27- This paper size is in accordance with Chinese National Standard (CNS) A4 (210 X 297 mm) (Please read the notes on the back before filling out this page) • Binding • Printed by the Intellectual Property Bureau of the Ministry of Economic Affairs and Consumer Cooperatives 484228 A7 5 6. Description of the invention (FIGS. 6A-6D are cross-sectional views of steps in the process for obtaining the structure shown in FIGS. 5A and 56. FIGS. 7A and 7B are succinct diagrams of the structure of the nonvolatile semiconductor memory device of the third conventional example 7A and 7B. Figs. 9A-9C are cross-sectional structural representations of a memory cell and a peripheral circuit transistor of the iEEpROM in the first embodiment of the present invention. Fig. 10 is a plan view of a memory cell array of an EEPROM according to a second embodiment of the present invention. Figs. 1A-1 1C are cross-sectional views taken along lines AA, BB, and c_c 'of Fig. 10. Figs. 12A-12C are used for A_A, BB, and C-C, cross-sectional views of the processing steps for forming the element separation groove of the memory cell array of the second embodiment. Figures 1 A-1 3 C are each used to form the memory of the second embodiment AA, BB, and CC, cross section Figures 1 4 A -1 4 C are sectional views A_A, B_B, and C-C, respectively, for forming the protective insulating film forming steps of the memory cell array of the second embodiment. Figure 1 5 A 1 5 C is an AA ′, BB, and C-Cf cross-sectional view of the steps of forming the second gate material film of the memory cell array of the second embodiment. FIG. 1 6 A AA, B-Bf, and C-C 'cross-sectional views of the steps of forming the second gate material film of the memory cell array of the second embodiment. Figures 17A-17C are each used to form the second embodiment. A_A 'and a cross-sectional view of the step of forming the third gate material film of the memory cell array. Figures 1 A- 1 8C are gates used to form the memory cell array of the second embodiment. Standard (CNS) A4 specification (210 x 2 mm) (Please read the precautions on the back before filling out this page) Packing. Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 484228 A7 ___ B7 26 V. Description of Invention () Cross section of AA, BB, and CC of the electrode. (Please read the precautions on the back before filling this page.) Figure 3 shows the sum of the EEPROM memory cell array. 1 A and 1 1 B are sectional views. Figures 20 A-2 0 F are sectional views of steps in the manufacturing steps of the memory cell according to the third embodiment of the present invention. Figure 2 A and 2 1 B are EEPROMs A plan view and a cross-sectional view of a structure of a peripheral circuit transistor region. Figs. 2A and 2B are plan views of a nonvolatile semiconductor memory device according to a fourth embodiment of the present invention. Figure 2 3 A 2 3 D is a sectional view of the steps used to obtain the manufacturing steps of the structure of Figures 22A and 22B. Fig. 24 is a sectional view of a special case of the structure shown in Fig. 2 3A. Figs. 25A and 25B are a plan view and a cross-sectional view of a nonvolatile semiconductor memory device according to a fifth embodiment of the present invention. Figures 26A-26D are cross-sectional views of steps used to obtain the manufacturing steps of the structure of Figures 25A and 25B. Fig. 27 is a sectional view of a special case of the structure shown in Fig. 25A. Figs. 2A and 2B are a plan view and a sectional view of a nonvolatile semiconductor memory device according to a sixth embodiment of the present invention. Printed by the Employees' Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs. Figures 29A-29D are cross-sectional views of the steps used to obtain the manufacturing process of Figures 28A and 28B. 30A and 30B are a plan view and a cross-sectional view of a nonvolatile semiconductor memory device according to a seventh embodiment of the present invention. Figure 31 1 shows the general characteristics of the non-volatile semiconductor memory device of the present invention. -29- This paper size applies to China National Standard (CNS) A4 (210 X 297 mm)% 4228

Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs. 32A-32D are plan and sectional views showing the structure of a low-voltage transistor and a highly durable transistor used in a nonvolatile semiconductor memory device according to an eighth embodiment of the present invention. 33A-33F are cross-sectional views of steps in a process of manufacturing a low-voltage transistor. 34A-34F are cross-sectional views of steps in a process of manufacturing a high-withstand piezoelectric crystal. 35A and 35B are cross-sectional views of a special case of the structure shown in Figs. 32A-32D. Preferred Embodiments Several embodiments of the present invention will be described below with reference to the drawings. Figs. 9A to 9C show a cross-sectional structure of a main part of eeprom in the first embodiment of the present invention. Fig. 9A is a cross-sectional view of the word line (WL) direction (width direction of the memory cell channel) of the memory cell portion, and Fig. 9B is a cross-sectional view of the same bit line (BL) direction (length direction of the memory cell channel). 9C is a cross-sectional structure of a peripheral circuit transistor. On the p-type silicon substrate 1, for example, the element isolation insulating film 2 is embedded according to the STI technology, and the element formation region 3 is distinguished. The memory cell array region is formed by forming a laminated film of the first gate material film 5 a and the second gate material film 5 b through the first gate insulating film (ie, the channel insulating film 4) in the element formation region as charge accumulation. The first gate (floating gate) of the layer ^ is formed on the floating chamber 2 and the second gate (control gate) 8 made of the third gate material film is formed through the second insulating film 7 '. The control room 8 is formed in a continuous pattern in the plane of FIG. 9A, and it becomes a character line. The formation of the self-integrated gate 8 as a source-pumped n + diffusion layer 6. The second gate material film 5 b constituting the floating gate 5 of the memory cell, although it is clamped to the element -30- This paper size applies the Chinese National Standard (CNS) A4 specification (210 X 297 mm) (Please read the note on the back ? Fill in this page again) ^ • Order · 484228

The separation insulating film 2 ′ forms a pattern from the element forming region 3 which becomes a recessed portion and partially overlaps the element separation insulating film 2, but as shown in 1 (a), the upper surface of the floating gate 5 is slightly flat across the whole. shape. The flattening of the surface of the floating gate 5 does not require a flattening process of |, and the element forming region sandwiched by the element separation insulating film 2 has a narrow width. By selecting a floating gate having the same width or more, The deposited film thickness of 5 is flattened. On the other hand, the peripheral circuit transistor is generally larger in size than the memory cell. Therefore, as shown in Fig. 9C, the first gate 5 'formed using the same material as the memory cell array portion and the floating gate 5 reflects the step difference between the element separation insulating film 2 and the element formation region 3. At this time, the film thickness of the floating gate 5 on the element forming region 3 of the memory cell becomes a + b. That is, the film thickness a on the element separation insulating film 2 is added to the step difference b between the element separation insulating film 2 and the element formation region 3. On the other hand, the film thickness of the first gate 5 'on the element formation region 3 of the peripheral circuit transistor is d. Therefore, the film thickness a + b of the floating gate 5 on the element formation region of the memory cell is larger than the film thickness d of the gate 5 on the element formation region of the peripheral circuit transistor. In the peripheral circuit transistor, the i-th gate 5 and the second gate 8 '(the same material as the control gate 8 of the memory cell) are short-circuited at appropriate positions and used as gate electrodes. FIG. 10 is a plan view of a memory cell array area of a NOR-type EEPROM according to the second embodiment of the present invention. 11A, 11B, and 11C are each a cross-section of A-A ', BB', and C-C of FIG. That is, FIG. 11A is a cross-sectional view of the word line (WL) direction of the memory cell section (channel width direction of the memory cell), and FIG. 11B is the same bit line direction (BL) direction (channel length direction of the memory cell) Section view. FIG. 1C shows a cross-sectional structure of the element separation membrane portion. -31-This paper size is in accordance with Chinese National Standard (CNS) A4 (210 X 297 mm) (Please read the notes on the back before filling out this page) Order,-Printed by the Employees' Cooperative of Intellectual Property Bureau of the Ministry of Economic Affairs 484228 A7 ____ B7 29 ----- V. Description of the invention () The P-type silicon substrate 1 is an element separation insulating film 2 formed at equal intervals in the y direction (word line direction), in the y direction (bit perpendicular to the X direction). Element line direction) distinguishes a plurality of elongated element forming regions 3. The first cell array region forms a first gate (floating gate) 5 as a charge accumulation layer on the element formation region 3, which passes through the first! The gate insulating film and the channel insulating film 4 are made of a laminated film of a first gate material film 5a and a second gate material film 讪. Although the second gate material film 5b constituting the floating gate 5 of the memory cell is sandwiched between the element isolation insulating film 2 and the element formation region 3 which becomes a recessed portion, the pattern is formed so as to partially overlap the element isolation insulating film 2. As shown in Fig. 1a, the upper surface of the floating gate 5 is generally flat. The planarization of the surface of the floating gate 5 is not to perform an active planarization process, and the width of the element forming region 3 sandwiched by the insulating film 2 can be narrowed by the element separation. The stacked film thickness of the floating gate 5 described above achieves planarization. The floating gate 5 is formed with a second gate (control gate) 8 formed of a third gate material film via a second gate insulating film 7. The floating gates 5 are each independently formed in each memory cell, and the control gates 8 are zigzag lines w L formed continuously in the X direction. The formation of the control gate 8 self-integration becomes the source-n-type n + -type diffusion layer 6. The y-direction side ends of the control gate 8 and the floating gate 5 are formed by self-integration. By performing ion implantation using this layered gate as a mask, an n + -type diffusion layer 6 serving as a source is formed. The surface forming the memory cell is covered by an interlayer insulating film. Here, the bit line (B L) 10 is continuously arranged in the y direction. -32- This paper size is in accordance with China National Standard (CNS) A4 (210 X 297 mm) (Please read the note on the back? Matters before filling out this page).

The 5th series of Yangzha Gate 5 is formed from the element forming area of the aluminum 绦 丨 front 丨 knife set ® is formed on the element separation, rest, and film 2 'as shown in the cross-section of FIG. 11A, cut on the edge film 2 in the χ direction Broken into gaps, each memory cell is separated. The x direction on the element separation insulating film 2 is opposite to the adjacent::: Shao, a protective insulating film n is arranged at this end, which is used to prevent the element separation insulating film 2 The film thickness is reduced. As described later, in the form of being integrated into the protective insulating film n, the closed material film of the floating gate 5 is formed by metal inlay molding, and is cut by the protective insulating film 11 in the χ direction. ㈣The insulating film u is shown in FIG. 2. The S element insulating film 2 is continuously arranged in the 7 direction, and is also arranged in the area less than the control gate 8. Net: > The protective insulating film Η must be a different type of insulating film from the element separation insulating film 2. For example, when the element isolation insulating film 2 is mainly composed of a silicon oxide film, the protective insulating film 1 1 is composed of an insulating film mainly composed of a silicon nitride film. In addition, the thickness of the protective insulating film 11 is made thinner than the film thickness of the floating gate 5 (more specifically, the tongue 'refers to the film thickness of the second gate material film 5 b). The upper surface of the floating gate 5 of the memory cell is 0. As described above, the width of the element formation region is narrow, while the deposited film thickness of the gate material film becomes slightly flat when it is thicker to a certain extent or more. In this way, if the surface of the floating gate 5 is flat as described above, the error (unevenness) of the capacitive coupling between the floating gate 5 and the control gate 8 will be reduced, and the characteristics of the complex memory cells will change. Therefore, the data rewriting function is excellent. Specifically, it refers to the EEPROM with a small threshold of data writing state or erasing state. Secondly, refer to Figures 12A_12c -33- corresponding to the cross-sections of the steps corresponding to Figure 1 1A-1 1C. This paper size applies the Chinese National Standard (CNS) A4 specification (210 X 297 mm). C Please read the note on the back first? Please fill in this page for further information)-Binding · Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 484228 Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs A7 Heart 31 V. Description of the invention () to Figure 16 A-1 6 C, The manufacturing steps of the EEPROM cell array of this embodiment will be described. As shown in FIGS. 12A-12C, after the channel insulating film 4 is formed by thermal oxidation on a p-type silicon substrate 丄, a first gate material film 5a is deposited, and a masking material 2 is formed thereon. The first gate material film 5 a is, for example, a polycrystalline silicon film. The mask material 21 is patterned in such a manner as to cover an element formation area, such as a silicon nitride film. Using this masking material 21, the first gate material film 5a and even the substrate 1 are etched by RIE to form trenches 20 in the element isolation region. Next, as shown in FIGS. 3A to 1C, the element isolation insulating film 2 formed of the silicon oxide film is buried in the trench 20 formed on the substrate 1 so that the surface is flat. The planarization of the surface is performed by, for example, depositing a thick silicon oxide film thicker than the depth of the groove. In contrast, the masking material 21 made of the silicon nitride film may be used as a stopper for CMP. Next, as shown in Figs. 14A-14C, a protective insulating film for protecting the element-separating insulating film 2 is deposited on the planarized substrate of the element separation, and then stacked to embed the floating gate by the metal inlay method. The gate-embedding insulating film 22 is formed. Specifically, the protective insulating film u is a silicon nitride film, and the gate embedding insulating film 22 is a TEOS oxide film. Thereafter, as shown in FIG. 14A-14, the second gate material film is buried in the element isolation insulating film 2 in the X direction with the gate insulating film 22 separated. Thereafter, the insulating film 22 for gate embedding is removed by wet etching such as hydrofluoric acid. At this time, the protective insulating film U formed of the silicon nitride film will not be etched, but will remain on the element isolation insulating film 2. That is, the laminated film of the i-th gate material film 5 & and the second gate material film 爽 keeps the element-separated insulating film 2 between the memory cells and the element-separated insulation -34- This paper standard applies to the Chinese National Standard (CNS) A4 size (210 X 297 mm) (Please read the note on the back? Matters before filling out this page)-Equipment. Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 484228 A7 ---- B7 32 V. Description of the invention () The film is separated, and the element separation insulation film 2 of the separation portion is covered with the protective insulation film 11. In this embodiment, the insulating film 22 for burying the gate is removed after the floating gate 5 is formed as described above, but the protective insulating film 丨 remains on the element isolation insulating film 2 as it is. Thereafter, as shown in FIGS. 1A to 10C, an ONO film is formed as a second gate insulating film 7 on which a third gate material film 8a is deposited. The third gate material film 8 & is a polycrystalline silicon film, a layered layer of a polycrystalline silicon film and a metal film, a metal fragment, a self-aligne (j) polycrystalline film, and the like. Thereafter, the third gate material film 8 is Etching, as shown in Figures 8 A-1 8 C, is the formation pattern of the control gate 8 that becomes the word line WL continuous in the x direction. At the same time, the floating gate 5 below is also formed by the integration of the control gate 8 The position above the floating gate 5 is higher than the position above the protective insulating film 11 on the element separation insulating film 2. Therefore, the control gate 8 is formed not only on the floating gate 5 but also through the second gate insulating film 7 Later, according to ion implantation, a diffusion layer 6 is formed as shown in FIG. N A-nc. In addition, an interlayer insulating film 9 is stacked, a via hole is opened, and a bit line 10 is provided. According to this embodiment, each floats The element separation of the gate 5 The isolation on the insulating film 2 is not performed by etching the gate material film, but is performed by embedding the gate material film of the metal damascene method. Therefore, it is not necessary to separate the elements as usual. In the case of gap processing of the gate material film on the insulating film, the component is separated. A groove is formed on the insulating film. Accordingly, the short-circuit failure between the control gates can be suppressed. Moreover, as shown in FIGS. 15A-15C, the step of removing the masking material 21 used in the process of separating the grooves of the components is performed according to the protective insulating film. And masking material ^ Protection-35 · This paper size is applicable to China National Standard (CNS) A4 (210 X 297mm f) (Please read the precautions on the back before filling this page): 484228 A7 Description of invention (component separation The insulating film 2 prevents the element from being separated. The film thickness of the insulating film 2 is reduced. Also, the patterning steps of the control gate 8 and the floating window 5 shown in Figs. 18A-18C are also (please read the precautions on the back before filling this page) Although the etching step of the gate insulating film 7 made of the ONO film is added, as shown in FIG. 9C, the surface of # of the element isolation insulating film 2 is protected by the protective insulating film 11 to prevent the element from being insulated. The film thickness of the film 2 is reduced. In the above-mentioned embodiment, although the element separation insulation τ knife and the protective insulating film 11 on the S-edge film 2 are not removed to the last and remain, they are shown in FIG. 13B. After the insulation energy is removed, the insulation film 22 for gate embedding is removed, and then It is also possible to go to the protective insulation & " In this case, the pattern processing steps of the control room 8 and the floating gate 5, especially the step of etching the gate insulating film 7, will cause the film thickness of the element separation insulating film 2 to decrease. $, Which is different from the conventional method of adding a groove on the element separation insulating film before the gate material film is deposited. At least, when the gate material film is stacked, no groove is formed on the element separation insulating film 2, which can be prevented and controlled. The effect of a short circuit occurring between the gates. Figs. 19A and 19B correspond to Figs. 11A and 11B, respectively, showing the cross-sectional structure of the EEPROM cell array according to the second embodiment of the present invention. In this embodiment, the conditions of the element separation step and the gate formation step are the same. The previous embodiment is different, and the corner of the upper end of the element formation region 3 is rounded. However, the basic structure is the same as that of the first-cut embodiment, and the plan view is the same as that shown in Figure 10. Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs The manufacturing steps of this embodiment will be described in detail with reference to FIGS. 20A to 2F. As shown in FIG. 20A, a masking material 31 for element separation processing is formed on the surface of the p-type silicon substrate 1 through a sacrificial oxide film 4a. The masking material 31 in the present embodiment is polycrystalline silicon. Using this masking material 31, the substrate-36 paper size is applicable to China National Standard (CNS) A4 specification (210 X 297 mm) 484228 A7 " ^ '------- 2Z ----- -χ 34 -----— 5. Description of the invention () The element separation trench 2 is formed by etching according to RIE. Next, an oxide film is formed on the exposed surface of the element separation trench 20 by thermal oxidation, and the bird's beak oxide film is eaten on the upper part of the element formation region 3 to perform smooth processing. Thereafter, as shown in FIG. 20B, the oxide film is buried in the same flat shape as in the previous embodiment as an & The planarization of the surface is performed by, for example, depositing a thick silicon oxide film thicker than the depth of the groove. For this purpose, the masking material 31 made of the polycrystalline silicon film may be used as a stopper for CMP. Secondly, as shown in FIG. 2 OC, a protective insulating film for protecting the element separating insulating film 2 is deposited on the substrate for planarization of the element separation, and then an insulating film for burying the gate for separating and forming a floating gate is deposited. 3. Specifically, the protective insulating film 11 is a silicon nitride film, and the gate-insulating insulating film 32 is a TEOS oxide film. Thereafter, as shown in FIG. 20D, the gate buried insulating film 32 is etched and etched by light to form a continuous mask pattern on the tg-piece separation insulating film 2 in the direction of FIG. The gate insulating film 32 is used as a mask to etch the protective insulating film, and the masking material 3 i on the element formation area is etched and removed. Then, a thick polycrystalline silicon is deposited as the i-th gate. The material film is flattened by a CMP process using the gate-insulating insulating film 32 as a catch. Accordingly, as shown in FIG. 20E, the floating gate 5 is patterned on the element isolation insulating film 2 in the x direction with the gate buried insulating film 32 separated. Thereafter, the gate-insulating insulating film 32 is removed by wet etching such as hydrofluoric acid. Therefore, the 'floating gate 5 is between the adjacent memory cells sandwiching the element separation insulation film' is separated on the element separation insulation film 2 to become the floating-37- Chinese paper standard (CNS) A4 Specifications (210 X 297 mm) (Please read the precautions on the back before filling out this page) J ^ T · Printed by the Intellectual Property Bureau of the Ministry of Economic Affairs Consumer Cooperatives 484228 A7 -------__ 35 ---- --- V. Description of the invention () The state of the protective insulation film " (Please read the precautions on the back before filling this page.) The insulating film 32 for gate embedding is removed after the floating gate 5 is formed as described above. The Inho insulating film 1 1 remains on the element isolation insulating film 2 as it is. . Thereafter, as shown in FIG. 20F, the second gate insulating gate 7 is actuated through the ONO film, and the second gate material film is stacked to form the control gate 8. The second gate material film is a polycrystalline silicon film, a laminated film of a polycrystalline silicon film and a metal film, a metal silicide film, a film, and the like. The control gate 8 is shown in FIG. 10 or FIG. 11B, and a pattern is formed as a continuous word line WL in the χ direction. At the same time, the floating gate 5 below it also integrates with the control gate 8 to form a pattern. The position of the upper surface of the floating gate 5 is higher than the position of the upper surface of the protective film 11 on the element separation insulating film 2. Therefore, the control gate 8 is formed not only on the floating gate 5 but also on the side via the second gate insulating film 7. Although the floating gate 5 is formed through the first gate insulating film 4 after the components are separated in this embodiment, the component is prevented from being separated during the masking material peeling step by using the protective insulating film arranged on the element separation insulating film 2i. The reduction in the film thickness of the insulating film 2 and the prevention of the reduction in the film thickness of the element separation insulating film 2 in the step of forming the laminated gate structure are the same as in the previous embodiment. Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs in the first and second embodiments described above, although the memory cell array area is described, the peripheral circuits formed simultaneously with the memory cell array are better.示 的 结构。 Shows the structure. 21A and 21B are a plan view of the peripheral circuit transistor q and its surroundings, and a D-D 'cross-sectional view thereof. That is, the same thin insulation film 1 1 ′ as the protective insulating film i 丨 formed on the element isolation insulating film 2 in the memory cell array region is used as a virtual pattern on the element isolation insulating film 2 around the peripheral circuit transistor Q. , Such as forming a periodic pattern. The gate system of the peripheral circuit transistor Q is the same as that of the memory cell array. -38- This paper size applies the Chinese National Standard (CNS) A4 specification (210 χ 297 mm) 484228 A7 B7 _ 36 --------- —— V. Description of the invention () The gate insulation film overlaps to form the U5th and top 8 'laminated structures that are short-circuited at appropriate positions. In this case, as described in Embodiments 2 and 3, the flattening and embedding by the metal damascene method are performed. * In the flattening step of the CMP process, it is known that there is a large space, and polishing can be performed quickly, so it cannot be flattened uniformly. If a protective insulating film is formed around the transistor Q in FIG. 21A as a virtual pattern, the material film of the gate 5 formed at the same time as the floating gate 5 of the memory cell is ground and buried to protect the insulation. The film u becomes a stopper, and it is possible to complete the planarization excellent in uniformity. The invention is not limited to the embodiments described above. For example, in the embodiment, a nor-type control gate is taken as an example, but the present invention can also be applied to a non-volatile memory cell type, an AND type, a DINOR type, and the like having a layered gate structure with a charge accumulation layer and a control gate. Other EEPROM. As described above, according to the present invention, an EEPROM can be obtained, which is to flatten the surface of the floating gate 'to suppress the non-uniformity of the capacitive coupling when the memory cell is miniaturized', and to perform excellent data rewriting Performance person. In addition, by arranging a protective insulating film on the element isolation insulating film between the memory cells, an EEPROM can be obtained, which can prevent the reduction of the film thickness of the element isolation insulating film caused by the separation of the charge accumulation layer or the short circuit between the gates. And can achieve the miniaturization of memory cells. 22A and 22B are memory cell structures according to the fourth embodiment of the present invention. FIG. 22A is a plan view and FIG. 22B is a cross-sectional view. A trench 20 for element separation is formed on the P-type substrate 1 or the p-well 1. The trench 20 is embedded with a silicon dioxide material, for example, to form the element isolation insulating film 2. -39-This paper size is in accordance with China National Standard (CNS) A4 (210 X 297 mm) Ί4ιί J ------ Package --- (Please read the notes on the back before filling this page) Order the Ministry of Economy Printed by the Intellectual Property Bureau's Consumer Cooperatives 484228 Α7 ___ Β7 37 V. Description of the invention () Channel area 3 on the substrate where this component is separated. On the whole, for example, a silicon dioxide film having a thickness of 150 A (angstrom) or less is formed as a thin channel insulating film 24 through which a channel current can flow. A first conductive layer 25 is formed thereon, and the side ends of the first conductive layer 25 are formed. The parts are co-located with the ends of the component separation area. Although the oxide film 33 is formed on the inner surface of the trench 20 and the end surface on the element isolation region side of the first conductive layer 25, the oxide film is omitted for the sake of simplicity in the subsequent drawings. A second conductive layer 26 is formed on the first conductive layer 25 in contact with the first conductive layer 25, and its side end is slightly wider than the first conductive layer 25. The charge storage layer 27 is formed by the laminated structure of the first conductive layer 25 and the second conductive layer 26. The upper surface of the element separation insulating film 23 is the same as the upper surface of the charge storage layer 27, and is separated from the upper surfaces. The inter-gate insulation film 2 8 forms the control gate 2 9. As shown in FIG. 22A, the control gate 29 and the charge accumulation layer 27 are processed by themselves in such a manner that the side edges are aligned in the vertical direction, and an n-type diffusion layer 34 is formed between the gates. Figures 23A-23D are cross-sectional views of steps used to obtain the self-integrated STI cell structure shown in Figures 22A and 22B. First, a channel insulating film 24 is formed on the semiconductor substrate 1, and a polysilicon layer doped with impurities is deposited by the CVD method as the first conductive layer 25, and a photoresist is deposited thereon as a masking material 35. . Next, the masking material 35, the first conductive layer 25, the channel insulating film 24, and the semiconductor substrate 21 in the element separation region are etched and removed to form the grooves 20 so that the positions of the side ends are consistent (FIG. 23A) 〇-40- This paper size is in accordance with Chinese National Standard (CNS) A4 (210 X 297 mm) C Please read the note on the back first? Please fill in this page again for the matter}-¾ Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 484228 A7

V. Description of the invention () Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs, followed by oxidation treatment or surface modification, etc., the side walls of the trench 20 and the side walls of the M conductive layer 25 are oxygenated, and the components are separated. The surface of the insulating film 2 is deposited, and the surface is polished according to dry etching or chemical polishing (cMp), the element isolation insulating film 2 is flattened, and finally the upper surface of the masking material 35 is exposed (FIG. 23B). Next, the masking material 35 is peeled off to expose the upper surface of the second conductive layer 25, and the second conductive layer 26 made of a polysilicon layer doped with impurities is completely deposited, and the second conductive layer 26 is etched or polished to a plane. The second conductive layer 26 is separated until the element isolation insulating film 23 is exposed (FIG. 23c). The i-th conductive layer 25 and the second conductive layer 26 have the function of the charge accumulation layer 27 as described above. Next, the inter-gate insulation film 28 and the control gate are stacked, and gate processing is performed to complete the cell structure (Fig. 23D). In the structure obtained by this process, the first! Since the side wall of the conductive layer 25 is slightly receded due to the oxidation step after the groove formation, the width of the second conductive layer 26 becomes slightly wider than the width of the first conductive layer 25. In addition, when the second conductive layer 26 is deposited, the upper surface of the i-th conductive layer 25 is cleaned by chemical treatment, and a small oxide film is formed on the i-th conductive layer to form the first conductive layer 25 and the second conductive layer. The shape of an oxide film is sandwiched between the conductive layers 26. However, since the oxide film is extremely thin, there is no problem in electrical conduction, and the first conductive layer and the second conductive layer are maintained at the same potential. The memory cell of this first embodiment has the following characteristics. First, in the STUfe structure shown in the above-mentioned second conventional example, when the trench is separated into elements and the insulating film is buried, there is a problem that the buried aspect ratio becomes high. In contrast, the present invention uses the charge accumulation layer as the first conductive layer and the second conductive layer. -41-This paper size is applicable to China National Standard (CNS) A4 (210 X 297 mm) (Please read the note on the back first) Please fill in this page for further information.) • Installed 484228 printed by A7 B7 of the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs. 5. Description of the invention () Because of the layered structure of the layers, the aspect ratio of the component insulation film is embedded. The thickness of the first conductive layer film and the thickness of the masking material are determined. Therefore, by making the film thickness of the first conductive layer thinner than the film thickness of the second conductive layer, the buried aspect ratio can be reduced. For example, consider a case where the depth of the groove is set to 0.3 and the film thickness of the charge accumulation layer is 0. 15 " m. If it is set that the aspect ratio in which the insulating film for element separation can be provided with holes is 2, the thickness of the masking material is set to 0.1 m, and the thickness of the first conductive layer is set to 0 05. " m, the buried element separation width is 0.225 " m, which can make the element separation width finer than the STI cell structure of the second conventional example shown previously. Furthermore, by stacking the second conductive layer on the first conductive layer 25, the film thickness of the desired charge accumulation layer 27 necessary for gate processing control can be matched, and the first gate insulation can be formed. The decrease in the impurity concentration of the i-th conductive layer 25 at the film interface can reduce the resistance of the entire charge storage layer 27. In addition, in order to increase the capacitance between the charge storage layer 27 and the control gate 29, for example, the upper surface of the charge storage layer 27 may be roughened, and the second conductive layer 26 may be sufficiently deposited. This roughening process can be performed after the components are separated and buried. In addition, in order to control the threshold voltage and voltage of a memory cell, a transistor, and the like, impurities are infiltrated into the semiconductor substrate under the gate electrode because the first conductive layer 2 5 is thin. At this point, ion implantation can be performed after a high-temperature heat treatment step necessary for the formation of a gate insulating film such as thermal oxidation, and the impurity distribution in the semiconductor substrate can be precisely controlled. In addition, in the memory cell shown in the fourth embodiment, the top of the charge accumulation layer 27 is completely flat in the cell array. Therefore, the upper surface of the charge accumulation layer is controlled. ) A4 size (210 X 297 mm) (Please read the precautions on the back before filling out this page) • -Packing.- 484228 A7 V. Description of the invention (the area error capacitance error can constitute a neat rewrite feature Although FIG. 24 has a structure similar to that of FIG. 22B, the side positions of the i-th conductive layer 25 and the second conductive layer 26 constituting the charge accumulation layer 27 are exemplified, and the widths of the two layers are consistent. Obtained by combining materials and conditions that cause the first conductive layer 25 to recede little due to etching when the trench 23 is formed, or by surface modification treatment other than oxidation that does not cause the i-th conductive layer to recede. Obtained. This structure is a self-integrated structure, there is no step difference, no parasitic capacitance is generated, and it is expected to improve the characteristics by smooth charge movement. Figures 2 A, 2 5 B are the fifth embodiment of the present invention Nonvolatile Semiconductor 25A is a plan view, and FIG. 25B is a F_F and a cross-sectional view of the device. A trench 42 for element separation is formed on a p-type silicon substrate or a p-well 41, and, for example, a silicon dioxide material is buried in the trench 4 2. Insulating material for element separation 43. A thin channel insulating film 44 through which channel current can flow is formed on the entire channel region on the substrate of such element separation, and a first conductive layer 45 is formed thereon. The position of the side end portion of 45 is the same as the end portion of the element isolation region 43. The second conductive layer 46 is formed on the first conductive layer 45 in contact with the first conductive layer, and its side end portion is more than the first conductive layer. 45 is slightly wider and extends to the outside. The laminated structure of the i-th conductive layer 45 and the second conductive layer 46 constitutes a charge storage layer 47. The element isolation insulating film 43 is located slightly higher than the lower surface of the second conductive layer 46. Position, on this second conductive layer 4 6 above and in the side wall, the components are separated than -43- This paper size applies to China National Standard (CNS) A4 (210 X 297 mm) (Please read the precautions on the back before reading) (Fill in this page)% Intellectual Property Bureau of the Ministry of Economic Affairs Employee Cooperatives Print Wisdom of the Ministry of Economic Affairs Printed by employee property cooperative of property bureau 484228 A7 __B7 41 V. Description of the invention () In the part where the insulation film is located, an inter-gate insulation film 48 is formed on a part of the element separation insulation film 43, and a control gate 49 is formed thereon. As shown in FIG. 25A, the control gate 49 and the charge accumulation layer 47 are integrated and processed by themselves so as to align the side ends in the vertical direction to form an n-type diffusion layer 51 between the gates. Figure 2 6 A -2 6 D is a sectional view showing the steps of the process for obtaining the STI cell structure shown in Figs. 2 a and 2 5 B. A channel insulating film 44 is formed on a semiconductor substrate 41, and an i-th conductive layer 45 and Mask material 52. Thereafter, the mask material 52, the first conductive layer 45, the channel insulating film 44 and the side ends of the semiconductor substrate 41 of the element isolation region are aligned so as to form a trench 42. Next, an oxidation treatment or a surface modification treatment is performed, the sidewalls of the trench 42 and the sidewalls of the first conductive layer 45 are oxidized, and the insulating film 43 for element separation is deposited, and then etched back by dry etching or chemically polished ... 乂"The surface is polished, the element isolation insulating film 43 is flattened, and finally the top surface of the masking material 52 is exposed (Fig. 26A). Next, the masking material is peeled off and the second conductive layer 46 is continuously deposited (Fig. 26B). Next, the second conductive layer 46 is etched or plane-polished until the element isolation insulating film 43 is exposed, and the second conductive layer 46 is separated (FIG. 26). Only the element isolation insulating film 43 is etched and etched. The upper surface thereof reaches any position within the thickness of the second conductive layer 46, for example, to a position corresponding to a thickness of 1/3 or 1/4 from the lower surface, and then a gate-to-gate insulating film and a control gate 49 are stacked to complete the gate processing. Structure (Fig. 2 6d). Although the upper position of the element separation insulating film 43 is lower than the second conductive layer 46, the capacitance can be increased, but it is almost impossible to form a stable position (please read the (Please fill in this page again) Order ... -44-

42484228 A7 V. Description of the invention (Because of the inter-gate insulation film on the lower side, consideration should be given to determine its position. The memory cell of this fifth embodiment is two = J Dianhe He accumulation layer 4 7 spot i order to make the gate The capacitance between 49 makes the second conductive ^ 4 and ^ a side of the electric arm 46 exposed to make the control gate 49 facing each other. Therefore, the bismuth person-^ has made the coupling capacitance better than the first The memory cell shown in the embodiment is larger. In addition, the difference between the upper surface of the second conductive layer and the non-layer 40 and the upper surface of the element separation insulating film 48 can be adjusted by the electric field storage layer 47 and the control gate 49 by J Jitian. The capacitance between the capacitor and the desired 値 is set to obtain the relative area, and the segment difference can be made uniform in the cell array ... In order to easily expose a part of the side wall, it is desirable to make the second conductive layer 46 The thickness is made thicker than the thickness of the first conductive layer 45. Fig. 27 and Fig. 24 show that the i-th conductive layer 45 and the second conductive layer have the same width, which is a structure for self-integrated manufacturing. Fig. 28A And 28B show the cell structure of the non-volatile semiconductor memory device according to the sixth embodiment of the present invention. Fig. 28A is a plan view, and Fig. 28B is a G_G, cross-sectional view. This structure is similar to the second embodiment, and the corresponding constituent elements are shown on the reference signs of the fifth embodiment shown in Figs. 2 5 A and 2 5 B. If you add 20, it becomes 60 ~, 70 ~. The difference between the fifth embodiment and the sixth embodiment is that the second conductive layer 46 is equivalent to the second conductive layer 66 in the fifth embodiment! The point where the width of the conductive layer 65 is wide. Figs. 28A and 28B clearly show the point where the width of the second conductive layer is widened. Figs. 29A-29D are steps of a process for obtaining the cell structure shown in Figs. 28A and 28B. Cross-section view. A channel insulation film 64 is formed on the semiconductor substrate 61, and the i-45th is stacked thereon.-This paper size applies the Chinese National Standard (CNS) A4 specification (210 X 297 mm). Γ I -11 --- -Install --- (Please read the notes on the back before filling out this page). Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 484228 Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs A7 B7 V. Description of Invention (43) Conductive Layer 65 and masking material 72. In this state, the masking material 72, the first The electrical layer 65, the channel insulation film 64, and the side ends of the semiconductor substrate 61 are removed in an aligned manner to form a trench 62. Then, an oxidation treatment or a surface improvement treatment is performed to make the sidewall of the trench 62 and the first conductive The surface of the side wall of the layer 6 5 is oxidized and then the insulating film for element separation 6 2 is deposited, and the surface is polished according to dry etching or chemical polishing (CMP) to planarize the insulating film for element separation, and finally the mask material The upper surface of 72 is exposed (FIG. 29A) After the masking material 72 is peeled off, the isolating film for element separation is etched by a desired amount in the horizontal direction by isotropic etching such as wet etching. As a result, a portion having no element isolation insulating film wider than the width is formed on the first conductive layer 65 (FIG. 2B). Secondly, a second conductive layer 66 is deposited on the entire surface of the semiconductor substrate, and the second semiconductor is etched back or ground until the element isolation insulating film 63 is exposed, and the second conductive layer is separated (Fig. 29C). Next, the element isolation insulating film 63 is additionally etched back so that the element isolation insulating film 63 is retracted to the lower side of the second conductive layer 66 and the upper side of the second conductive layer 66 is exposed. In this state, the inter-gate insulation film 68 and the control gate 69 are stacked, and idle processing is performed to complete the cell structure (Fig. 29D). In the memory cell of this third embodiment, the element conductive insulating film is etched only by a desired amount in the lateral direction after the masking material 72 is peeled off, so that the second conductive layer can be made smaller than the first conductive layer. Structure with wider element width. Therefore, the memory cell shown in the third embodiment can be compared with the memory cell and the -46- shown in the first embodiment (please read the precautions on the back before filling this page)-

484228 A7 ----------- B7 V. Description of the Invention (44) The memory cell shown in the second embodiment can further improve the charge storage capacity. Furthermore, after the second conductive layer 66 is flattened, the element isolation insulating film 63 is additionally etched to expose a part of the side surface of the charge accumulation layer 67, which is used to expose the control gate 69 and the charge accumulation layer. The step of increasing the capacitance of 67 is not carried out under the condition that the capacitance between the control gate 6 9 and the charge accumulation layer 67 can be sufficiently increased only by the relative area above the charge accumulation layer 67. necessary. Figs. 30A and 30B show a nonvolatile semiconductor memory device according to a seventh embodiment of the present invention. Fig. 30A is a plan view, and Fig. 30B is? F_F and a cross-sectional view. The cross-sectional view shown in FIG. 3 OB is exactly the same as the cross-sectional view shown in FIG. 25β = it is indicated that the same structural elements are marked with the same reference numerals, and their details are omitted. This embodiment shows a case where a NAND structure is used as a cell array structure. . That is, the 16 cells connected in series in this embodiment are connected to the bit line and the source line via the selection transistor 53. The selected crystal system is composed of the same film thickness and the same laminated structure as the cell 7. In the memory cell, the gate electrode of the accumulation layer also forms a floating structure in the selection transistor = between the transistors between adjacent bit lines, the charge accumulation layer is not electrically charged, and the appearance of the memory cell and the selection transistor is No different. , Huai, = Necessary memory cell is different from the choice of transistor. The transistor system is selected based on the combination of the capacitance of the storage layer and the gate, and a second voltage is applied to the charge storage layer. Therefore, by applying a voltage to the control gate, you can perform normal daily turnover. Therefore, by making the memory cell and the selection transistor into the same body: • 47- This paper size is applicable to the Chinese National Standard (CNS) A4 specification (210 X 297, issued 484228 A7 ____ B7 45 V. Description of the invention () 1You can omit unnecessary processing steps inside the cell, and you can make the memory cell in the least number of steps. In addition, the AND type or DINOR type array structure other than the NAND structure also connects plural memory cells in parallel or in parallel to form a unit. In the connection of the bit line or the source line, it is a selection transistor through a switching transistor, and this embodiment can be used in the same way. Fig. 3 1 shows the distance between the side ends of the element separation region of each of the above embodiments and Element cross-sectional view of the relationship between the distance between the uppermost layers and the distance between the lowermost layers of the charge storage layer. As described above, the width of the uppermost layer of the charge storage layer is made wider than the width of the lowermost layer. The distance between the region side ends is X 1, and the distance between the lowermost side ends of the adjacent charge storage layers is Y '. When the distance between the uppermost side ends is X 2, Y &X; X is satisfied. 1 > X2 or Υ > X1 = χ2. Figure 3 2 A-3 2 D is a non-volatile semiconductor memory device according to the eighth embodiment of the present invention. Figure 32A is a plan view of a low voltage transistor, and Figure 32B is a j_ J 32C is a plan view of a high-resistance piezoelectric crystal, and FIG. 32D is a K-K 'section view. These are authors of the same element. Although the planar structure is the same, if the cross-sectional structure is viewed, any All of them have laminated gates, which have: a lower gate, which has the same two-layer structure as the charge accumulation layer (83, 87 for low voltage, 8 3, 9 7 for high withstand voltage); and 8 8 for upper gate, It is made of the same conductive layer as the control gate -48- This paper size is applicable to China National Standard (CNS) A4 (210 X 297 mm) (Please read the precautions on the back before filling out this page)-installed. Ministry of Economic Affairs Printed by the Intellectual Property Bureau employee consumer cooperative 484228 A7 ____ B7 46 V. Description of the invention () (Please read the notes on the back before filling out this page) The creator. Among them, the thickness of the upper layer in the lower gate is for low voltage electricity consumption The crystal is thicker than the transistor for high withstand voltage. Furthermore, the low voltage transistor has a thin gate oxygen The chemical film 82 has a thick gate oxide film 92 compared to this. Nannan Dust-resistant transistor is based on the following reasons. Generally, the sense amplifier and booster circuit that drive the memory cell, and the input and output switch circuits are used in combination with voltage. The desired gate insulation film thickness of the transistor, the low-voltage transistor in the sense amplifier can use high-speed transistors in the memory cell channel insulation film is the same or thinner than the channel insulation film. On the other hand, drive the memory cell The high-voltage booster circuit used for data rewriting or the input / output switch circuit can perform high-voltage operation. The high-withstand voltage series transistor uses a gate insulating film that is thicker than the channel insulating film. 33A-33F are cross-sectional views of steps in a process of manufacturing a low-voltage memory cell transistor of the nonvolatile semiconductor memory device shown in FIGS. 32A and 32B. 34A-34F are cross-sectional views of steps in a process of manufacturing a high-voltage electric memory cell transistor of the nonvolatile semiconductor memory device shown in FIGS. 32A and 32B. Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs. A plurality of gate insulating films are formed on the semiconductor substrate 81 with a desired film thickness. For example, a 100A thermal oxide film is used as a channel insulation film 8 2 for a memory cell formed by a low-voltage transistor, or an 8 〇A thermal oxide film 8 2 is used as a thin gate for sensing amplifier operation NMOS and PMOS. Insulation film. On the other hand, for example, a thermal oxide film 92 of 200A each is formed as a thick gate insulating film for a high-withstand piezoelectric crystal that functions as a booster circuit, and a first conductive layer 8 3 and a masking material 84 (FIG. 33A, Figure 34A). The trench insulating film 85 is formed by aligning the channel insulating film formed by the mask material, the first conductive layer, and a plurality of film thicknesses of the device isolation region with the gate insulating film and the side ends of the semiconductor substrate (Figs. 33B and 34B). -49- This paper size is in accordance with Chinese National Standard (CNS) A4 (210 X 297 mm) 4228 A7

τρ 47 IX. Description of the invention () After the side walls of the trench 85 and the first conductive layer 8 3 are oxidized, the insulating film 86 for separating the components is deposited, and etched back by dry etching or chemical polishing (CMP) The surface is polished to planarize the insulating film 86 for element separation, and the upper surface of the masking material 8 4 is preferably exposed (FIG. 3 3 C). At this time, regardless of whether the thickness of the gate insulation film is different or not, the height after etching is the same. The thickness of the masking material remaining in the low-voltage transistor and the high-resistance® transistor is 8 4 and 8 4 They are different. The peeling masking material is a second conductive layer deposited on a semiconductor substrate, and the second conductive layer is left over or planarly polished until the insulating film for element isolation is exposed, and the second conductive layer is separated. At this time, the thickness of the second conductive layer is also different from that shown in 87 of the low-voltage transistor and 97 of the high-endurance piezoelectric crystal (Fig. 12 (a) (d)). The laminated structure of the first conductive layer and the second conductive layer described above forms a charge storage layer or a first gate electrode. Next, the element separation memory cell 85 is additionally etched back to expose a part of the charge accumulation layer (83, 87, 97) and the first gate electrode (82, 92) (Fig. 12 (b) (e)). Next, for example, an ONO film is formed on the semiconductor substrate as an inter-gate insulating film. In addition to Yuan Yi Cell ', at least a part of the ON film of the peripheral circuit is peeled off, and the control gate 88 is deposited. In addition, the control gate is formed as a second gate circuit 88 in the transistor, so that the inter-gate insulation film is removed, and the i-th gate electrode and the second squeeze electrode are electrically connected to the same potential. Align the side ends of the laminated structure of the memory cell and the transistor to complete the cell structure and transistor structure (Figure 12 (c) (f)). The non-volatile semiconductor shown in this fifth embodiment The memory device constitutes -50- This paper size applies to the Chinese National Standard (CNS) A4 specification (210 X 297 mm) (please read the precautions on the back before filling this page). Printed by the cooperative 48484228 V. Description of the invention (The employees of the Intellectual Property Bureau of the Ministry of Economic Affairs consume the same gate material between printed memory cells and transistors in the cooperative, so they can easily realize the cost and high yield. &Amp; 'Make charge accumulation Part of the side of the layer is performed on the entire wafer, and it does not require a photo-etching step, which can achieve low cost. However, the exposed height is compared with that of the transistor because of the addition of the step _ 闸 间 绝 =. The memory cell is high. Therefore, the film thickness of the second conductive layer may be thicker than the film thickness required by the memory cell. This is a degree-configured gate structure that may affect the quality of the gate structure. The rate ° Before it is necessary to When the film thickness of the electrical layer is reduced to a thin layer, the retroactive photoetching step is used to expose a part of the side surface of the charge accumulation layer. The etchback step is performed only in the memory cell portion. In this case, the charge ^ The exposed height of the gate electrode and the first gate electrode is high in the memory cell even when the step of separating the gate insulating film is performed. The film thickness of the charge accumulation layer can be set to the necessary level in the memory cell. The film thickness of the second conductive layer is controlled. Fig. 13 shows the fifth embodiment in which the upper and lower layers of the first gate electrode have the same end face position according to the selection of appropriate conditions. Although various embodiments have been described above, The invention is not limited to the above-mentioned various embodiments, and may be variously modified. For example, in the embodiment, the electrode serving as the charge storage layer is formed into a two-layer structure, but a multilayer structure having three or more layers may be used. The uppermost layer may have the structure and function of the upper layer of the embodiment, and the lowermost layer may have the same structure and function of the lower layer of the embodiment. In addition, the channel insulating film as the first gate insulating film is in the embodiment. It uses the oxide cut layer, but it can also use the nitrided layer, oxynitrided layer, or any of these laminated layers, etc. -51 This paper size is applicable to China National Standard (CNS) A4 (210 X 297) Li) (Please read the note on the back? Matters before filling out this page) ^ • Printed by the Employees' Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 484228 A7 ____B7 _ Heart 49 5. Description of the invention () In addition, the charge accumulation layer and the control gate Although the insulating film is a silicon oxide film in the embodiment, a nitride film, an oxide nitride film, a laminated film of an oxide film and a nitride film, etc. may also be used. Also, although the control gate is used in the embodiment A polysilicon layer doped with impurities, but an amorphous silicon layer, a high-melting-point metal material layer such as tungsten, a low-resistance metal layer such as aluminum, and a metal silicide such as tungsten silicide (WSi) and silicon materials may be suitably used. Laminated, self-integrated polycrystalline silicon film formed by stacking metals such as titanium on the silicon material by chemical reaction through thermal annealing. In addition to the insulating film for element separation, in addition to the silicon dioxide having excellent embedding characteristics as described in the embodiment, a doped oxide film such as PSG or BPSG containing impurities such as phosphorus and boron, or Such a layered structure. Various capacitors, resistance elements, etc. other than the peripheral circuits can be modified and implemented in a manner not departing from the gist of the present invention, if necessary. < Effects of the invention> According to the present invention, in a non-volatile semiconductor memory device formed by a memory cell having a self-integrated STI structure (the self-integrated STI structure refers to a trench where a charge accumulation layer is separated from a 7G component). Those who self-form), the charge storage layer is formed into a laminated structure of at least two layers, and the first conductive layer is thinned to reduce the buried aspect ratio of the 7L separate insulating film. The second conductive layer is used for control Since the capacitance between the gates is desired, and the necessary film thickness is made, it can provide a large-capacity non-volatile semiconductor memory device with low cost and excellent intermetallicity, which has excellent process controllability and excellent data rewriting characteristics. (Please read the precautions on the back before filling this page) 丨 装 -52-

484228

[Explanation of the Invention] [Second Guideline] The layers are formed according to the flattening step of using an insulating film for element separation as a stopper. The necessary non-volatile semiconductor memory devices can be used. The first etching step, which is used to cut the # 破 拉 炫 ^ ^ tail end animal layer on the component separation area into a gap shape, ^ / is omitted, and can achieve the effect of reducing the manufacturing steps 0 (Please read the back Note: Please fill in this page again.) Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs-53- This paper size applies to China National Standard (CNS) A4 (210 X 297 mm)

Claims (1)

484228 6. Scope of patent application Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economics 1. A non-volatile semiconductor memory device, which is characterized by: It has an element separation insulation film formed on this semiconductor substrate to distinguish the element formation area And a memory cell array, which is formed by arranging memory cells in an array, the memory cell has: a first gate, which is connected to the aforementioned semiconductor substrate, separated by the second! The gate is formed by the insulating film; and the second gate is formed on the second gate by the second gate insulating film; the first gate of the memory cell is formed from the aforementioned element formation area to the aforementioned element On the separation insulating film, a part of the pattern is formed in a overlapping manner; and a protective insulation film is disposed on the separation insulating film adjacent to the first gate and sandwiched between the aforementioned components sandwiched by the aforementioned element formation area. 2. The non-volatile semiconductor memory device according to item 丨 of the application, wherein the surface of the aforementioned first gate is slightly flat. 3. The non-volatile semiconductor memory device according to item 1 of the patent application scope, wherein the second gate is a span of a plurality of memory cells arranged in a direction in which the above-mentioned element separation insulating film is transected. The upper part of the protective insulating film is arranged through the second gate insulating film. 4. The non-volatile semiconductor memory device according to item 丨 of the application, wherein the film thickness of the protective insulating film is thinner than the film thickness of the first gate on the element isolation film. 5. The non-volatile semiconductor memory device according to item 3 of the scope of the patent application, wherein the protective insulating film is arranged on the element isolation insulating film and is continuously arranged in a direction perpendicular to the length direction of the second gate. By. 6. If the non-volatile semiconductor memory device in item i of the patent application scope, its paper size is -54- applicable to China National Standard (CNS) A4 specifications (210 X 297 mm) (Please read the precautions on the back before filling (This page) --install _ϋ HI ϋ 0- II n ϋ ϋ · ϋ n I »Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 484228 ____g8s 6. In the scope of patent application, the components around the transistor of the peripheral circuit are separated A protective insulating film formed on the insulating film at the same time as the protective insulating film in the region of the memory cell array is configured as a virtual pattern. 7 · A non-volatile semiconductor memory device, comprising: an element separation insulating film for distinguishing a plurality of element formation regions formed on the semiconductor substrate and continuous at a certain interval in one direction; and A memory cell array is formed on the semiconductor substrate, and a plurality of memory cells are arranged in an array, and each memory cell has a charge storage layer formed in the aforementioned element formation region and formed through a first insulating film; and The control gate is a structure in which a plurality of memory cells arranged in a direction transverse to the element isolation insulation film are arranged, and the charge accumulation layer is continuously arranged through the second gate insulation film; the charge accumulation layer of the foregoing memory cell The pattern is formed from the element formation region to the element separation insulating film in a partly overlapping manner, and is adjacent to the charge accumulation layer. The element separation insulating film sandwiched by the element formation region is provided with The aforementioned .2 gate insulating film and the protective insulating film covered by the control gate. 8 · A method for manufacturing a non-volatile semiconductor memory device, which includes the following steps: a step of depositing a first gate material film on a semiconductor substrate via a first gate insulating film; and the first gate material film is described below , The step of separating the masking material used for component separation to form a pattern; -55- This paper size towel --.-- Γ I 1 I ---- install -------- order! --- (Please read the notes on the back before filling this page) Scope of patent application: The consumer cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs printed the masking material, and the aforementioned first gate material film and semiconductor substrate were oriented in the vertical direction of m, in a specific way; the steps of separating the grooves; The aforementioned element separation trench is the ancient VI, Xin-from >, and the masking material is embedded in the same plane position, and the step of embedding π pieces of insulation film is embedded on the aforementioned element separation insulation film. Mm V ^ In a continuous manner of 10,000, the layers used to protect the insulating film from the insulating film and the insulating film, and the remaining and laminated films for gate embedding are formed to form a pattern. Steps: The laminated film is used as a mask, and the aforementioned masking material is removed. The substrate is laminated with a second gate material film and its surface is polished, so that the laminated film is separated from the 7G insulating film. The steps of purely describing the charge accumulation layer formed by the lamination structure of the ^ 1 gate material film and the second gate material film. Before the aforementioned element separation insulating film is removed, the "separation insulating film is removed, and then the aforementioned charge accumulation layer is removed. And the above-mentioned protective insulating film, the second insulating film is deposited 3 gate material film steps; and etching the aforementioned third gate material film, second gate insulation film, and charge accumulation layer in accordance with f, and successively integrate the control gate in the second direction with itself, and accumulate charge accumulation separated in the first direction. Steps for forming a pattern in a layer 9. A non-volatile semiconductor device memory device, which connects a plurality of memory cells to form a cell array, the memory cells have: a plurality of grooves, which are directed on a semiconductor substrate Those extending in one direction; component separation areas that are embedded with component separation insulation films in the aforementioned trenches; multiple semiconductor areas 56- ^ Paper size applies to China National Standard (CNS) A4 specifications (21 × X 297 mm- -i Hr -------- install (please read the precautions on the back before filling this page) 2 to connect #-A8 B8 C8 D8 2. The scope of the patent application is based on the respective electrical separation of the aforementioned element separation area; the charge storage layer is formed on the semiconductor area and is separated by the first gate insulating film; and the control gate is connected to The charge storage layer is formed by interposing a second insulating film; it is characterized in that the fast charge storage layer is a laminated structure of two or more conductive layers, in which the bottom layer < the side end of the conductive layer The position is the same as that of the trench wall above. The width of the uppermost conductive layer is the same as the width of the lowermost conductive layer. The upper side of the aforementioned element separation insulating film is the same as the uppermost layer of the charge storage layer. Consistent. 10. The non-volatile semiconductor memory device according to item 9 of the patent scope, wherein the uppermost layer of conductive I included in the charge storage layer is formed by self-integration of the aforementioned element separation area. 11. The non-volatile semiconductor memory device according to item 9 of the patent application park, wherein the uppermost conductive layer and the lowermost conductive layer included in the aforementioned charge accumulation layer are in a short-circuited state or the same potential that is electrically connected . 12. The non-volatile semiconductor memory device according to item 9 of the application, wherein the film thickness of the uppermost conductive layer included in the charge storage layer is the same as or thicker than the film thickness of the lowermost conductive layer. 13. A type of non-volatile semiconductor memory device, which is composed of a plurality of memory cells connected to form a cell array, the memory cell has: a plurality of grooves, which are arranged on a semiconductor substrate to extend in one direction; a component separation area, It is a device isolation insulating film buried in the aforementioned trench; a plurality of semiconductor regions are electrically separated according to the aforementioned device isolation region; a charge storage layer is disposed on the aforementioned semiconductor region and separated by an i-th gate insulating film The shape of 57-sheet paper applies the Chinese National Standard (CNS) A4 specification (210 X 297 mm) (Please read the precautions on the back before filling out this page). Printed by the Intellectual Property Bureau of the Ministry of Economic Affairs and printed by the Consumer Cooperatives. Printed by the Ministry of Intellectual Property Bureau's Consumer Cooperatives 6. The applicants for the patent application scope are controlled by the aforementioned charge accumulation layer and formed by the second insulating film, which is characterized by the charge accumulation layer It is a laminated structure of more than two conductive layers. The position of the side end of the conductive layer is the same as the width of the upper conductive layer. Lowermost conductive layer of the same danger of dew or wider, the device isolation insulating film above the happy bit lines between the Park range above and below the most upper layer of the charge storage layer. 14. The non-volatile semiconductor memory device according to item 13 of the application, wherein the uppermost conductive layer included in the aforementioned charge accumulation layer is formed by self-integration of the aforementioned 70 separate areas. I5. If the non-volatile semiconductor memory device of item U of the patent application park is used, wherein the uppermost conductive layer and the most f-layer sense conductive layer included in the aforementioned charge accumulation layer are in a short-circuited state with electrical connection or the same Potential person. 16. The non-volatile semiconductor memory device according to item ls of the patent application park, wherein the film of the uppermost conductive layer included in the aforementioned charge accumulation layer is the same as or thicker than the film thickness of the lowermost conductive layer . 17. If the above-mentioned charge storage layer in the non-volatile semiconductor memory device according to item i 3 of the applied patent park is above the above-mentioned charge accumulation layer, the above-mentioned element separation insulating film, and the uppermost side of the above-mentioned charge accumulation layer, The second insulating film is formed from the upper surface of the insulating film for separation to the uppermost surface of the first insulating film, and the control gate is formed on the second insulating film. 18. The non-volatile semiconductor memory device according to item 13 of the scope of patent application, wherein the segment difference between the upper part of the insulating film for element separation buried in the groove and the uppermost layer of the charge storage layer is about within the cell array. For someone. -58- This paper size is in accordance with the Chinese National Standard (CNS) A4 specification (210 X 297 mm, whose I ^ I »ί ^ ^ -I -ϋ ii 1 I ^ I ^ β * ι π read first 03 read Remember to read and fill in the water page W / 484228 A8 B8 C8 D8 • 、 Applicable patent scope 19. If the non-volatile semiconductor memory device of item 9 of the patent scope is applied, it contains a selective transistor for switching in the aforementioned cell array, which is 1; and the aforementioned memory cell Constructor of the same laminated gate. 8. 20. If the non-volatile semiconductor memory device of the 19th scope of the application for a patent, and the aforementioned non-volatile semiconductor memory device further has a transistor ⑲--the aforementioned transistor includes: the i-th closed electrode, which is connected to the front half (2) a substrate formed by interposing a third gate insulating film; and a second gate electrode formed by contacting the first gate electrode. 21. The non-volatile semiconductor memory device according to claim 20, wherein the third gate insulating film of the transistor is configured as a layer including at least two kinds of films having different film thicknesses; The voltage-resistant application means that the third gate insulating film is thicker than the first gate insulating film, and the low voltage-resistant application in the transistor is that the third gate insulating film has the same thickness as the i-th gate insulating film or Thinner. '22. The non-volatile semiconductor memory device according to item 20 of the application, wherein the first gate electrode is formed of two or more conductive layers which are electrically connected to the same charge storage layer; The position of the side end portion where the element isolation region of the lowermost conductive layer of the gate electrode contacts is the same as the position of the groove wall. 23. The non-volatile semiconductor memory device as claimed in claim 20, wherein the plurality of conductive layers constituting the first gate electrode are made of the same conductive layer as the conductive plurality of conductive layers constituting the charge accumulation layer of the memory cell.材 59- This paper size is applicable to the Chinese National Standard (Cns) A4 specification (21 × 297 mm) ------ J ------ installed (please read the precautions on the back before filling this page) 1 I · ϋ ϋ 一 ^ ϋ ϋ I · ϋ mm — n I #-Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs The second gate electrode is composed of the same material as the aforementioned control gate of the aforementioned memory cell. 24. If the non-volatile semiconductor memory device according to item 18 of the patent scope, the step difference between the upper surface of the insulating film for element separation buried in the aforementioned groove in the memory cell array and the uppermost portion of the aforementioned charge accumulation layer, The difference between the upper part of the insulating film for element separation buried in the groove in the circuit part including the transistor and the uppermost part of the first gate electrode is 25. Such as the non-volatile semiconductor memory of the 18th scope of the patent application In the device, the difference between the upper part of the insulating film for separating the elements buried in the groove in the memory cell array and the uppermost part of the charge accumulation layer is smaller than that buried in the groove in the circuit including the private crystal. The step between the upper surface of the element separation insulating film and the uppermost portion of the first gate electrode is larger. 26 · A kind of non-volatile semiconductor memory device, which is composed of a plurality of memory cells connected to form a cell array, the memory cell has: a plurality of element separation regions, which are arranged in a groove extending in a direction on a semiconductor substrate, 7L buried insulation films; multiple semiconductor regions, which are electrically separated by the aforementioned element separation regions; a charge storage layer, which is formed by a first gate insulation film on the semiconductor region as described above A layered structure of two or more conductive layers; and a control gate, which is formed on the aforementioned charge accumulation layer and is formed through a second gate insulating film, and is characterized in that the adjacent element separation region is provided on the side When the distance between the ends is χ 1, the distance between the ends of the lowermost layer of the adjacent charge accumulation layers is γ, and the distance between the ends of the uppermost layer is X 2, the following relationship is satisfied: ----- ---, ------ Installation -------- Order --------- (Please read the precautions on the back before filling this page) # -60- This paper size applies to China National Standard (CNS) A4 specifications (210 X 297 male 1) 484228 A8 B8 C8 D8 Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 6. Scope of patent application Y > X1 > X2 or Υ > χι = χ2 0 27. A method for manufacturing a non-volatile semiconductor memory device, comprising the steps of: forming a first gate insulating film on a semiconductor substrate; and forming the first gate insulating film on the first gate insulating film. A step of forming the first conductive layer at the bottom of the charge accumulation layer; a step of forming a masking material on the first conductive layer; a step of forming the masking material, the first conductive layer, the first gate insulating film, and The semiconductor substrate is etched so that the side end portions thereof are aligned to form a trench; at least the step of performing an oxidation treatment on the surface of the sidewall of the trench and the surface of the sidewall of the first conductive layer; A step of embedding; a step of planarizing the insulating film for element separation to expose the upper surface of the masking material; peeling the masking material to make the i-th conductive layer Step of exposing the surface; step of depositing a second conductive layer which becomes the uppermost layer of the charge accumulation layer on the semiconductor substrate; flattening the second conductive layer so that the upper surface thereof is on the same plane as the upper surface of the element-dividing insulating film Steps: a step of forming a 2-gate insulating film on the aforementioned second conductive layer and the aforementioned insulating film for element separation; a step of depositing a control gate material on the second-gate insulating film, and a 2-part-61- (Please read the note on the back? Matters before filling out this page) Install! | Order! _1 #-484228 A8 B8 C8 D8 VI. Scope of patent application Steps for processing the stacked control gate materials into a specific shape. 28. The method for manufacturing a non-volatile semiconductor memory device according to item 27 of the scope of patent application, wherein the planarization steps of the aforementioned first and second conductive layers are performed by dry etching or grinding. 29 · A method for manufacturing a non-volatile semiconductor memory device, comprising the following steps: 'forming a first gate insulating film on a semiconductor substrate; and forming a charge on the first gate insulating film The step of forming the first conductive layer in the lowermost layer of the accumulation layer; the step of forming a masking material on the first conductive layer; the masking material, the first conductive layer, the first gate insulating film, and the semiconductor The substrate is etched in such a way that its side ends are aligned to form a trench; at least the step of performing oxidation treatment on the surface of the trench sidewall and the sidewall of the i-th conductive layer; stacking the insulating film for component separation, and burying the trench A step of flattening the insulating film for element separation to expose the upper surface of the masking material; a step of peeling the masking material to expose the upper surface of the first conductive layer; The step of the second conductive layer on the top of the charge accumulation layer; planarizing the second conductive layer so that the upper surface of the second conductive layer is separated from the above-mentioned elements for insulation. Steps for the film to become the same plane; 62- This paper size is applicable to China National Standard (CNS) A4 (210 X 297 mm) (Please read the precautions on the back before filling this page) Install IIII Order 1111! Ministry of Economy Wisdom Printed by the Consumer Cooperative of the Property Bureau Employees printed by the Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs 484228 6. Apply for a patent to make the above insulation film for component separation above the second conductive layer i in front of the front, A step of performing selective etching; a step of forming a second gate insulating film on the side wall of the second conductive layer, the upper surface of the second conductive layer, and the upper surface of the insulating film for element separation exposed by the etching; A step of depositing and controlling the gate material on the second gate insulating film; and a step of processing the deposited material into a specific shape. 30. A method for manufacturing a non-volatile semiconductor memory device, such as a patent application, in which the planarization step of the first ^ 2 conductive layer is performed by dry etching or grinding. 31 · A method for manufacturing a nonvolatile semiconductor memory device, comprising the following steps: forming a first gate insulating film on a semiconductor substrate; and forming a charge accumulation on the first gate insulating film The step of forming the first conductive layer at the bottom of the layer; the step of forming a masking material on the first conductive layer; 2 the masking material, the first conductive layer, the first gate insulating film ′, and the semiconductor substrate Steps of etching to form side grooves so as to form grooves; At least a step of performing oxidation treatment on the surfaces of the sidewalls of the trenches and the sidewalls of the P conductive layers; stacking the insulating film for component separation, and burying the trenches Steps; the steps of planarizing the aforementioned insulating film for element separation to expose the above mask; -63 'The paper size applies the Chinese National Standard (CNS) A4 specification (21〇χ 297 mm. ^ --- ----- ^ --------- (Please read the notes on the back before filling this page) 484228 A8 B8 C8 D8, the scope of patent application will ride the aforementioned masking material to form the first conductive step; 1 < The step of increasing the width of the concave portion by isotropic etching; depositing the second conductive layer, which is the uppermost layer of the charge accumulation layer on the semiconductor substrate, on the semiconductor film for isolation of components and the concave portion: ; The step of planarizing the second conductive layer so that the upper surface thereof is on the same plane as the upper surface of the insulating film for element separation; so that the upper surface of the insulating film for element separation is located below the second conductive layer ^ Selective etching is performed in a selective manner; a second gate insulating film is formed on the side wall of the second conductive layer, the upper surface of the second conductive layer, and the upper surface of the insulating film for element separation exposed by the etching. The step of depositing the control gate material on the aforementioned second gate insulating film; and the step of processing the deposited control gate material into a specific shape. 32. Non-volatile semiconductor memory such as the scope of application for item 3 丨The manufacturing method of the device, wherein the aforementioned first and second conductive layer planarization steps are performed by dry etching or grinding. ---------- Please read the back of C Please fill in this page for further information.) • 1 n «I mmmmm n i-Bi ϋ ϋ n ϋ ϋ« 1 1 ϋ I #-Printed by the Intellectual Property Bureau of the Ministry of Economic Affairs Employee Cooperatives 64 This paper size applies to Chinese National Standards (CNS) A4 specification (21〇 ^ 97 mm)