TW461843B - Chemical mechanical polish process for copper damascene structure - Google Patents

Abstract

This invention provides a chemical mechanical polish process for copper layer on semiconductor substrate. Firstly, a semiconductor substrate is given and a copper layer is formed on the substrate. Then, part of the copper layer is removed using the chemical mechanical polish process in which the semiconductor substrate is secured on a polish pad and polish slurry is sprayed on the pad to increase the effectiveness of polish. Subsequently, the supply of polish slurry is terminated and citric acid solution is sprayed on the pad to synchronically carry out a cleaning process and remove copper oxide micro particles on the surface of the substrate and the polishing pad.

Description

461843 V. Description of the invention (1) '-Field of the invention: The present invention relates to copper inlays and semiconductors in semiconductor manufacturing processes. It is an in-situ step when performing a chemical mechanical polishing process on a copper inlay structure. The process of removing pads and contaminated particles on the wafer surface is a ^^ process, in order to effectively reduce the chance of defects, remove particles on the polishing pad, and maintain a stable polishing rate. Background of the Invention: With the continuous development of the semiconductor industry, in the development and design of ultra large integrated circuits (ULSI), in order to meet the design trend of high density integrated circuits, the size of various components has been reduced to sub-micron β Due to the continuous shrinking of components, the related semiconductor process often encounters unprecedented problems, and the complexity of the process is also increasing. Generally speaking, 'integrated circuits include millions of components in a specific area on a wafer' and the electronic connection structure used to connect these components in order to perform the specific functions required. Performance, in addition to the performance and reliability of the contained components, also requires countless precision and fine metal interconnections' in order to effectively transfer electronic signals between components. Especially as the size of integrated circuits continues to shrink, current integrated circuit designs have evolved toward multi-metal interconnects. And ’in the multi-metal interconnect process, because

461843 V. Description of the invention (2) ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------———————————————————————————————————————————————————————————————————————————————————————————————————————————————————————————————————————————————————————————————————————————————————————————— 461843 V. Description of Invention In particular, the use of the _: technique can greatly improve the reliability and yield of integrated circuits ... In the embedded circuit, the 'tessellation process' has become the mainstream technology for making interconnects. In addition, as the accumulation of semiconductor components continues to increase, the use of gold! To make connection structures has also encountered many difficulties. Example # In high-temperature environments, aluminum atoms are prone to "spikes" between silicon substrates and lead to poor aluminum wire contact. In addition, as the size of aluminum wires continues to shrink, the aluminum atom movement caused by "electromigration" also easily shorts the aluminum connection structure. Therefore, in the current semiconductor industry, it is often tried to use conductivity A higher and lower resistivity copper metal to replace the traditionally used aluminum. Please refer to the first figure, this figure shows the relevant procedures for making copper mosaic structures on semiconductor substrates. A dielectric layer 12 is formed on 10 ', and then a number of contact hole patterns are formed in the dielectric layer 12 using a lithography process. Then, a copper layer 14 is deposited on the dielectric layer 12 and filled in the contact holes. Subsequently, , Remove a portion of the copper layer 14 on the upper surface of the dielectric layer 12 to form a copper inlay structure located in the contact hole _. In general, the engraving process or chemical mechanical polishing method (chemical mechanical P (〇li shi ng, CMP) to achieve the effect of removing part of the copper layer, but it is worth noting

Page 5 461843 V. Description of the invention (3) Means that 'when performing the last name engraving method' because of the use of high energy ion strikes', the copper damascene structure and the dielectric layer 12 are formed after the etching process is completed. The upper surface will not be able to meet the requirements of planarization. Therefore, in order to take into account the effect of comprehensive planarization 'and to ensure that the copper mosaic structure produced has a better surface shape, chemical mechanical polishing is often used to remove unwanted Copper layer. A typical chemical mechanical polishing device (CMP) is shown in the second figure. Among them, "on the upper surface of the polishing machine table 20" is provided a polishing pad 22 for performing a polishing process on the semiconductor substrate 10. The polishing pad 22 has a plurality of grooves 24 in addition to rough particles in order to increase the mechanical polishing effect. In this way, the slurry 28 'sprayed on the surface of the polishing pad 22 by the slurry supply device 26 can pass through these grooves 24 and be evenly distributed on the polishing surface 22. In addition, a handle 30 is used to adsorb the semiconductor substrate 10 'and place the dust on the surface of the polishing pad 22. At the beginning of the grinding process, the grinding machine 20 is rotated in one direction, and the handle 30 is also rotated in a certain direction to polish the surface of the semiconductor substrate 10. In addition, by spraying the slurry 28 as a chemical additive, the purpose of removing a part of the copper layer H on the semiconductor substrate 10 can be achieved by chemical reaction and mechanical grinding. However, it is worth noting that During the polishing of the copper layer 14, by-products such as copper oxide (CuOx) particles are often generated between the interface between the semiconductor substrate 10 and the copper layer 14. Moreover, these copper oxide particles are often buried in the trench 24 ', and in the subsequent polishing process, the semiconductor substrate 1 is caused.

461843 V. Description of the invention (4) ~ Defects such as scratches on the surface. In addition, when too many oxide steel particles are trapped in the groove 24, the rate of the grinding process will also be reduced, and the output β will be reduced. Therefore, after the grinding process is completed, deionized water is often used ( DI water) to perform a cleaning process on the polishing pad 22 and the semiconductor substrate 10 to wash away the remaining slurry and copper oxide particles. However, for copper oxide particles trapped in the trenches, using deionized water to perform the cleaning process often cannot be effectively removed. Therefore, in order to avoid the residual copper oxide particles, the surface of the semiconductor substrate that is subsequently ground will be scratched. 'Another cleaning machine (c 1 eaner) is required to perform a cleaning procedure on the polishing pad 22 in order to completely remove the copper oxide particles. except. But in this way, it often needs to add extra cleaning steps, which makes the whole process more complicated. Moreover, for the polished semiconductor substrate 10, the copper oxide particles adhering to the surface of the copper post-structural structure will also reduce its conductive properties. Therefore, after completing the CMP process, an additional removal process is also required to remove the copper oxide particles on the surface of the copper damascene structure. OBJECT AND SUMMARY OF THE INVENTION The main object of the present invention is to provide a method for simultaneously removing copper oxide particles on the surface of a semiconductor substrate and a polishing pad. Another object of the present invention is to provide a synchronous cleaning program for

Page 7 461843 Description of the invention (5) After the completion of the chemical mechanical polishing process, use the solvent of # 々μ 仏 15L M chemical solution to remove the grinding and copper oxide particles on the surface of the semiconductor substrate. . The present invention discloses a method for performing a chemical mechanical polishing process on a copper layer on a semiconductor substrate. First, a dielectric layer is formed on a semiconductor substrate, and the dielectric layer is etched to form an opening pattern therein. Then, deposit a copper layer on the dielectric layer and fill the opening pattern. A chemical mechanical polishing process is performed to remove a portion of the copper layer. The semiconductor substrate is pressed onto the polishing pad, and the slurry is sprayed on the polishing pad to increase the polishing effect. Then, the simultaneous cleaning process is performed to remove the copper oxide particles on the surface of the semiconductor substrate and the polishing pad simultaneously. The citric acid solution can be sprayed on the polishing pad, and the heavy chemical solution can dissolve the copper oxide particles while Remove the oxide steel particles on the surface of the semiconductor substrate and polishing pad. Detailed description of the invention: The present invention provides a new chemical-mechanical polishing procedure for removing copper oxide particles on the surface of a polishing pad and a semiconductor substrate at the same time in a procedure for manufacturing a copper embedded structure. Among them, after the polishing process is completed, the supply of the slurry is stopped 'and the citric acid solution is input to the polishing pad so as to dissolve the polishing pad and the copper oxide particles on the surface of the semiconductor substrate. In this way, it is possible to simultaneously achieve the effect of cleaning the polishing pad and the semiconductor substrate in the simultaneous cleaning process. A detailed description of the present invention is as follows.

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V. Description of the invention (6) Please refer to the third drawing 'to provide a < 100 > crystal substrate 40 first. · Generally speaking, other types of semiconductor materials, such as gallium arsenide, germaniuin, or silicon on insulator (SOI), can be used as semiconductor substrates. In addition, since the characteristics of the surface of the semiconductor substrate have no particular influence on the present invention, the crystal orientation can also be selected as <; 1 丨 〇 > or < 111>. A dielectric layer 42 is then formed on the semiconductor substrate 40 to produce an insulating effect. It should be explained here that before the dielectric layer 42 is formed, various active components, passive components, peripheral circuits and the like required for integrated circuits have been fabricated on the semiconductor substrate 40. In other words, on the surface of the semiconductor substrate 40, there are already various functional layers and material layers required. In a preferred embodiment, the dielectric layer 42 may be formed of silicon oxide or silicon nitride. For example, chemical vapor deposition (CVD) can be used to form tetraethyl silicate (TEOs) at a temperature of about 600 to 800-◦, and a pressure of about 0.1 to 101 rpm. Silicon oxide. Alternatively, silicon oxide can also be produced by thermal oxidation. As for silicon nitride, it can be formed in a furnace of about 400 to 450 C, and the reaction gases in the process are SiH4, N2O and NH3. In addition, 'tetraethyl silicate (TE0s) can also be used as a reaction material' and fluorine atoms are added 'to form a fluorosilicate glass (FSG) by chemical vapor deposition (LpcvD) as the above-mentioned dielectric layer 42 . Also, as the dielectric layer 42 described above, unused glass (USG) 'can be used. As for other low dielectric constant materials (low κ), the dielectric layer 42 may be formed here.

4-1843 V. Description of the invention (7) Then, an opening pattern 44 can be defined on the dielectric layer 42 by conventional lithography and etching techniques, so as to expose each material layer used to connect with the interconnect. Generally speaking, a photoresist is first formed on the dielectric layer 42 to define an opening pattern, and the photoresist is used as an etching mask power. Then, a lithography process is performed on the dielectric layer 42 and an opening pattern 44 is defined. among them. In the preferred embodiment ' plasma etching can be used to define the opening pattern 44. Among them, when the dielectric layer 42 is made of a silicon oxide material, cc12f2, CHF3 / cf ^, CHF3 / 〇2, CHgCHF2, CF4 / 〇2 can be selected. If the material of the dielectric layer 42 is made of silicon nitride ', CF4 / H2, CHF3, or CH3CHF2 can be selected. Still referring to the second figure, 'the barrier layer 46 is then formed on the sidewall and the bottom of the opening pattern 44 to prevent the copper layer and the dielectric layer 42 or other components from diffusing in the subsequent fabrication process', resulting in a spike effect. ). In a preferred embodiment, the material of the barrier layer 46 may be selected from Ta, TaN, or any combination thereof. In addition, the thickness of the preferred barrier layer a can be controlled between 100 and 800 angstroms. In general, nitridation can be used to form the desired nitride group layer. First, a low-level plating process is performed to deposit a tantalum layer on the sidewall and bottom surface of the opening 44, and then in a% or NH3 environment 'to form a tantalum nitride layer through high temperature processing. Alternatively, a reactive sputtering process may be used to form the tantalum nitride layer. The button metal is first bombarded with plasma ions, and argon and nitrogen are passed in, so that the group atoms spattered by the bombardment can react with the gas atoms formed by the dissociatiori reaction and form tantalum nitride It is deposited on the surface of the opening pattern 44.

Page 10 461843 V. Description of the invention (8) After the barrier layer 46 is formed, the semiconductor substrate 40 can be transferred to a cooling reaction chamber under a vacuum environment to perform a cooling process. After cooling the semiconductor substrate 40, a copper seed layer (Cu seeding) can be formed on the upper surface of the barrier layer 46. Among them, in a preferred embodiment, the steel seed layer 4 8 can be used well-known It is formed by a similar process such as physical vapor deposition (PVD), sputtering, and the like, and has a thickness of about 300 to 2000 angstroms. Next, the semiconductor substrate 40 may be immersed in a copper sulfate solution, and subjected to an electro chemical plating (ECP) reaction, thereby forming a copper layer 50 above the copper seed layer 48 and filling the opening pattern 44. In general, the copper seed layer 48 can be electrically connected to the cathode of a power source, and the copper ions in the copper sulfate solution can be reduced and deposited on the surface of the copper seed layer 48. That is, copper atoms can be deposited on the surface of the copper seed layer 48 through the electroplating process to form a desired copper layer. Then, as shown in the fifth figure, a chemical mechanical polishing (CMP) process may be performed on the semiconductor substrate 40 to remove a portion of the copper layer 50, the copper seed layer 48, and the barrier on the upper surface of the dielectric layer 42. Layer 46 and defines a copper damascene structure in the opening pattern 44. As described above, the semiconductor substrate 40 can be attracted from the back surface of the semiconductor substrate 40 using the grip 52 and pressed against the surface of the polishing pad 56 on the polishing machine table 54. During the CMP process, the slurry 60 sprayed from the slurry supply device 58 on the surface of the polishing pad 56 passes through the groove 62 on the surface of the polishing pad 56 and

Page 11 V. Description of the invention (9) Evenly distributed on the polishing pad 62. In this way, the purpose of removing part of the copper layer 50 can be achieved by the chemical action of the slurry and the mechanical action of the particles on the surface of the polishing pad 56. When the copper layer 50 is polished to a desired thickness, the supply of the slurry 60 may be stopped and the citric acid solution may be sprayed onto the surface of the polishing layer 56 so that the polishing pad 56 and the semiconductor substrate 4 are simultaneously 〇The copper oxide particles on the surface are dissolved. In a preferred embodiment, citric acid and deionized water with a concentration of 40% can be mixed at a ratio of 20: 1, and then sprayed onto the polishing pad 56 to perform a synchronous cleaning process. And after carrying out the cleaning procedure for about 1 to 30 seconds, the copper oxide particles can be dissolved and removed by the chemical reaction of citric acid and the copper oxide particles. In other words, 'After removing a portion of the copper layer 50, the copper seed layer 48, and the barrier layer 46 located on the upper surface of the dielectric layer 42,' and after completing the CMP process of the copper mosaic structure, the citric acid solution can be sprayed directly to On the polishing pad, the effect of cleaning the surface of the polishing pad 56 and the semiconductor substrate 40 is achieved in-situ. In this way, after the grinding process and the synchronous cleaning process are completed, the copper damascene structure 70 on the semiconductor substrate 40 in the sixth figure can be obtained. Among them, the copper damascene can be effectively removed due to the synchronous cleaning process described above. The copper oxide particles on the upper surface of the structure 70 need not to remove the copper oxide particles from the semiconductor substrate 40. At the same time, as for the polishing pad 56 on the polishing machine table 54, the copper oxide particles that may be buried in the groove 62 have been dissolved and removed using citric acid in the synchronous cleaning process.

Μ Page 12: 4 3 V. Description of the Invention (ίο) This does not require additional removal steps. Please refer to FIG. 7A, which shows the surface of the polishing pad after the chemical mechanical polishing process and the cleaning process in the conventional process. Among them, on the surface of the grinding pad 80, a dark shaded area 82 made of copper oxide particles can be clearly seen. Further, after the surface of the polishing pad 80 is enlarged, a dark shadow 86 composed of copper oxide particles can be clearly seen in the area 84. Therefore, an additional cleaning step is required for the polishing pad 80 to remove the copper oxide particles on the surface. In contrast, referring to Figure 7B, the surface of a polishing pad using a citric acid solution for a simultaneous cleaning process is shown. Among them, on the surface of the abrasive cymbal 80, a shadow area composed of copper oxide particles will not be seen. Even if a part of the surface of the polishing pad 80 is enlarged, as in the area 88, it is difficult to find the residual copper oxide particles. Similarly, please refer to FIG. 8A, which shows the surface of the semiconductor substrate after the chemical mechanical polishing process and the cleaning process in the conventional process. Among them, on the surface of the dense copper mosaic structure 90, a dark shadow composed of copper oxide particles is also generated. The relative 'refer to FIG. 8B, which shows the surface of a semiconductor substrate in which a citric acid solution is subjected to a simultaneous cleaning process. Since the copper oxide particles have been removed, there is no dark shadow in the eighth A picture on the surface of the copper mosaic structure 90 '. According to the synchronous cleaning program provided by the present invention, a citric acid solution is used to remove copper oxide particles located between the semiconductor substrate and the polishing pad.

Page 13 丨 84 3 V. Description of the invention (11) '' Dangdu's advantages. First, the copper oxide particles buried in the grooves of the polishing pad during the polishing process can be effectively removed in the synchronous cleaning process without the need to use another cleaning machine o 'after completing the entire chemical mechanical polishing process. The procedure β for removing copper oxide particles on the polishing pad is such that the copper oxide particles on the surface of the polishing pad can be immediately removed during each cleaning process of the polishing process, so that the successive polishing procedures can be maintained at It is carried out at a relatively stable grinding rate. In addition, because the oxide steel particles on the surface of the polishing pad can be effectively removed, when the next semiconductor substrate is replaced to perform the polishing process, the surface of the semiconductor substrate will not cause defects such as scratches. In this way, it will also help the copper mosaic structure to have a better surface morphology after the chemical mechanical polishing process is completed. ^ At the same time, during the above-mentioned simultaneous cleaning process, the copper oxide particles on the surface of the semiconductor substrate. Also dissolved by citric acid solution. Therefore, after the chemical mechanical polishing process is completed, there is no need to perform an additional cleaning step on the semiconductor substrate. ^ Although the present invention is illustrated above with a preferred example, it is not used for the spirit and the invention of the present invention, and only This embodiment is here. Changes made to those skilled in the art of the field without departing from the spirit and scope of the present invention should all be included in the scope of patent application described below. #

Page 14 · 61 Β 4 3 Schematic explanation --- By following the detailed description combined with the attached drawings, the above content and the many advantages of this invention can be easily made, among which: The surface view according to the traditional technology is shown Shows the steps for semiconductors; shows the semi-conducting substrate according to the technology of the present invention. The first half of the figure shows the wearing surface of a semiconductor wafer, and the step of depositing a copper layer on the substrate; the second figure shows the loading of a chemical mechanical polishing machine A grinding process is performed to produce a copper damascene structure. The third figure is a cross-sectional view of a semiconductor wafer, and the step of forming an opening pattern on a conductor substrate. The fourth figure is a cross-sectional view of a semiconductor wafer, showing a copper layer deposited on a semiconductor substrate according to the present invention. The fifth diagram is a cross-sectional view of a chemical mechanical polishing machine, showing the steps of the semiconductor substrate grinding process according to the present invention; ^ The sixth diagram is a cross-sectional view of a semiconductor wafer 'shows the fabrication of surface 1 embedded according to the present invention Steps for structuring on a semiconductor substrate; 'shows the comparison between the traditional method and the surface of the polishing pad. The seventh A and B are top views of the polishing pad. The method of the present invention After the cleaning process is performed, the eighth, eighth, and eighth figures A and B are top views of semiconductor wafers, showing the comparison between the conventional method f and the method of the present invention on the surface of the semiconductor substrate after the cleaning process.

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Claims (1)

461843 Six 'Scope of Patent Application 1. A method for performing a chemical mechanical polishing process on a copper layer on a semiconductor substrate' The method includes at least the following steps: providing a semiconductor substrate, wherein the upper surface of the semiconductor substrate has a copper layer; Performing a chemical mechanical polishing procedure to remove a portion of the copper layer, wherein the semiconductor substrate is pressed onto a polishing pad, and a slurry is sprayed on the polishing pad to increase the polishing effect; and the supply of the researcher is stopped, and Spray the citric acid solution on the polishing pad to perform a simultaneous cleaning process, and simultaneously remove the semiconductor substrate and copper oxide particles on the surface of the polishing pad. Fan Li Li please refer to the table 2. The material layer on the material layer includes the bottom material guide material half or the layer's performance in the energy, the ^ 1 method of each item of the ^ 1 method 3. If the scope of patent application 笫! @ ^ ^ ^ Can be used to generate chemical methods with the copper oxide particles, the citric acid hydrolysis reaction described above, and the copper oxide particles are dissolved 4. If the scope of the patent application is washed, the process time is about 1 to 30 seconds. Method, in which the above-mentioned simultaneous cleaning 5 · The first solution of the Shenyang Patent Fanyuan solution is a method using a 40% concentration of Songsong term 'Qi Yin above citrate and deionized water, in a ratio of 20: 1 Page 16 461843 VI. Scope of Patent Application Blended. 6. The method according to item 1 of the patent application range, wherein the above-mentioned grinding procedure can remove a part of the copper layer, and a copper mosaic structure is fabricated on the semiconductor substrate. The sequence of square-ik sinks into the bottom of the conductor in order to promote the pad surface and a method of chemical mechanical polishing of a steel layer on the semiconductor substrate by means of a semiconductor. The method includes at least the following steps: forming a dielectric layer on the semiconductor substrate; Engraving the dielectric layer to form an opening pattern; depositing a copper layer on the dielectric layer and filling the opening pattern; performing a chemical mechanical polishing process to remove a portion of the copper layer, wherein the half material is pressed into place On the polishing pad, and spray the slurry on the second polishing pad, add the polishing effect; and = step the cleaning process while removing the semiconductor substrate and the polishing ::: copper particles, in which a chemical solvent is sprayed on the polishing pad, The solvent dissolves the copper oxide particles, and at the same time, the substrate and the copper oxide particles on the surface of the abrasive grate are removed. 8. If the patent application scope is 7th, the + layer before the semiconductor substrate, further includes / the step of forming the dielectric substrate on the semiconductor substrate includes forming various elements or material layers in 9. As in Please apply for the method in the scope of patent No. 7, in which the above-mentioned chemical solution is 461843. 6. The agent in the scope of patent application is the citric acid solution. 10) For the method in scope of patent application No. 7, in which the above-mentioned synchronization &time; 1 to 30 seconds. … 11. The method according to the item No. 丨 0 of the patent application, wherein the citric acid solution is a mixture of citric acid and deionized water with a concentration of 40% in a ratio of 20.1. · 12. The method according to claim 7 of the patent scope, wherein the above-mentioned chemical = grinding process can remove a part of the copper layer, and define a copper mosaic structure on the semiconductor substrate. ~ 13. If the method of claim 7 is claimed, before the above procedure for depositing the copper layer, the method further includes the following steps: depositing a barrier layer on the surface of the opening pattern; and depositing a copper seed layer on the resist Barrier surface. 14. The method according to item 13 of the patent application range, wherein the above barrier layer can be selected from buttons (Ta), lithium nitride (TaN), or any combination thereof. 15 · The method according to item 13 of the scope of patent application, wherein the above-mentioned copper layer can be deposited using chemistry, method, etc., wherein the semiconductor substrate is immersed in sulfuric acid / valley, and the copper seed layer is Electrically connected to the cathode lead to Page 18 Λ613 6. Scope of patent application The copper ions in the copper sulfate solution can be reduced and deposited on the surface of the copper seed layer. 1 · ^ p. 19