^¾部中呔"'^'^m-消於合竹杉印t 410502 A7 --------- B7 五、發明説明（1 ) 本發明係有關一種I/O保護裝置，特別有關於—種 用於防止靜電或多電壓電源（dual power supply)中之高虔 損傷的I/O保護裝置及其結構（I/O protection device)。 在積體電路（ICs)的應用上，高電壓自晶片之輸出/ 入墊（I/O pad)侵入而造成内部電路損傷，一直是亟待改 善的課題。尤其在進入極大型積體電路（ULSI)世代以 後’例如使用0.25μηι以下之深次微米製程所形成的半導 體裝置’如CMOS ICs，其薄閘極氧化層（thin gate oxide) 之運用衰減了電晶體之抗高壓能力，且影響其可靠度問 題。 此外，由於目前超大型（VLSI)或極大型（ULSI)積體 電路晶片之工作電壓因隨著半導體製造技術的進步及節 ” 約能源之要求’而有逐漸降低之趨勢，因此以前僅用於 單一電壓源系統（single voltage system)之晶片設計並不適 合’而在各數位電子元件間產生不同電位階之介面電壓 也難以避免。再者’混合電壓也被應用到許多的電路型 態中’其特徵疋於不同的電路方塊（sections of the circuit) 中使用不同的工作電壓，例如類比-邏輯混合電路之特用 IC(ASIC : application specific integrated circuit)的 I/O 電 路和核心邏輯電路（core logic)，或者是嵌入式動態隨機 存取記憶體（embedded DRAM)等。 若以目前產品規格為例’典型常見於數位電子系統 中之工作電壓為5伏特，但由於降低工作電壓可減少電 力消耗及提昇性能，因此，目前市場上已同時有採用33 3 本紙ft尺纟ii則1關家料（CNS ) Λ4規格（2]GX 297公楚)^ ~ -----1L__l·~______丁______友 1 (誚先閲讀背面之注意事項再填'"?本頁) 410502 A7 _________________ _B7 五、發明説明（2 ) ~ 伏特及2.5伏特（甚或丨.8伏特）工作電壓之電子元件出 現。 例如第1圖所示之電腦系統中，此裝置電路4〇包 括内部電路如核心邏輯44(Core i〇gic)及複數個1/〇電 路I/O電路一般由輸出/入塾（I/O pad)和I/O緩衝串（i/Q buffers)組成，核心邏輯44則需透過I/C)電路來與外部電 路耦接（coupling)，但該些外部電路則各自具有相對應的 工作電壓，諸如，工作電壓2·5伏特之微處理器 (CPU)10，工作電壓3.3伏特之靜態隨機存取記憶體 (SRAM)20，或者工作電壓5伏特之動態隨機存取記憶體 (DRAM)30 ’其均可透過I/O墊12、22、32和I/O緩衝串 14、24、34來輕接至内部電路44。 其中依據傳統製程’薄閘極氧化層抗高壓能力不 足’谷易損傷’而厚閘極氧化層則會造成電晶體之性能 (performance)不佳’因此’目前常用之作法是令上述1/〇 緩衝串透過不同厚度之閘極氧化層，來匹配不同位階之 工作電壓’亦即使各閘極結構具有不同之閘極導通電 壓。 如第2圖所示’該閘極結構係在基底ι〇〇表面形成 有3V、5V之電晶體i6a、16b，場氧化層11〇則用以隔 離出主動區’其次，不同厚度之閘極氧化層16〇a'16〇b 及複晶矽層180則分別形成於該主動區表面，其中，薄 閘極氧化層16〇a厚度約為70人，因此電晶體16a可在 3.3伏特之工作電壓下操作（導通），厚閘極氧化層16〇b 4 本紙張尺度追川中國國家標準（〇^〉八4現格（2】〇'乂297公釐） (誚先閱讀背面之注意事項再硪T本S ) '^ ¾ 部 中 呔 " '^' ^ m-Yu Yuzhu Shan Yin t 410502 A7 --------- B7 V. Description of the invention (1) The present invention relates to an I / O protection device, It is particularly related to an I / O protection device and its structure (I / O protection device) for preventing high damage in static electricity or dual power supply. In the application of integrated circuits (ICs), high-voltage invasion from the chip's output / input pads (I / O pads) causes damage to internal circuits, which has been an urgent problem to be improved. Especially after entering the ultra large-scale integrated circuit (ULSI) generation, 'for example, semiconductor devices formed using deep sub-micron processes below 0.25 μm', such as CMOS ICs, the use of thin gate oxides has attenuated electrical The high voltage resistance of the crystal affects its reliability. In addition, because the current operating voltage of very large (VLSI) or very large (ULSI) integrated circuit chips is gradually decreasing due to the advancement of semiconductor manufacturing technology and saving energy requirements, it was previously only used for The chip design of a single voltage system is not suitable ', and it is difficult to avoid the generation of interface voltages with different potential levels between various digital electronic components. Furthermore,' hybrid voltage is also applied to many circuit types' Features: Different working voltages are used in different sections of the circuit, such as I / O circuits and core logic circuits (ASIC: application specific integrated circuit) of analog-logic hybrid circuits. ), Or embedded dynamic random access memory (embedded DRAM), etc. If the current product specifications are taken as an example, the typical common operating voltage in digital electronic systems is 5 volts, but the power consumption can be reduced due to lower operating voltage and Improved performance, therefore, 33 3 paper ft 纟 纟 ii and 1 home material (CNS ) Λ4 specifications (2) GX 297 public Chu) ^ ~ ----- 1L__l · ~ ______ 丁 ______you 1 (诮 Please read the precautions on the back before filling in '"? This page) 410502 A7 _________________ _B7 V. Description of the invention (2) ~ Electronic components with working voltage of 2.5 volts and 2.5 volts (or even .8 volts) appear. For example, in the computer system shown in Figure 1, the device circuit 40 includes internal circuits such as core logic 44 ( Core i〇gic) and a plurality of 1 / 〇 circuits I / O circuits generally consist of output / input pads (I / O pads) and I / O buffer strings (i / Q buffers). The core logic 44 needs to pass I / C ) Circuits are coupling with external circuits, but these external circuits each have a corresponding working voltage, such as a microprocessor (CPU) 10 with a working voltage of 2.5 volts, and a static random working voltage of 3.3 volts. Access memory (SRAM) 20, or dynamic random access memory (DRAM) 30 with an operating voltage of 5 volts, which can be passed through I / O pads 12, 22, 32 and I / O buffer strings 14, 24, 34 To lightly connect to the internal circuit 44. Among them, according to the traditional process, the thin gate oxide layer has insufficient high-voltage resistance and the valley is easily damaged, while the thick gate oxide layer Will cause poor performance of the transistor '. Therefore,' the current common practice is to pass the 1/0 buffer string through the gate oxide layer of different thickness to match the working voltage of different levels', even if the gate structure Has different gate-on voltages. As shown in Figure 2, 'The gate structure is formed with 3V and 5V transistors i6a, 16b on the surface of the substrate ι〇, and the field oxide layer 11 is used to isolate the active area.' Second, gates of different thicknesses An oxide layer 16a'16b and a polycrystalline silicon layer 180 are respectively formed on the surface of the active region. The thickness of the thin gate oxide layer 16a is about 70 people, so the transistor 16a can work at 3.3 volts. Operating under voltage (conduction), thick gate oxide layer 16〇b 4 This paper scale follows the Chinese national standard (〇 ^〉 八 4 格 (2) 〇 '乂 297mm) (诮 Read the precautions on the back before reading硪 T Ben S) '
'1T -線丨. ' —— 1 —— 410502 A7 _ B7 五'發明説明（3) 厚度約為100 A，因此電晶體16b可在5伏特之工作電壓 下操作（導通）。 然而’由於傳統方法係依據不同位階之工作電壓來 調整其所對應之閘極導通電壓，因此在製程上，必須沈 積不同厚度之閘極氧化層以形成不同之閘極導通電壓， 因此不僅無法與内部電路形成相同厚度之閘極氧化層， 且在製程上十分困難及複雜，再者於製程中形成不同厚 度之閘極氧化層極易產生缺陷，因此可靠度亦不佳。 有鑑於此，本發明之目的即在於對出現在1/〇墊之 過高電壓，利用耦合電容進行分壓，以於輸出緩衝器之 輸入端形成一耦合信號，降低跨閘極氧化層之電壓差， 避免損傷。其中耦合電容可為一堆疊電容結構，以相容 於現有半導體製程。 本發明之另一目的在於，利用控制反閘輸出一隔離 控制信號，使前級緩衝器之輸出端與接地節點隔離，由'1T-line 丨.' —— 1 —— 410502 A7 _ B7 Five 'Description of the invention (3) The thickness is about 100 A, so the transistor 16b can be operated (conducted) at a working voltage of 5 volts. However, since the traditional method is to adjust the corresponding gate conduction voltage according to the working voltage of different levels, in the process, it is necessary to deposit gate oxide layers of different thicknesses to form different gate conduction voltages. The gate oxide layer of the same thickness is formed in the internal circuit, and it is very difficult and complicated in the manufacturing process. Furthermore, the formation of the gate oxide layer of different thickness in the manufacturing process is prone to defects, so the reliability is not good. In view of this, the purpose of the present invention is to divide the excessive voltage appearing on the 1/0 pad by using a coupling capacitor to divide the voltage to form a coupling signal at the input end of the output buffer and reduce the voltage across the gate oxide layer. Poor, avoid damage. The coupling capacitor can be a stacked capacitor structure to be compatible with the existing semiconductor processes. Another object of the present invention is to use the control back gate to output an isolation control signal to isolate the output end of the front stage buffer from the ground node.
於其與輸出緩衝器之輸入端耦接，因此可持續維持此耦 合信號值’以保護I/O電路D 為達成上述目的，本發明提供一種1/〇保護裝置， 其包括·-輸出緩衝器：一耦合電容，耦接該輸出緩衝 器之輸出端至其輸入端，以於該輸出緩衝器之輸出端出 現-既定電位信號時’在其輸入端形成一耦合信號；一 控制反閘，其耦接該輸出緩衝器之輸入端，用以當該耦 合信號達到一第一電壓值時，輸出—隔離控制信號，且 當該耦合信號在一第二電壓值以下時，輸出—正常控制 5 ^尺度^^^酬家料1^)人4祕（210\ 297公楚> ~--- I I K n--- I ^I «^1 1 I H ------- T---1 1 -I - - - ^ H V Ί Λ J I (請^閱讀背面之注意事項再"'寫本頁) 五 410502 A7 B7 發明説明（4)~—~~~~ ———— 波’及—前級緩衝5!，贫私± 輸入娃 °其輸出端耦接該輪出緩衝器之 /V嘴，且争且士_ 出，用以Α & Γ ~工制端，其耦接該控制反閘之輸 衝器之」收者為該隔離控制信號時，使該前級緩 =輸出端與接地隔離，且當所接收者為該正常控制 1°唬時，使該前級緩衝器正常操作。 為讓本發明之上述和其他目的 明顯易懂，下文特舉—較佳實施例 作詳細說明如下： 圖式之簡單說明： 第1圖係 '顯示-傳統邏輯電路與具不同工作電壓之 外部電路耦接之方塊示意圖。 第2圖係顯示—依據傳統製程形成不同閘極氧化層 厚度之半導體剖面圖。 曰 苐3圖係顯示傳統I/O電路之輸出緩衝串。 第4圖係顯示本發明之1/〇保護裝置之實施例。 第5圖係顯示第4圖1/〇保護裝置之耦合電容部 特徵、和優點能更 並配合所附圖式， 份 份 份 份 第6圖係顯示第4圖1/〇保護裝置之控制反閘部 第7圖係顯示第6圖1/0保護裝置之控制反閉部 其轉換特性曲線圖。 第8圖係顯示第4圖1/◦保護裝置之耦合電容部 其半導體結構剖面圖。 符號說明 本纸讯尺度这圯屮國國家標挲（CNS ) A4規格（210X 297公釐） ------：------"-- — II--訂— II 線 1 1 、 (誚先閱讀背面之注意事項再楨g本H j ，、* 部 屮 λ il .τ ΐίί t： 厶 ϊ\ 卬 r A7 B7 五、發明説明（5 ) —~— 1〇、2〇、30〜外部電路；12 ' 22、32〜1/0 墊；14、 24、34〜1/〇緩衝串；40〜核心邏輯；44〜内部電路；16a、 _〜電晶體·’ 100〜矽基底；"Ο〜場氧化層；130、140〜複 晶石夕層n160b〜閘極氧化層：3ι〇、4ΐ〇〜前級緩衝 器，330 430〜輸出緩衝器；INV1〜控制反閘；Cc~耦合 電合，450〜I/O塾；8〇〇〜石夕基底；81〇〜淺溝槽氧化層； 830〜源/汲極：85〇〜閘極；87〇〜複晶矽層。 實施例 為明顯區別本發明之實施例與傳統技術之差異，越 刀別說月第3圖傳統輸出緩衝_與第4圖之卯保護裝 置電路圖，以進行比較。 首先請參閱第3圖，在1/0電路中，傳統輸出緩锋 串係由一輸出緩衝器（output buffer)330及一與之串接之 前級緩衝器310組成（但不限於一級），兩者屬於CM〇f 結構’刖級緩衝器310包括串聯之PM〇s電晶體M7和 NMOS電晶體M5，PM〇s電晶體M7耦接系統供應電壓 VDD’而NM0S電晶體MS則耦接接地節點vss，同 理，緩衝器330包括串聯之PM〇s電晶體M2和NM〇s 電晶體Ml ’ PM0S電晶體M2耦接系統供應電壓VDD , 而NMOS電晶體]Vi 1則耦接接地節點VSS。 般而έ ’在輸出模式（outpUt mode)下，由内部電 路提供之號’係符合規格電壓之額定值範圍，例如 2.5V，因此，緩衝器31〇、33〇可正常操作，亦即當内部 電路提供信號V7至前級緩衝器310之閘極輸入端A7 本紙张尺廋述川中國國家標率（CNS ) Λ4规格（厂0><297公釐） ----------ί 於------訂------^ I r~ (誚先閱讀背面之注意事項再填艿本頁) A7 B7 410502 ------------- -----_ 五、發明説明（6 330 ’二由輸出端輸出其結果V2至下-級之輸出緩衝器 了後再由輸出緩衝器330進行輸出。 ° 而有時在輸出緩衝器330之輸出端A1會出 局電壓信號’例如高靜電電壓（ESD)，或者另—外部電路 於=出-既定電位信號VDDH以作為其他具有較高電壓 額定^之輸出緩衝器（未顯示）的輸入時，此既定電位信 號之高電壓值如VDDH=5V將同時出現在輸出緩衝器 33〇之輸出端A1，此時，電晶體M1之跨問極和接地節 點VSS之閘極氧化層便極易為此高電壓損傷。 反之，請參閱第4圖，其顯示本發明1/〇保護裝置 之實施例，其中為方便說明起見’與第3圖有相同之編 號者，代表相同之元件，於後不擬贅述。 按第4圖，本實施例主要係包括一輸出緩衝器 430 ’而耦合電容Cc則耦接輸出緩衝器430之輸出端A1 至其輸入端A2’用以在發生第3圖所示之情形時如於 輸出緩衝器430之輸出端A1出現一既定電位信號V1 時，能在其輸入端A2形成一耦合信號V2。 此外，實施例亦提供一控制反閘INV1，其糕接前 述輸出緩衝器430之輸入端A2，用以當耦合信號v2達 到一第一電壓值（0·5 VDDH)時’輸出一隔離控制信號 L’且當耦合信號V2在一第二電壓值（0.5VDDL)以下 時，輸出一正常控制信號Η。 又I/O保護裝置另包括多個串接之前級緩衝器，其 中在此係顯示最後一級前級緩衝器410。前級緩衝器41 〇 本紙张尺度述/1】中國國家標®M CNS ) Α4規格（210Χ 297公楚） (誚先閱讀背面之注意事項再填寫本頁) ，1Τ -峻！ 好浐部 tA«.M'-^,-;i1-消於合卬 410508 A7 --------------------- ---Η / 五、發明説明（7 ) ' A2’立：出端A5 ,其耦接輸出緩衝器430之輸入端 、'、有控制端A6 ’其耦接於控制反閘INv丨之 輪出A3用以當所接收者為隔離控制信號 緩衝器410之輪屮轳Ac t 文引规 去h〜輸 與接地VSS隔離，且當所接收 吊1制仏號Η時，使前級緩衝器41〇正常操作。 舉例而。，在1/0電路中，有時於輸出緩衝器430 之輸出端A1會出現高電壓信號，例如在具有較高操作 $壓VDDH或具有較低操作電壓vddl之外部電路中， :其以正電位輸出信號來作為其他具有輸出緩衝器(未顯 τ)的輪人時’此既定正電位信號之電壓值如（VDDH=5V， VDDL 2.5V)亦會出現在1/〇塾45〇處亦即輸出緩衝器 430之輸出端A1所出現之既定電位信號VI，有可能是 ，出0緩衝器430可承受之較低操作電歷VDDL，也有可 月匕疋輸出緩衝器430所無法承受之較高操作電壓 VDDH。 基於前述，請配合第4圖並參閱第5圖，由於實施 灼中係使耦合電容Cc耦接輸出緩衝器43〇之輸出端 A1(電晶體M1之沒極）至其輸入端A2(電晶體Ml之閘 極）如第5圖之等效電路所示，此時耦合電容係跨 越及極輸出# A1及開極輸入端A2，而電晶體M1之開 極電谷Cg則跨越閘極輪入端A2及接地節 點VSS，如此 閘極輪入端A2將形成一耦合信號V2，依據I/O墊-A1-Cc-A2-Cg-VSS形成之串聯線路可知，耦合信號V2為輸 出端A1之既定電位信號乂丨之分壓，因此，若藉由調整 9 本紙乐尺度种關家料（⑽）A<J規格（2】Gx 297公楚） I-^-----l·--ί 於------訂------4 — (誚先閱讀背面之注意事項再蛾寫本頁) 410502 A7 B7 五、發明説明（8 ) — — _容Cc之適當值’例如令電容量Cc=Cg，則將使耦 合信號V2=G.5V1，亦即跨閉極電容Cg之開極氧化層之 壓差W)，*跨麵合電容Cc之層間絕緣層 (V1-V2)，其電位範圍均祜 ^ 礼囷巧被限鈿至（〇 5 VDDL〜〇 5 VDDH)，因此不易因緩衝器43〇輸出端νι之高電壓而 損傷。 睛參閱第8圖，其顯示耦合電容Cc之―實施例 中，部份半導體結構剖面圖。此耦合電容主要係建立在 電晶體Ml之閘極上，亦即在一具有源/沒極83〇之基底 800上，其以淺溝槽隔離結構81〇予以隔離，並依序形 成一閘極絕緣層890及一閘極導電層85〇，其構成電晶 體Ml，接著形成一堆#結構，其至少包括一層間絕緣層 860及一第二導電層87〇，其形成於閘極導電層8兄表 面，且堆疊結構係依據閘極導電層85〇和第二導電層 870所佔面積及其重疊感應面積，來決定耦合電容值a 和閘極電容值Cg。 舉例而言，一矽基底800分別具有淡摻雜結構之源 極和汲極830，其中汲極耦接I/C)墊45〇，作為輸出緩衝 器430之汲極輸出端A1。閘極氧化層89〇形成於矽基底 800表面，複晶矽層85〇形成於閘極氧化層89〇表面， 其作為輸出緩衝器430之閛極輸入端A2。此外形成之堆 養結構’在此以一層為例’包括一層間絕緣層86〇及一 複晶碎層870,其形成於閘極複晶矽層860表面，前述 結構並於側壁形成絕緣間隙壁880。 本紙張尺度^用中囤國家棉準（CNS )八4規掊（2|〇χ297公釐> ------r--ίA------訂------味 1 ("先閲讀背面之注意事項再蜞巧本頁} 410502 Λ7 ______________________________ B7 五、發明说明（9 ) — 如此所形成之跨層間絕緣層860之耦合電容Cc及 跨閘極絕緣層之閉極電容Cg，係依據複晶石夕層㈣及複 晶矽層870所佔面積和其重疊感應面積，來調整耦合電 容Cc及閘極電容Cg之值，例如使Ce=Cg，則跨層間絕 緣層860之壓差和跨閘極氧化層89〇之壓差均約等於 0.5V卜進而兩者皆不易造成損傷，纟+ V1包括具不同 幅度之屬邏輯1位階之電位電壓VDDH和VDDL，如5 V 和 2.5V。 然而，在緩衝器430輸出端A1出現V1之高電壓如 VDDH期間，緩衝器430輸入端（M1電晶體閘極端）八2之 耦合信號V2必須足以維持一段時間，否則一旦循放電 路徑而自接地節點放電，則跨耦合電容Cc及跨閘極電容 _ Cg之電壓差將恢復為VDDH，若因此使隔離之絕緣層遭 致破壞’輸出緩衝器430亦將失去功能。 因此，基於前述，請配合第4圖並參閱第6圖及第 7圖’為持續維持緩衝器43〇輸入端（Μι電晶體閘極 端）A2之耗合信號V2，如第4圖所示，本實施例在前級 緩衝器410增加一控制電晶體如nm〇S電晶體M6及其 控制閘極端A6，而第6圖則提供一控制反閘iNV丨，其 由耦接接地節點VSS之NMOS電晶體M3和耦接系統電 源VDD之PMOS電晶體M4串聯形成，其中，電晶體 M3、M4之閘極共接至緩衝器43〇輸入端即mi電晶體 閘極端A2，且串聯之汲極輸出端A3耦接至前級缓衝器 410中控制電晶體M6之撩制閘極端A6。 11 尺度屮囤國家榇卑（CNS ) A4規格（210X297公釐） --：-----K---uli 表------^-------Λ (誚先閱讀背面之注意事項再蛾*?本1 ) 410502 A7 B7 ----- —— --------—.—--------- —— ---- -___... _ — 五、發明説明（10) 此外，參照第7圖，控制反閘INV1所欲形成之輪 入（A2)/輸出（A3)的關係如表1所示，其中藉由調蚊 PMOS電晶體M4和NMOS電晶體M3之特性曲線，可形 成一具高邏輯轉換電壓值Vtl之控制反閘INV1 ,如利用 一道離子植入步驟如植入氟化硼離子（BF2)，來提高控制 反閘INV1之NMOS電晶體M3之起始電壓值Vt，如使 Vt(M3)=0.5VDDL’以將控制反閘INV1之邏輯轉換電壓 Vtl控制在0.5VDDL與0.5VDDH之間，至於邏輯轉換電 壓Vtl與0.5VDDL、0.5VDDH之轉換區間（A，B)，較佳者 是選擇 0.05V<A<2V ; 〇.〇5V<B<2V。 {誚先閱讀背而之注意事喟再"':':"本頁) 表1 控制反閘INV1 (邏葬 F轉換電壓值Vtl) 輸入端A2 輸出端A3 0.5VDDL 邏輯1電位：H(hi£h) 0.5VDDH 邏輯〇電位：Ulow) -訂 -__ 因此當耦合信號V2為一較高電壓值時，如 0.5VDDH，貝，！可使控制反閘INV1之電晶體M3導通，因 而輸出一邏輯0之低電位信號（L)，並以之作為隔離控制 仏號’且當柄合信號V2為一較低電壓值時，如 (K5VDDL ’則可使控制反閘INV1之電晶體M3關閉，因 而輸出一邏輯1之高電位信號（H)，並以之作為正常控制 信號。 至於前級缓衝器410與控制反閘INV1之操作關係 則如第4圖所示’前級緩衝器41〇包括一耦接接地節點 12 本紙张尺廋这用1hf國家標卑（CNS ) A4規格（210X297公藶） 410502 A7 _______B7 五、發明说明（11) (詡先閱讀背面之注意事項再填艿本萸) VSS之NMOS電晶體M5和一耦接系統電源VDD之 PMOS電晶體M7，電晶體M5、M7之閘極共接形成一輸 入端A7’在輸出模式下’其接收來自内部電路之信號， 以將之傳送到輸出緩衝器430 ’而控制pm〇S電晶體M6 則分別串接於NMOS電晶體M5和PMOS電晶體M7 間。 在前級緩衝器410中’電晶體M6、M7之汲極共接 形成一輸出端A5’其耦接輸出緩衝器430之輸入端 A2，此外電晶體M6具有一控制閘極端A6，其耦接於控 制反閘INV1之輪出端A3。 因此，當輸出緩衝器430之輸出端A1出現一既定 電位“號VI時，透過麵合電容Cc之分壓，輸出緩衝器 430之輸入端A2形成一約為〇,5V1之輕合信號V2，當 輕合^破V2為〇.5VDDH(大於控制反閘invi之邏輯轉 換電壓VU)時，控制反閘INV1輸出低電位之隔離控制 信號L，並由電晶體M6之控制閘極端A6接收，使電晶 體M6關閉，結果前級緩衝器41〇之輸出端八5與接地節 點VSS隔離。 反之’當叙合信號V2為〇.5VDDL(小於控制反閘 INV1之邏輯轉換電壓Vtl)時，控制反閉mvi輪出高電 位之正常控制信號Η，並由電晶體M6之控制閘極端a6 接收，使電晶體M6導通’因此在輸出模式（〇utput m〇de) 下，前級緩衝器410之輸入（A7)/輸出（A5)可依電晶體 M5、M7正常操作。 13 本紙掁尺度適扣中國囤家標隼（CNS ) A4規格（210X297公釐〉 A7 410502 B7 ,-v _ — —--.-.— - 五、發明説明（12) 另外’依據第7圖’如果出現在輸出緩衝器43〇之 輸出端A1之既定電位信號V1，係屬於低電位信號如邏 輯0 k號或接地信號等小於0.5VDDL值者，則由於控制 反閘INV1之電晶體M3保持關閉狀態，因此控制反閘 INV1輸出高電位之正常控制信號H ,使電晶體M6導 通’前級緩衝器410處於正常操作狀態。 綜合上述’本發明之實施例對於出現在1/〇墊之過 高電壓，係利用耦合電容進行分壓，並由控制反閘輸出 隔離控制信號，使前級緩衝器之輸出端與接地節點隔 離，由於前級緩衝器之輸出端與輸出緩衝器之輸入端耦 接，因此可持續維持此分壓值’降低耗合電容和閘極電 谷之壓差’達到防止I/O電路之靜電或多電壓電源中之 高壓損傷。此外’耦合電容可為一堆疊電容結構，如此 可相容於現有步驟，避免傳統複雜之半導體製程。 雖然本發明已以一較佳實施例揭露如下，然其並非 用以限定本發明’任何熟習此技藝者，在不脫離本發明 之精神和範圍内’當可做些許之更動與潤飾，因此本發 明之保護範圍當視後附之申請專利範圍所界定者為準。 14 本紙张尺度適川中國國家標芈（（：]^)八4規格（2】0：< 297公釐） (誚先閱讀背而之注意事項再頊寫本頁}Because it is coupled to the input end of the output buffer, the coupling signal value is continuously maintained to protect the I / O circuit D. In order to achieve the above object, the present invention provides a 1/0 protection device, which includes a-output buffer : A coupling capacitor is coupled to the output end of the output buffer to its input end, so that when a predetermined potential signal appears at the output end of the output buffer, a coupling signal is formed at its input end; a control reverse brake, which The input end of the output buffer is coupled to output-isolate the control signal when the coupling signal reaches a first voltage value, and output-normal control when the coupling signal is below a second voltage value. 5 ^ Scale ^^^ Reward Family Materials 1 ^) Person 4 Secret (210 \ 297 Gongchu > ~ --- IIK n --- I ^ I «^ 1 1 IH ------- T --- 1 1 -I---^ HV Ί Λ JI (please ^ read the notes on the back again " 'write this page') 5 410502 A7 B7 Description of Invention (4) ~ —— ~~~~ ———— Wave 'and — The front stage buffer is 5 !, and the input voltage is poor. The output terminal is coupled to the / V mouth of the wheel-out buffer, and it is used for Α & Γ ~ When the “receiver” of the control reverse brake input is the isolated control signal, make the front stage slow = the output terminal is isolated from ground, and when the receiver is 1 ° for the normal control, make the front stage buffer In order to make the above and other objects of the present invention obvious and easy to understand, the following is enumerated-the preferred embodiment is described in detail as follows: Brief description of the diagram: Figure 1 shows the display-traditional logic circuit with different work Block diagram of voltage external circuit coupling. Figure 2 shows the cross-section of a semiconductor with different gate oxide layer thicknesses according to the traditional process. Figure 3 shows the output buffer string of a traditional I / O circuit. Figure 4 Fig. 5 shows an embodiment of the 1/0 protection device of the present invention. Fig. 5 shows the characteristics and advantages of the coupling capacitor portion of the 1/0 protection device of Fig. 4 and can be further matched with the attached drawings. The diagram is shown in Fig. 4 of the 1/0 control device of the protection device. The 7th diagram is shown in Fig. 6 of the 1/0 control device of the control device. ◦Semiconductor junction of the coupling capacitor of the protection device Cross-section diagram. Symbols indicate the national standard of this paper (CNS) A4 specification (210X 297 mm). ------: ------ "-— II--Order— II line 1 1 ((Read the precautions on the back before reading the book H j), * 屮 λ il .τ ίίί t: 厶 ϊ \ 卬 r A7 B7 V. Description of the invention (5) — ~ — 1〇 , 20, 30 ~ external circuits; 12 '22, 32 ~ 1/0 pads; 14, 24, 34 ~ 1/0 buffer strings; 40 ~ core logic; 44 ~ internal circuits; 16a, _ ~ transistor ·' 100 ~ silicon substrate; " 0 ~ field oxide layer; 130, 140 ~ polycrystalline stone layer n160b ~ gate oxide layer: 3ι, 4〇〇 ~ previous buffer, 330 430 ~ output buffer; INV1 ~ control Anti-gate; Cc ~ Coupling, 450 ~ I / O 塾; 800 ~ Shi Xi substrate; 81 ~ Shallow trench oxide layer; 830 ~ Source / drain: 85 ~~ gate; 87 ~~ Crystal silicon layer. Example In order to clearly distinguish the difference between the embodiment of the present invention and the conventional technology, let's not talk about the traditional output buffer in Figure 3 and the circuit diagram of the protection device in Figure 4 for comparison. First, please refer to FIG. 3. In the 1/0 circuit, the traditional output buffer series is composed of an output buffer 330 and a previous-stage buffer 310 (but not limited to one stage). It belongs to the CM0f structure. The "level buffer 310" includes a PM0s transistor M7 and an NMOS transistor M5 connected in series. The PM0s transistor M7 is coupled to the system supply voltage VDD 'and the NM0S transistor MS is coupled to a ground node. vss. Similarly, the buffer 330 includes a PMMOS transistor M2 and a NMOS transistor M1 ′ PM0S transistor M2 connected in series to the system supply voltage VDD, and the NMOS transistor V1 is coupled to the ground node VSS. Generally, in the output mode (outpUt mode), the number provided by the internal circuit is in accordance with the rated value range of the voltage, such as 2.5V. Therefore, the buffers 31 and 33 can operate normally, that is, when The internal circuit provides a signal V7 to the gate input terminal A7 of the front stage buffer 310. This paper ruler describes the China National Standard (CNS) Λ4 specification (factory 0 > < 297 mm) -------- --ί From ------ Order ------ ^ I r ~ (诮 Read the notes on the back before filling this page) A7 B7 410502 ------------ ------_ 5. Description of the invention (6 330 '2 The output is output by the output terminal V2 to the lower-level output buffer and then output by the output buffer 330. ° Sometimes the output buffer The output terminal A1 of 330 will output a voltage signal such as a high electrostatic voltage (ESD), or another external circuit at = output-a predetermined potential signal VDDH as the input of other output buffers (not shown) with a higher voltage rating ^ At this time, the high voltage value of the predetermined potential signal such as VDDH = 5V will appear at the output terminal A1 of the output buffer 33 at the same time. At this time, the transistor M1 and the ground are grounded. The gate oxide layer of VSS is easily damaged by this high voltage. On the contrary, please refer to FIG. 4, which shows an embodiment of the 1/0 protection device of the present invention. The numbered ones represent the same components and will not be described later. According to FIG. 4, this embodiment mainly includes an output buffer 430 'and the coupling capacitor Cc is coupled to the output terminal A1 of the output buffer 430 to its input. The terminal A2 'is used to form a coupling signal V2 at its input terminal A2 when a predetermined potential signal V1 appears at the output terminal A1 of the output buffer 430 when the situation shown in FIG. 3 occurs. In addition, the embodiment also Provide a control reverse brake INV1, which is connected to the input terminal A2 of the aforementioned output buffer 430, to 'output an isolation control signal L' when the coupling signal v2 reaches a first voltage value (0 · 5 VDDH) and when coupled When the signal V2 is below a second voltage value (0.5VDDL), a normal control signal is output. Also, the I / O protection device further includes a plurality of series-connected previous-stage buffers, wherein the last-stage front-stage buffers are displayed here. 410. Fore buffer 41 〇 This paper Dimension description / 1] Chinese National Standard ® M CNS) A4 specification (210 × 297 male Chu) (诮 Please read the precautions on the back before filling this page), 1T-Jun!浐 部 tA «.M '-^,-; i1-eliminated together 410508 A7 --------------------- --- Η / V. Invention Explanation (7) 'A2' stands: output terminal A5, which is coupled to the input terminal of output buffer 430, ', has a control terminal A6', which is coupled to the wheel output A3 of the control reverse brake INv 丨 for the receiver In order to isolate the wheel of the control signal buffer 410, the Ac reference is used to isolate the output from the ground VSS, and when the received system number is received, the front-stage buffer 41o operates normally. For example. In the 1/0 circuit, a high voltage signal sometimes appears at the output terminal A1 of the output buffer 430, for example, in an external circuit with a higher operating voltage VDDH or a lower operating voltage vddl: When the potential output signal is used by other wheelers with output buffers (not shown τ), the voltage value of this predetermined positive potential signal (such as (VDDH = 5V, VDDL 2.5V) will also appear at 1 / 〇 塾 45〇) That is, the predetermined potential signal VI appearing at the output terminal A1 of the output buffer 430 may be a lower operating calendar VDDL that the output buffer 430 can withstand, or a comparison that the output buffer 430 cannot withstand. High operating voltage VDDH. Based on the foregoing, please refer to Fig. 4 and refer to Fig. 5, because the implementation of the system is to make the coupling capacitor Cc coupled to the output terminal A1 of the output buffer 43 (the end of the transistor M1) to its input A2 (the transistor The gate of M1) is shown in the equivalent circuit of Fig. 5. At this time, the coupling capacitor crosses the pole output # A1 and the open-electrode input A2, and the open-circuit power valley Cg of the transistor M1 crosses the gate wheel. Terminal A2 and ground node VSS, so the gate wheel input terminal A2 will form a coupling signal V2. According to the series line formed by I / O pad-A1-Cc-A2-Cg-VSS, it can be known that the coupling signal V2 is the output terminal A1. The predetermined partial voltage of the potential signal 乂 丨, so if you adjust the 9 family of paper music scales (关) A < J specifications (2) Gx 297 cm) I-^ ----- l ·- ί In ------ Order ------ 4 — (I read the precautions on the back before writing this page) 410502 A7 B7 V. Description of the invention (8) — — _ Appropriate value of Cc ' For example, if the capacitance Cc = Cg, then the coupling signal V2 = G.5V1, that is, the voltage difference W across the open-electrode layer of the closed-electrode capacitor Cg, * the interlayer insulation layer (V1- V2), the potential range is 祜 ^ Qiao granary is limited to a tin (5 square VDDL~〇 5 VDDH), it is not easy due to the high voltage output of the buffer νι of 43〇 damaged. Referring to FIG. 8, a cross-sectional view of a part of the semiconductor structure in the embodiment of the coupling capacitor Cc is shown. This coupling capacitor is mainly established on the gate of the transistor M1, that is, on a substrate 800 having a source / inverter 83, which is isolated by a shallow trench isolation structure 810, and sequentially forms a gate insulation. Layer 890 and a gate conductive layer 85 °, which constitute the transistor M1, and then form a stack of #structures, which includes at least an interlayer insulating layer 860 and a second conductive layer 87 °, which are formed on the gate conductive layer 8 The surface and the stacked structure determine the coupling capacitance value a and the gate capacitance value Cg according to the area occupied by the gate conductive layer 85 and the second conductive layer 870 and their overlapping sensing areas. For example, a silicon substrate 800 has a lightly doped source and a drain 830, respectively. The drain is coupled to the I / C pad 45, and is used as the drain output terminal A1 of the output buffer 430. A gate oxide layer 890 is formed on the surface of the silicon substrate 800, and a polycrystalline silicon layer 850 is formed on the surface of the gate oxide layer 890, which is used as the cathode input terminal A2 of the output buffer 430. In addition, the built-up structure, 'here one layer is taken as an example', includes an interlayer insulating layer 86 and a polycrystalline broken layer 870 formed on the surface of the gate polycrystalline silicon layer 860. The foregoing structure forms an insulating gap on the side wall. 880. The size of this paper ^ China National Cotton Standard (CNS) Regulation 8 (2 | 〇χ297mm > ------ r--ίA ------ order ------ flavor 1 (" Read the precautions on the back first, and then clever this page} 410502 Λ7 ______________________________ B7 V. Description of the invention (9) — The coupling capacitor Cc of the inter-layer insulation layer 860 thus formed and the closed pole of the gate insulation layer The capacitance Cg is based on the area occupied by the polycrystalline silicon layer and the polycrystalline silicon layer 870 and its overlapping sensing area to adjust the values of the coupling capacitance Cc and the gate capacitance Cg. For example, if Ce = Cg, the interlayer insulation layer is crossed. The voltage difference of 860 and the voltage difference of 89 across the gate oxide layer are equal to about 0.5V. Both of them are not easy to cause damage. 纟 + V1 includes potential voltages VDDH and VDDL of different logic levels, such as 5 V and 2.5V. However, during the high voltage of V1 such as VDDH at the output terminal A1 of the buffer 430, the coupling signal V2 of the input terminal of the buffer 430 (M1 thyristor extreme) 8 must be sufficient for a period of time, otherwise once it is cycled Discharge path and discharge from the ground node, the voltage difference between the cross-coupling capacitor Cc and the cross-gate capacitor _ Cg will be Return to VDDH, if the isolated insulation layer is damaged, the output buffer 430 will also lose its function. Based on the foregoing, please cooperate with Figure 4 and refer to Figures 6 and 7 to maintain the buffer 43. 〇 Input (M1 transistor gate) A2 consumption signal V2, as shown in Figure 4, this embodiment adds a control transistor such as nm 0 transistor M6 and its control gate terminal to the front buffer 410 in this embodiment. A6, and Fig. 6 provides a control reverse brake iNV 丨, which is formed by a series connection of an NMOS transistor M3 coupled to the ground node VSS and a PMOS transistor M4 coupled to the system power supply VDD. Among them, the gates of the transistors M3 and M4 The pole is connected to the buffer 43 ° input terminal, which is the mi transistor gate terminal A2, and the series drain output terminal A3 is coupled to the control gate terminal A6 of the control transistor M6 in the previous stage buffer 410. 11 Dimensions Country National Humble (CNS) A4 specification (210X297 mm) ---------- K --- uli Table ------ ^ ------- Λ (诮 Please read the note on the back first Matters again? * Ben 1) 410502 A7 B7 ----- ---- ----------.------------ ---- ---- -___... _ — V. Description of the invention (10) Figure. The relationship between the turn-in (A2) / output (A3) to be formed by controlling the reverse gate INV1 is shown in Table 1. Among them, by using the characteristic curves of the mosquito-control PMOS transistor M4 and the NMOS transistor M3, a The control logic INV1 of the high logic switching voltage value Vtl, such as using an ion implantation step such as implanting boron fluoride ion (BF2), to increase the initial voltage value Vt of the NMOS transistor M3 controlling the voltage INV1. Vt (M3) = 0.5VDDL 'to control the logic switching voltage Vtl of the control reverse gate INV1 between 0.5VDDL and 0.5VDDH. As for the logic switching voltage Vtl and the switching interval (A, B) of 0.5VDDL and 0.5VDDH, compared with The better one is to select 0.05V < A <2V; 0.05V < B < 2V. (诮 Read the back of the note first, and then "quot: ':': " this page) Table 1 Control Inverter INV1 (Logic F conversion voltage value Vtl) Input A2 Output A3 0.5VDDL Logic 1 potential: H (hi £ h) 0.5VDDH logic 0 potential: Ulow) -Order -__ Therefore, when the coupling signal V2 is a higher voltage value, such as 0.5VDDH, Bay ,! The transistor M3 of the control inverter INV1 can be turned on, thereby outputting a logic 0 low-potential signal (L) and using it as an isolation control signal 'and when the handle signal V2 is a lower voltage value, such as ( K5VDDL 'can make the transistor M3 of the control inverter INV1 turn off, so it outputs a logic 1 high potential signal (H) as a normal control signal. As for the operation of the front stage buffer 410 and the control inverter INV1 The relationship is as shown in Figure 4. 'The front stage buffer 41〇 includes a coupling paper to the ground node 12 paper size. This uses 1hf national standard (CNS) A4 specification (210X297 cm) 410502 A7 _______B7 V. Description of the invention ( 11) (Please read the precautions on the back before filling in this text) The NMOS transistor M5 of VSS and a PMOS transistor M7 coupled to the system power VDD, the gates of the transistors M5 and M7 are connected together to form an input terminal A7 'In the output mode', it receives signals from internal circuits to transmit it to the output buffer 430 ', and the pmMOS transistor M6 is connected in series between the NMOS transistor M5 and the PMOS transistor M7. The common connection of the drains of the transistors M6 and M7 in the stage buffer 410 An output terminal A5 ′ is formed, which is coupled to the input terminal A2 of the output buffer 430. In addition, the transistor M6 has a control gate terminal A6, which is coupled to the wheel output terminal A3 of the control inverter INV1. Therefore, when the output buffer 430 When a predetermined potential "No. VI" appears at the output terminal A1, the input terminal A2 of the output buffer 430 forms a light-on signal V2 of about 0.5V1 through the divided voltage of the surface-bonding capacitor Cc. 〇5. When VDDH (greater than the logic switching voltage VU of the control inverse gate invi), the control inverse gate INV1 outputs a low-level isolation control signal L and is received by the control gate terminal A6 of the transistor M6, so that the transistor M6 is turned off. The output terminal 85 of the stage buffer 410 is isolated from the ground node VSS. Conversely, when the combined signal V2 is 0.5VDDL (less than the logic switching voltage Vtl of the control inverter INV1), the anti-closing mvi is turned to a high potential. The normal control signal Η is received by the control gate terminal a6 of the transistor M6, so that the transistor M6 is turned on. Therefore, in the output mode (〇utput m〇de), the input (A7) / output (A5) of the front buffer 410 ) Can operate normally according to the transistor M5, M7. 13 Paper size Deduct Chinese storehouse standard (CNS) A4 specification (210X297 mm> A7 410502 B7, -v _ — — --..-. —-V. Description of the invention (12) In addition, according to Figure 7 if it appears in the output The predetermined potential signal V1 of the output terminal A1 of the buffer 43 is a low-potential signal such as a logic 0 k number or a ground signal and the value is less than 0.5VDDL. Because the transistor M3 that controls the reverse brake INV1 remains closed, the control The anti-gate INV1 outputs a high-level normal control signal H, so that the transistor M6 is turned on, and the former buffer 410 is in a normal operating state. In summary, the above embodiment of the present invention uses a coupling capacitor to divide the over-high voltage appearing on the 1/0 pad, and outputs an isolation control signal by the control back gate to isolate the output end of the front buffer from the ground node. As the output end of the front buffer is coupled to the input end of the output buffer, this voltage division value can be continuously maintained to 'reduce the voltage difference between the power dissipation capacitor and the gate valley' to prevent static electricity in the I / O circuit or High voltage damage in multi-voltage power supplies. In addition, the 'coupling capacitor' can be a stacked capacitor structure, so it is compatible with existing steps and avoids traditional complicated semiconductor processes. Although the present invention has been disclosed in the following with a preferred embodiment, it is not intended to limit the present invention, 'any person skilled in the art, without departing from the spirit and scope of the present invention', can make a few changes and retouching. The scope of protection of the invention shall be determined by the scope of the attached patent application. 14 This paper is suitable for the Sichuan National Standards ((:) ^) 8 4 specifications (2) 0: < 297 mm) (诮 Read the following precautions before writing this page}
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