TW201816761A - Display control circuit and operation method thereof - Google Patents

Abstract

A display control circuit includes a charging unit, a writing unit, a display unit, a maintaining unit, a first control unit, a second control unit, a first capacitor and a second capacitor. The writing unit is used to receive a data signal. The display unit is electrically coupled to the charging unit and a common voltage terminal for displaying an image. The maintaining unit is electrically coupled to the writing unit, the display unit and the second capacitor. The first capacitor is electrically coupled to the first control unit and the writing unit. The second control unit is electrically coupled to the charging unit and a reference voltage.

Description

Display control circuit and operation method thereof

The invention relates to a display control circuit and an operation method thereof, and more particularly to a liquid crystal display control circuit and an operation method thereof.

In the field of liquid crystal display, in a display control circuit (such as a pixel control circuit of a liquid crystal display), a driving transistor as a source follower can control whether a data voltage is written into a liquid crystal capacitor. However, this driving transistor is prone to aging with long-term use, which affects the gray-scale accuracy of the liquid crystal display.

At present, display control circuits of six-transistor-two-capacitor (also known as 6T2C) architecture can be used in the art, which can detect the critical voltage drift of the transistor of the source follower and compensate for it, thereby mitigating the effect of transistor aging . The 6T2C architecture display control circuit includes at least six transistors and two capacitors, four control lines and three reference power lines, for a total of seven signal lines.

In addition, a display control circuit with a six-transistor-three-capacitor (also known as 6T3C) architecture is currently available in the art, which can also be used to compensate for the threshold voltage drift of the driving transistor. The 6T3C architecture display control circuit includes at least six transistors and three capacitors, three control lines and two reference power lines, for a total of five signal lines.

As mentioned above, current display control circuits usually include at least six transistors and five to seven signal lines. The above 6T2C and 6T3C display control circuits have complicated structures, too many components and signal lines, resulting in too low an aperture ratio and poor light transmission. Therefore, a better solution is still needed in the field of liquid crystal display to improve the aperture ratio, simplify the circuit structure, reduce the number of components and signal lines, and avoid poor display grayscale accuracy caused by transistor aging.

An embodiment of the present invention provides a display control circuit including a first switch, a second switch, a liquid crystal capacitor, a third switch, a fourth switch, a first capacitor, a second capacitor, and a fifth switch. The first switch includes a first terminal and a second terminal. The second switch includes a first terminal and a second terminal, and the first terminal is used for receiving data signals. The liquid crystal capacitor includes a first terminal and a second terminal. The first terminal is electrically coupled to the second terminal of the first switch, and the second terminal is electrically coupled to the common voltage terminal. The third switch includes a first terminal and a second terminal, the first terminal is electrically coupled to the second terminal of the second switch, and the second terminal is electrically coupled to the first terminal of the liquid crystal capacitor. The fourth switch includes a first terminal and a second terminal. The first capacitor includes a first terminal and a second terminal, the first terminal is electrically coupled to the second terminal of the fourth switch, and the second terminal is electrically coupled to the second terminal of the second switch. The second capacitor includes a first terminal and a second terminal, and the first terminal is electrically coupled to the first terminal of the third switch. The fifth switch includes a first terminal and a second terminal, the first terminal is electrically coupled to the second terminal of the first switch, and the second terminal is electrically coupled to the reference level.

An embodiment of the present invention provides a display control circuit including a charging unit, a writing unit, a display unit, a maintaining unit, a first control unit, a first capacitor, a second capacitor, and a second control unit. The charging unit includes a first terminal and a second terminal. The writing unit includes a first terminal and a second terminal. The first terminal is used for receiving data signals. The display unit includes a first terminal and a second terminal, the first terminal is electrically coupled to the second terminal of the charging unit, and the second terminal is electrically coupled to the common voltage terminal. The sustaining unit includes a first terminal and a second terminal. The first terminal is electrically coupled to the second terminal of the writing unit, and the second terminal is electrically coupled to the first terminal of the display unit. The first control unit includes a first terminal and a second terminal. The first capacitor includes a first terminal and a second terminal, the first terminal is electrically coupled to the second terminal of the first switch, and the second terminal is electrically coupled to the second terminal of the writing unit. The second capacitor includes a first terminal and a second terminal, and the first terminal is electrically coupled to the first terminal of the sustaining unit. The second control unit includes a first terminal and a second terminal. The first terminal is electrically coupled to the second terminal of the charging unit, and the second terminal is electrically coupled to the reference level.

An embodiment of the invention provides a method for operating a display control circuit. The display control circuit includes a charging unit, a first control unit, a second control unit, a writing unit, a maintaining unit, a first capacitor, a second capacitor, and a display unit. The second terminal of the charging unit is electrically coupled to the first of the display unit. One end, the second end of the maintenance unit and the first end of the second control unit. The first end of the maintenance unit is electrically coupled to the second end of the first capacitor, the first end of the second capacitor, and the writing unit. The second end, the first end of the writing unit is used to receive data signals, the first end of the first capacitor is electrically coupled to the second end of the first control unit and the control end of the charging unit, and the first end of the display unit. The two terminals are electrically coupled to the common voltage terminal, and the second terminal of the second capacitor is electrically coupled to the control terminal of the second control unit. The operation method includes turning on the maintenance unit and the first control unit during the reset phase, switching the first end of the first control unit to a high level, thereby turning on the charging unit, and switching the first end of the charging unit to a low level. Position to reset the second end of the maintenance unit to the low level; in the compensation phase after the reset phase, the first end of the charging unit is switched to the high level, and the second end of the second capacitor is switched to the high level To turn on the second control unit and the second end of the charging and maintaining unit to the first predetermined level; in the writing stage after the compensation stage, turn off the maintaining unit and the first control unit and turn on the writing unit to turn the first The first end of the capacitor is coupled to a second predetermined level; in the sustaining phase after the writing phase, the writing unit is turned off to charge the level of the second end of the maintaining unit to a level substantially equal to the data signal; and In the display phase after the maintenance phase, the second control unit is turned off, and the second end of the second capacitor is lowered to a low level, so that the control end of the coupled charging unit is at a low level to turn off the charging unit.

The display control circuit and the control method provided by the embodiments of the present invention can reduce the threshold voltage drift of the transistor to stabilize the brightness and gray scale of the liquid crystal display.

FIG. 1 is a schematic diagram of a display control circuit 100 according to another embodiment of the present invention. The display control circuit 100 may include a charging unit 110a, a writing unit 120a, a display unit 170a, a maintaining unit 130a, a control unit 140a, a control unit 150a, a first capacitor C1, and a second capacitor C2. The writing unit 120a can receive a data signal Sd. The display unit 170a may be electrically coupled to the charging unit 110a and the common voltage terminal V _COM for displaying an image. The sustaining unit 130a may be electrically coupled to the writing unit 120a, the display unit 170a, and the second capacitor C2. The first capacitor C1 can be electrically coupled to the control unit 140a and the writing unit 120a. The control unit 140a is configured to receive the control signal S _REF and is electrically coupled to the charging unit 110a. The control unit 150a can be electrically coupled to the charging unit 110a and the reference level VSS. The control units 140a and 150a can be controlled to be turned on or off.

FIG. 2 is a schematic diagram of a display control circuit 200 according to an embodiment of the present invention. The display control circuit 200 may include a first switch 110, a second switch 120, a liquid crystal capacitor _CLC , a third switch 130, a fourth switch 140, a first capacitor C1, a second capacitor C2, and a fifth switch 150. The first switch 110 may include a first terminal and a second terminal, wherein the first terminal is electrically coupled to the operating voltage V _DD . The second switch 120 may include a first terminal and a second terminal, and the second terminal may be used to receive a data signal Sd. The liquid crystal capacitor C _LC may include a first terminal and a second terminal, the first terminal is electrically coupled to the second terminal of the first switch 110, and the second terminal is electrically coupled to the common voltage terminal V _COM . The third switch 130 may include a first terminal and a second terminal. The first terminal is electrically coupled to the second terminal of the second switch 120, and the second terminal is electrically coupled to the first terminal of the liquid crystal capacitor C _LC . The first end of the third switch 130 may correspond to the node B in FIG. 1. The fourth switch 140 may include a first terminal and a second terminal. The first terminal is used to receive the control signal S _REF . The first capacitor C1 may include a first terminal and a second terminal, the first terminal is electrically coupled to the second terminal of the fourth switch 140, and the second terminal is electrically coupled to the second terminal of the second switch 120. The first terminal of the first capacitor C1 may correspond to the node A in FIG. 1. The second capacitor C2 may include a first terminal and a second terminal, and the first terminal is electrically coupled to the first terminal of the third switch 130. The fifth switch 150 may include a first terminal and a second terminal. The first terminal is electrically coupled to the second terminal of the first switch 110, and the second terminal is electrically coupled to the reference level VSS. The first end of the fifth switch 150 may correspond to the node C in FIG. 1. According to the embodiment of the present invention, the reference level VSS may be a suitable level.

According to the embodiment of the present invention, when the first switch 110 and the fifth switch 150 are transistor switches, the value of the reference level VSS may be selected to make the first switch 110 and the fifth switch 150 operate in a saturation region. According to the embodiment of the present invention, in contrast to the control circuit 100 in FIG. 1, in the embodiment in FIG. 2, the charging unit 110 a may include a first switch 110, the writing unit 120 a may include a second switch 120, and the maintaining unit 130 a A third switch 130 representation may be included. The display unit 170 a may include a liquid crystal capacitor C _LC , the control unit 140 a may include a fourth switch 140, and the control unit 150 a may include a fifth switch 150. Therefore, the charging unit 100a, the writing unit 120a, and the maintaining unit 130a may be elements that have substantially a switching function and can be controlled to be turned on / off. The control circuit 100 in FIG. 1 of the present invention is not limited to the range shown in the embodiment in FIG. 2. The developer can still adjust the circuit design according to requirements, such as electrostatic protection, design rule check, or other function control. It still falls within the scope of the embodiments of the present invention.

According to an embodiment of the present invention, as shown in FIG. 2, the second switch 120 may further include a control terminal for receiving the control signal S2 and controlled by the control signal S2. The fourth switch 140 may further include a control terminal for receiving the control signal S1 and controlled by the control signal S1. The fifth switch 150 may further include a control terminal for receiving the control signal S _BIAS and controlled by the control signal S _BIAS . The control terminal of the fifth switch 150 is also electrically coupled to the second terminal of the second capacitor C2. The third switch 130 may further include a control terminal, which is electrically coupled to the control terminal of the fourth switch 140 for receiving the control signal S1 and controlled by the control signal S1. The first switch 110 may further include a control terminal, which is electrically coupled to the first terminal of the first capacitor C1, that is, node A in FIG. 1. According to the embodiment of the present invention, the display control circuit 100 may further include a sustaining capacitor C _st to help the liquid crystal capacitor C _LC maintain the charge and display data. The sustaining capacitor C _st may include a first terminal and a second terminal. The first terminal is coupled to the liquid crystal capacitor C _LC , and the second terminal is electrically coupled to the common voltage terminal V _COM . The holding capacitor C _st can be selectively used or omitted according to design requirements.

FIG. 3 is an operation waveform diagram of the display control circuit 100 of the embodiment in FIG. 2. 4 to 8 may be operation explanatory diagrams of the display control circuit 100 of the embodiments of FIGS. 2 and 3. In Fig. 3, the waveforms of the control signals S1, S2, S _REF and S _BIAS and the operating voltage V _DD can be adjusted corresponding to the reset phase P1, the compensation phase P2, the write phase P3, the maintenance phase P4 and the display phase P5 . These five stages can be cycled. The control signal S _REF can be a high level V _REFH or a low level V _REFL . The operating voltage V _DD may be a high level V _DDH or a low level V _DDL . In the present invention, the high level and the low level refer to relative values, and generally one of them corresponds to the level of the enabled circuit and the other corresponds to the level of the disabled circuit.

FIG. 4 may correspond to the reset phase P1. When the display phase P5 enters the reset phase P1, the control signal S1 can be set to a high level to turn on the third switch 130 and the fourth switch 140, and the control signal S2 is set to a low level, so that The second switch 120 and the fifth switch 150 are kept in an off state. Adjusting the control signal S _REF to a high level V _REFH can make the node A a high level, thereby turning on the first switch 110. By adjusting the operating voltage V _DD to a low level V _DDL , the first end and the second end of the third switch 130 can be reset to a low level.

Figure 5 may correspond to the compensation phase P2. When entering the compensation phase P2 from the reset stage P1, the control signal S1 can be kept at a high level to keep the third switch 130 and the fourth switch 140 on, and the control signal S2 can be kept at a low level to keep the second switch 120 off. The control signal S _BIAS can be adjusted to a high level to turn on the fifth switch 150, the control signal S _REF can be maintained at a high level V _REFH , and the operating voltage V _DD can be adjusted to a high level V _DDH . Since the fourth switch 140 is turned on, the level of the node A at this time can be the same as the control signal S _REF and also the high level V _REFH . The levels of nodes B and C can be represented by the level V _OUT . The following is the derivation process of the level V _OUT .

When the first switch 110 and the fifth switch 150 are transistor switches, and the first switch 110 is operated in a saturation region, the current I _D flowing through the first switch 110 can be expressed by an equation eq-1:

I _D = K ₁ (V _REFH -V _OUT -V _TH1 ) ² = K ₅ (V _BIAS – VSS–V _TH5 ) ² …… (eq-1);

Wherein, K ₁ may be a process parameter of a first transistor switch 110, K ₅ may process parameters of the fifth transistor switch 150, V _TH1 and V _TH5 may be respectively a first switch 110 and the fifth switch 150 The threshold voltage and the level V _BIAS can be the voltage value of the control signal S _BIAS . VSS is the aforementioned reference level coupled to the second end of the fifth switch 150. The algebra α is introduced to represent the square root of the ratio of the process parameters K ₁ and K _5. The formula eq-1 can be arranged into the formula eq-2:

α = √ (K ₁ / K ₅ ) = (V _BIAS -V _TH5 -VSS) / (V _REFH -V _OUT -V _TH1 ) ... (eq-2);

After finishing, the formula eq-3 can be derived:

_{αV REFH} -αV _OUT -αV _TH1 = V _BIAS -V _TH5 -VSS ... (eq-3);

Sorting out the formula eq-3, the formula eq-4 can be derived as follows:

_{V OUT = V REFH -V TH1 +} (1 / α) · V TH5 - (1 / α) · VSS - (1 / α) · V BIAS ...... (eq-4);

According to the equation eq-4, in Figure 5, the level of node C can be charged to the level V _OUT , which is [V _REFH -V _TH1 + (1 / α) V _TH5- (1 / α) · _VSS- ( 1 / α) V _BIAS ], this level V _OUT can be regarded as the first predetermined level. In addition, since the fourth switch 140 is turned on, the level of the node A in the compensation phase P2 may correspond to the control signal S _REF and also a high level V _REFH . Therefore, the first end of the first capacitor C1 and the second The terminal can store a level difference (V _REFH -V _OUT ), which can be used in the next stage.

FIG. 6 may correspond to the writing phase P3. When entering the writing phase P3 from the compensation phase P2, the control signal S1 can be adjusted to a low level to turn off the third switch 130 and the fourth switch 140, and the control signal S2 can be adjusted to a high level to turn on the second switch S2. The control signal S _REF can be maintained at a high level V _REFH , the operating voltage V _DD can be maintained at a high level V _DDH , and the control signal S _BIAS can be maintained at a high level to keep the fifth switch 150 on. After the second switch 120 is turned on, the data signal Sd can be transmitted to the node B through the second switch 120, so the level of the node B can correspond to the level Vd of the data signal Sd. As mentioned above, both ends of the first capacitor C1 (that is, between nodes A and B) can store the level difference (V _REFH -V _OUT ) after the compensation phase P2, so the level of node A can be the level of node B. The _{sum of the} level and the level difference (V _REFH -V _OUT ), that is, (Vd + V _REFH -V _OUT ). This value can be the second predetermined level.

The levels V _A , V _B , and V _C represent the levels of nodes A, B, and C, respectively. As mentioned above, it can be known that the level V _A can be coupled to the second predetermined level (Vd + V _REFH -V _OUT ). The level V _B may be the same as the level Vd of the data signal Sd, and the level V _C may be the output level V _OUT of the display control circuit 100 during the writing phase P3. After derivation, the output level V _OUT can be substantially equal to the level Vd of the data signal Sd, and its derivation is as follows.

The level V _A can be expressed by the equation eq-5: V _A = V _REFH + (Vd – V _REFH + V _TH1 – (1 / α) · V _TH5- (1 / α) · VSS + (1 / α) · V _BIAS ) ... (eq-5);

The aforementioned current I _D flowing through the first switch 110 can be expressed by an equation eq-6:

I _D = K ₁ (Vd + V _TH1- (1 / α) · V _TH5- (1 / α) · VSS + (1 / α) · V _BIAS – V _OUT – V _TH1 ) ²

= K ₁ (Vd-(1 / α) · V _TH5- (1 / α) · VSS + (1 / α) · V _BIAS – V _OUT ) ²

= K ₅ (V _BIAS –VSS–V _TH5 ) ² …… (eq-6);

As described above, the algebra α can be the square root of the ratio of the process parameters K ₁ and K ₅ , so the equation eq-7 can be derived:

α = √ (K ₁ / K ₅ )

= (V _BIAS – V _TH5 ) / (Vd-(1 / α) V _TH5 – (1 / α) VSS + (1 / α) V _BIAS – V _OUT ) …… (eq-7);

After finishing, you can get the formula eq-8:

α (Vd-(1 / α) V _TH5- (1 / α) VSS + (1 / α) V _BIAS -V _OUT ) = V _BIAS -V _TH5 ...... (eq-8);

Then we can sort out the formula eq-9:

αVd-V _TH5 -VSS + V _BIAS --αV _OUT = V _BIAS -V _TH5 -VSS ... (eq-9);

By deleting V _TH5 and V _BIAS on both sides of equation eq-9, the derivation result is as follows:

V _OUT = Vd ...... (eq-10);

It can be known from the equation eq-10 that the output level V _OUT can be substantially equal to the level Vd of the data signal Sd. However, the output level V _OUT still needs to be charged to reach the level Vd, so the operation of the embodiment of the present invention can enter the maintenance phase P4 shown in FIG. 7.

FIG. 7 may correspond to the maintenance phase P4. When entering the maintenance phase P4 from the writing phase P3, the control signal S1 can be kept at a low level to keep the third switch 130 and the fourth switch 140 off, and the control signal S2 can be adjusted to a low level to turn off the second The switch 120 can keep the control signal S _BIAS at a high level to keep the fifth switch 150 on, can keep the control signal S _REF at a high level V _REFH , and can keep the operating voltage V _DD at a high level V _DDH . In the sustaining phase P4, since the first switch 110 and the fifth switch 150 are turned on, the operating voltage V _DD set at the high level V _DDH can continuously charge the node C so that the output level V _{OUT of the} node C is sustained. Charge to the level Vd which is substantially equal to the data signal Sd. As described above, during the writing phase P3 and the sustaining phase P4, the liquid crystal capacitor C _LC can be displayed according to the data signal Sd.

FIG. 8 may correspond to the display phase P5. When entering the display phase P5 from the maintenance phase P4, the control signal S1 can be kept at a low level to keep the third switch 130 and the fourth switch 140 off, and the control signal S2 can be kept at a low level to keep the second switch S2 off. By adjusting the control signal S _REF to a low level V _REFL , the control signal S _BIAS can be adjusted to a low level to turn off the fifth switch 150. The control signal S _{BIAS is} adjusted to a low level, and the level V _{A of the} node A can also be coupled to the low level through the second capacitor C2 and the first capacitor C1. As deduced above, since the level V _C of the node C is the level Vd of the data signal Sd in the maintenance phase P4, the difference between the level V _A and the level V _C after the level V _A is coupled to the low level The value may be smaller than the threshold voltage of the transistor of the first switch 110, so that the first switch 110 is turned off. Therefore, in the display stage P5, the first to fifth switches 110-150 can all be turned off, thereby suppressing the leakage of the node C, and slowing down the aging effect of the transistors of all the switches.

FIG. 9 is a flowchart of an operation method 900 of the display control circuit of FIGS. 2 to 8. Steps 910 to 950 of the operation method 900 may correspond to the stages shown in the above-mentioned FIGS. 4-8, respectively. The operation method 900 steps can be as follows:

Step 905: Start;

Step 910: In the reset phase P1, turn on the third switch 130 and the fourth switch 140, keep the second switch 120 and the fifth switch 150 in an off state, and adjust the control signal S _REF to a high level V _REFH thereby turns on the first switch 110 and adjusts the operating voltage V _DD to a low level V _DDL to reset the first and second ends of the third switch 130 to a low level;

Step 920: In the compensation phase P2 after the reset phase P1, the operating voltage V _{DD is} converted to a high level V _DDH , and the control signal S _{BIAS is} converted to a high level to turn on the fifth switch 150, and then charge the third switch 130. The second end to the first predetermined level;

Step 930: In the writing phase P3 after the compensation phase P2, turn off the third switch 130 and the fourth switch 140, and turn on the second switch 120 to couple the first end of the first capacitor C1 to a second predetermined level;

Step 940: In the sustain phase P4 after the write phase P3, the second switch 120 is turned off, the third switch 130 and the fourth switch 140 are kept off, the fifth switch 150 is kept on, and the operating voltage V _DD is kept high. The level V _DDH charges the level of the second end of the third switch 130 to be substantially the same as the data signal Vd;

Step 950: In the display phase P5 after the maintenance phase P4, maintain the second, third, and fourth switches 120-140 to be off, turn off the fifth switch 150, and adjust the control signal received by the second end of the second capacitor C2. S _{BIAS is} at a low level, and then the first end of the first capacitor C1 is coupled to the low level through the second capacitor C2 and the first capacitor C1, so that the first switch 110 is turned off;

Step 955: if the display operation is continued, proceed to step 910; if the display operation is not continued, proceed to step 960; and

Step 960: End.

Fig. 10 is a schematic diagram of measurement results corresponding to the operation waveforms of Fig. 3, each operation stage of Figs. 4-8, and the operation method of Fig. 9. The horizontal axis of FIG. 10 can be time, and its unit can be microseconds (us) as an example, the vertical axis can be a measurement level, and its unit can be volts as an example. The curves V _A0 , V _A3 , and V _{A3 ′} can be the levels measured at node A by using transistors with threshold voltages of 0 volts, +3 volts, and -3 volts as switches, respectively. The curves V _C0 , V _C3 , and V _{C3 ′} can be the levels obtained by measuring at the node C by using the transistors whose threshold voltages and predetermined values have drift differences of 0 volts, +3 volts, and −3 volts, respectively. The curve V _S2 can be the level of the control signal S2. As shown in FIG. 10, at the later stage of the maintenance stage P4 and the display stage P5, the curves V _C0 , V _C3 , and V _{C3 ′} can be substantially superimposed. Therefore, according to the embodiment of the present invention, when the threshold voltage of the transistor is − Between 3 volts and +3 volts, the output level VOUT of node C can be kept substantially stable. Therefore, the display control circuit provided by the embodiment of the present invention can effectively improve the display instability caused by the process drift of the transistor.

The first to fifth switches 110-150 can be normally-off or normally-on transistors, and N-type metal-oxygen half-field-effect transistors can be selected according to the needs of developers. P-type half-effect transistor, bipolar junction transistor, or other similar switching elements. The display control circuit provided by the embodiment of the present invention can be applied to general liquid crystal display, and can also be applied to blue phase liquid crystal.

In summary, when a transistor is used as the switching element of the present invention, the display control circuit 100 provided by the embodiment of the present invention may include first to fifth switches 110-150, first to second capacitors C1-C2, and liquid crystal capacitor C _LC , so the display control circuit 100 in the embodiment of the present invention may be a display control circuit with a five-transistor-three-capacitor (may be referred to as 5T3C) architecture. In addition, the total number of control signals of the display control circuit 100 of the present invention can be as shown in FIG. 3, and a total of five signal lines are required. Compared with the control circuit of 6T2C architecture (seven signal lines) or 6T3C architecture (five signal lines) known in the art, the 5T3C architecture of the embodiment of the present invention can effectively reduce the number of components and therefore improve the aperture ratio. In addition, the display control circuit and the control method provided by the embodiments of the present invention can also resist the threshold voltage drift of the transistor to stabilize the brightness and gray scale of the liquid crystal display, and can also slow down the aging of the switching element. Therefore, the present invention is significantly helpful for improving the lack of known techniques in the art. The above description is only a preferred embodiment of the present invention, and all equivalent changes and modifications made in accordance with the scope of patent application of the present invention shall fall within the scope of the present invention.

100, 200‧‧‧ display control circuit

110‧‧‧The first switch

120‧‧‧Second switch

130‧‧‧Third switch

140‧‧‧Fourth switch

150‧‧‧ fifth switch

S1, S2, S _REF , S _BIAS ‧‧‧ Control signal

V _DD ‧‧‧ Operating voltage

Sd‧‧‧ Data Signal

VSS‧‧‧ Reference Level

C _st ‧‧‧

C _LC ‧‧‧ LCD Capacitor

C1‧‧‧first capacitor

C2‧‧‧Second capacitor

V _COM ‧‧‧ Common Voltage Terminal

A, B, C‧‧‧ nodes

110a‧‧‧Charging unit

120a‧‧‧write unit

130a‧‧‧maintenance unit

170a‧‧‧display unit

140a, 150a‧‧‧ Control Unit

V _REFH , V _DDH ‧‧‧ high level

V _REFL , V _DDL ‧‧‧ low level

P1‧‧‧ Reset stage

P2‧‧‧Compensation stage

P3‧‧‧writing stage

P4‧‧‧ Maintenance phase

P5‧‧‧Display stage

I _D ‧‧‧ Current

Vd‧‧‧level

V _OUT ‧‧‧ Output Level

900‧‧‧ operation method

905 to 960‧‧‧ steps

FIG. 1 is a schematic diagram of a display control circuit according to an embodiment of the present invention. FIG. 2 is a schematic diagram of a display control circuit according to an embodiment of the present invention. FIG. 3 is an operation waveform diagram of the display control circuit of the embodiment of FIG. 1. FIG. 4 to 8 are operation explanatory diagrams of the display control circuit of the embodiment of FIGS. 1 and 3 in each stage. FIG. 9 is a flowchart of the operation method of the display control circuit in FIGS. 1 to 8. Fig. 10 is a schematic diagram of measurement results corresponding to the operation waveforms of Fig. 3, each operation stage of Figs. 4 to 8, and the operation method of Fig. 9.

Claims (10)

A display control circuit includes: a first switch including a first terminal and a second terminal; a second switch including a first terminal for receiving a data signal and a second terminal; a liquid crystal The capacitor includes a first terminal, which is electrically coupled to the second terminal of the first switch, and a second terminal, which is electrically coupled to a common voltage terminal; a third switch, which includes a first terminal, electrically A second switch is electrically coupled to the second end of the second switch, and a second end is electrically coupled to the first end of the liquid crystal capacitor; a fourth switch includes a first end, and a second end A first capacitor including a first terminal electrically coupled to the second terminal of the fourth switch, and a second terminal electrically coupled to the second terminal of the second switch; a first Two capacitors, including a first terminal, electrically coupled to the first terminal of the third switch, and a second terminal; and a fifth switch, including a first terminal, electrically coupled to the first The second terminal and a second terminal of the switch are electrically coupled to a reference level. The display control circuit according to claim 1, wherein: the fourth switch further includes a control terminal; the fifth switch further includes a control terminal, which is electrically coupled to the second terminal of the second capacitor; The three switches further include a control terminal, which is electrically coupled to the control terminal of the fourth switch; and the first switch further includes a control terminal, which is electrically coupled to the first terminal of the first capacitor. The display control circuit according to claim 1 or 2, wherein: the fourth open relationship is used to be conductive during a reset phase and a compensation phase, and is set to a write phase, a maintenance phase, and a display phase. At the end of the reset phase, the compensation phase, the write phase, and the sustain phase, the first end of the fourth switch is used to set a high level, and during the display phase, the fourth switch The first end is used to set a low level; the fifth open relationship is used to be turned on during the compensation phase, the writing phase, and the maintenance phase, and set to be off during the reset phase and the display phase. ; The second open relationship is used to be turned on during the writing phase, and set to be closed during the reset phase, the compensation phase, the maintenance phase, and the display phase; the third open relationship is used to reset The phase and the compensation phase are set to be on, and are set to be off during the writing phase, the maintenance phase, and the display phase; the first open relationship is used in the reset phase, the compensation phase, the writing phase, and the The sustain phase is set to on, and the display phase is set to off , The first end of the first switch is used to set a low level in the reset stage, and the first end of the first switch is used in the compensation stage, the writing stage, the maintenance stage, and The display phase is set to a high level; and the second end of the second capacitor is used to set the low level during the reset phase and the display phase, during the compensation phase, the writing phase, and the The maintenance phase is set to a high level. The display control circuit according to claim 1, further comprising: a maintenance capacitor including a first terminal, which is electrically coupled to the first terminal of the liquid crystal capacitor, and a second terminal, which is electrically coupled to the Common voltage terminal. A display control circuit includes: a charging unit including a first terminal and a second terminal; a writing unit including a first terminal for receiving a data signal and a second terminal; a display unit Includes a first terminal electrically coupled to the second terminal of the charging unit, and a second terminal electrically coupled to a common voltage terminal; a maintenance unit including a first terminal electrically coupled The second terminal and a second terminal of the writing unit are electrically coupled to the first terminal of the display unit; a first control unit includes a first terminal and a second terminal; The first capacitor includes a first terminal, which is electrically coupled to the second terminal of the first control unit, and a second terminal, which is electrically coupled to the second terminal of the writing unit; a second The capacitor includes a first terminal, which is electrically coupled to the first terminal of the maintenance unit, and a second terminal; and a second control unit, which includes a first terminal, is electrically coupled to the charging unit. The second terminal and a second terminal are electrically coupled to a reference level. The display control circuit according to claim 5, wherein: the first control unit includes a first switch, and the second control unit includes a second switch; the first switch includes a first terminal and a second terminal Electrically coupled to the charging unit and a control terminal; the second switch includes a first terminal electrically coupled to the display unit, a second terminal electrically coupled to a reference level and a control terminal, electrically coupled At the second end of the second capacitor; the writing unit includes a third switch electrically coupled to the maintenance unit; the maintenance unit includes a fourth switch, the maintenance unit includes a control terminal, electrically coupled The control terminal of the first switch; and the charging unit includes a fifth switch, and the charging unit further includes a control terminal, which is electrically coupled to the first terminal of the first capacitor. The display control circuit according to claim 5 or 6, wherein: the first control unit is configured to be turned on in a reset phase and a compensation phase, and set in a write phase, a maintenance phase, and a display phase. To close, the first end of the first switch is used to set the high level during the reset phase, the compensation phase, the write phase, and the maintenance phase, and during the display phase, the first switch The first end is used to set the low level; the second control unit is used to set the conduction during the compensation phase, the writing phase, and the maintenance phase, and is set during the reset phase and the display phase. Is the cut-off; the writing unit is set to be turned on during the writing phase, and set to be cut-off during the reset phase, the compensation phase, the maintenance phase, and the display phase; the maintenance unit is used for the reset phase The setting phase and the compensation phase are set to be on, and the writing phase, the maintenance phase and the display phase are set to be off; the charging unit is used for the reset phase, the compensation phase, the writing phase and the The sustain phase is set to be on, and in this display phase Set to off, the first end of the charging unit is set to a low level in the reset phase, and the first end of the charging unit is used in the compensation phase, the writing phase, and the maintaining phase And the display phase is set to a high level; and the second end of the second capacitor is set to the reset phase and the display phase is set to a low level during the compensation phase, the writing phase, and the maintaining The stage is set to a high level. The method according to claim 5, wherein the display control circuit further includes a sustaining capacitor, including a first terminal, which is electrically coupled to the first terminal of the display unit, and a second terminal, which is electrically coupled At the common voltage terminal. A method for operating a display control circuit. The display control circuit includes a charging unit, a first control unit, a second control unit, a writing unit, a maintaining unit, a first capacitor, a second capacitor, and a display. Unit, a second end of the charging unit is electrically coupled to a first end of the display unit, a second end of the maintenance unit and a first end of the second control unit, and a first end of the maintenance unit One terminal is electrically coupled to a second terminal of the first capacitor, a first terminal of the second capacitor, and a second terminal of the writing unit. A first terminal of the writing unit is used for Receiving a data signal, a first terminal of the first capacitor is electrically coupled to a second terminal of the first control unit and a control terminal of the charging unit, and a second terminal of the display unit is electrically coupled At a common voltage terminal, a second terminal of the second capacitor is electrically coupled to a control terminal of the second control unit. The operation method includes: in a reset stage, turning on the maintenance unit and the first control unit. To switch the first end of the first control unit to a high level To turn on the charging unit and switch the first end of the charging unit to a low level to reset the second end of the maintaining unit to a low level; at a compensation stage after the reset stage, Switch the first end of the charging unit to a high level, and switch the second end of the second capacitor to a high level to turn on the second control unit and charge the second end of the maintenance unit to a A first predetermined level; in a writing phase after the compensation phase, closing the maintaining unit and the first control unit, turning on the writing unit to couple the first end of the first capacitor to a second A predetermined level; in a maintenance phase after the writing phase, closing the writing unit to charge the level of the second end of the maintenance unit to a level substantially the same as the data signal; and in the maintenance In a display stage after the stage, the second control unit is turned off, and the second end of the second capacitor is lowered to a low level, thereby coupling the control end of the charging unit to a low level to turn off the charging unit. The method according to claim 9, further comprising providing a sustaining capacitor including a first terminal, which is electrically coupled to the first terminal of the display unit, and a second terminal, which is electrically coupled to the common voltage. end.