RU2513759C1 - Heterogeneous processor - Google Patents

Abstract

FIELD: physics, computer engineering.

SUBSTANCE: invention relates to computer engineering and specifically to digital signal processing. The heterogeneous processor comprises: a universal processor with a port, an input/output unit with a port, a RAM controller with a port, a unit for rapid execution of digital signal processing algorithms with a port, which consists of a memory direct accessing controller, a program memory unit and a computer section control unit, each consisting of a register file unit with ports, connected to the port of the computer section control unit, a local ROM unit and an arithmetic logic unit, consisting of input register units, output register units, multiplier units and adder units, installed in a number which is sufficient to execute B±C×D operations for each circuit, where B, C and D are complex numbers, real and imaginary parts of which are 32-bit floating-point numbers, and the processor is equipped with a buffer memory unit with ports.

EFFECT: low power consumption per unit output and high processor throughput.

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Description

The invention relates to the field of computer technology, namely to the field of digital signal processing, where it is necessary to combine the functions of a universal microprocessor and the functions of a digital signal processor.

It is known that universal microprocessors are traditionally used for building computers, servers (Intel, AMD, IBM), as well as for embedding in other systems (ARM, MIPS). Universal microprocessors are characterized by tasks with a large number of conditional transitions and a low level of internal parallelism, respectively, universal microprocessors are optimized to effectively predict transitions and extract built-in parallelism of instructions. For programming universal microprocessors, high-level programming languages such as C are used. Another class of microprocessors, called digital signal processing processors, is used in areas of computer engineering where there is an input data stream on which it is required to perform a set of specific actions in the mode of their arrival. The input data can be digitized values from a video camera, microphone, locator and other sources. The tasks of digital signal processing are characterized by a high degree of parallelism according to the data, a small number of conditional transitions and a high input data rate. For efficient programming of digital signal processing processors, traditionally use low-level languages such as assembler.

With the development of the system-on-chip concept, which implies the integration of several functional devices on a single silicon chip, microcircuits began to appear, combining the functions of a universal microprocessor and a digital signal processing processor.

The closest in technical essence and the achieved result is the IBM Cell microprocessor, which includes a universal processor with a port, an input / output unit with a port, a memory controller with a port and 8 blocks of accelerated execution of digital signal processing algorithms with a port (JAKahle, M.N . Day et al. "Introduction to the Cell multiprocessor", IBM J. RES & DEV. VOL. 49 NO. 4/5, JULY / SEPTEMBER 2005, p. 589-504).

This microprocessor allows you to effectively solve problems that combine control tasks and digital signal processing tasks for most types of data, such as integer and real data. However, there are problems in which the data is presented in the form of complex numbers, the real and imaginary parts of which are 32-bit floating point numbers. For this type of data, an operation of the form B ± C × D, which is the main operation of the fast Fourier transform, requires 10 arithmetic operations - 4 multiplications and 6 additions / subtractions with 32-bit floating-point numbers. Traditionally, arithmetic operations are performed sequentially, while for each operation it is required to read data from the register file and save the result in the register file. The described processor uses modern multiplication and addition schemes, which allows performing operations in 1 clock cycle of the processor frequency, as a result of which the operation B ± C × D with complex numbers will be performed in 10 clock cycles and will require 20 readings and 10 writes to the register file for one operation , which leads to the need to perform a significant number of additional actions, which leads to increased energy consumption.

Thus, the disadvantage of the processor described above is the high power consumption per unit of performance.

The objective of the invention is to reduce energy consumption per unit of productivity.

The technical result from the use of the invention is to reduce power consumption per unit of productivity and increase processor performance, by increasing the speed and energy efficiency of program execution, combining control tasks and tasks of digital signal processing.

The specified technical result is achieved by the fact that in a heterogeneous processor including a universal processor with a port, an input / output unit with a port, a memory controller with a port and an accelerated block of digital signal processing algorithms with a port, the processor is equipped with a buffer memory unit with ports, one of which is connected with the input / output unit, and the universal processor, the unit for accelerated execution of digital signal processing algorithms and the memory controller are equipped with additional ports each, and this universal processor and the unit for the accelerated execution of digital signal processing algorithms through its ports are connected to the ports of the buffer memory unit and the ports of the RAM controller, and the unit for the accelerated execution of digital signal processing algorithms consists of a direct memory access controller, a program memory unit, and a computing control unit sections, each of which consists of a block of a register file with ports connected to a port of a control unit of computing sections, a block locally RAM and the block of the arithmetic-logic device, consisting of blocks of input registers, blocks of output registers, blocks of multipliers and blocks of adders, set in an amount sufficient to perform the operation B ± C × D each cycle, where B, C and D are complex numbers , real and imaginary, parts of which are 32-bit floating point numbers.

The invention is illustrated by drawings, where in Fig.1 shows a General diagram of a heterogeneous processor, in Fig. 2 is a block diagram of an accelerated processing unit for digital signal processing algorithms; FIG. 3 is a block diagram of an arithmetic logic unit.

A heterogeneous processor consists of an input / output unit 1 with ports 2 and 3, a buffer memory unit 4 with ports 5, 6 and 7, a universal processor 8 with ports 9, 10 and 11, a direct memory access controller 12 with ports 13, 14 and 15, an accelerated processing unit for digital signal processing algorithms 16 with ports 17, 18 and 19.

External communication lines connecting the heterogeneous processor to other external devices are connected to port 2 of the water / output unit 1, port 3 of the input / output unit 1 is connected to port 5 of the buffer memory unit 4, port 6 of the buffer memory unit 4 is connected to port 9 of the universal processor 8 , port 7 of the buffer memory unit 4 is connected to port 18 of the block for accelerated execution of digital signal processing algorithms 16, port 10 of the universal processor 8 is connected to port 14 of the controller for direct access to RAM 12, and port 11 of the universal processor 8 is for prison to the port block 17 expedite the digital signal processing algorithms 16, the port 19 is connected to the port 15 of RAM controller 12, the port 13 is connected to RAM chips vernal.

The block for accelerated execution of digital signal processing algorithms 16 consists of a program memory block 20, port 21 of which is connected to port 11 of universal processor 8, and port 22 is connected to port 23 of control unit of computing sections 24, port 25 of which is connected to port 11 of universal processor 8, port 26 is connected to port 27 of the direct memory access controller 28, and port 29 is connected to port 30 of the register file block 31. Ports 32 of the direct memory access controller 28 are connected to computing sections, each of which consists of Lok ALU 33, register file unit 31 and the local RAM unit 34 sequentially interconnected. Ports 18 and 19 of the block of the direct memory access controller 28 are connected to ports 7 of the buffer memory 4 and 15 of the RAM controller 12, respectively.

The block of the arithmetic-logical device 33 of each section contains blocks of input registers 35, 36, 37, with input ports 38, 39, 40, respectively, associated with ports of blocks of multipliers 41, 42, 43, 44, which in turn are connected to adder blocks 45 , 46. Blocks of adders 47, 48, 49, 50 are connected with blocks of output registers 51, 52, with output ports 53, 54.

The input / output unit 1 is designed to receive data coming from external communication lines to its port 2, and write it to the buffer memory unit 4, as well as to read data from the buffer memory unit 4 and transfer it to external communication lines through input 2.

The buffer memory unit 4 is designed to store data transmitted from the input / output unit 1 through port 5 and to provide access to this data from the universal processor 8 through port 6 or from the side of the accelerated block of digital signal processing algorithms 16 through port 7. The buffer memory unit 4 also stores data transmitted from port 9 of the universal processor 8 through port 6, while providing access to these data from the input / output unit 1 through port 5, or the block for accelerated execution of digital algorithms processing of signals 16 through port 7. The buffer memory unit 4 is also used to store data transmitted from the side of the accelerated block of digital signal processing algorithms 16 through port 7 and to provide access to these data from the universal processor 8 through input 6, or from I / O unit 1 through port 5. The buffer memory unit 4 can be built on the basis of standard random access memory with an access control circuit.

The universal processor 8 is designed to perform control tasks, as well as to download the control program from port 11 to port 17 of the accelerated block of digital signal processing algorithms 16. In this case, the universal processor 8 stores intermediate data in external RAM, which it accesses through the operational controller memory 12.

The memory controller 12 is designed to serve requests to external memory chips from the universal processor 8, arriving at port 14, and from the accelerated execution unit of digital signal processing algorithms 16, arriving at port 15. The memory controller 12 can be built on the basis of a standard RAM controller.

The block for accelerated execution of digital signal processing algorithms 16, comprising a program memory block 20, a control unit for computing sections 24, a direct access controller for memory 28, and several computing sections, each of which contains a block of an arithmetic-logical device 33, a block of a register file 31, and a block of local RAM 34, is designed to execute arithmetic instructions with 32-bit floating point numbers every clock cycle, including operations of type B ± C × D, where B, C and D are complex numbers, real and imaginary, parts of Which are 32-bit floating point numbers every clock cycle.

The heterogeneous processor described above operates as follows.

The input / output unit 1 writes the data coming from external communication lines to its input 2 to the buffer memory unit 4, and also reads data from the buffer memory unit 4 and transfers it to external communication lines through input 2. Data coming from external communication lines, can be a program for a universal processor 8, data for a universal processor 8, a program for an accelerated block of digital signal processing algorithms 16 or data for a block of accelerated execution of digital signal processing algorithms 16.

If the heterogeneous processor performs the control task, then the program for the control processor 8 is transmitted from the external communication lines 2 through the input / output unit 1 to the buffer memory unit 4. The control processor 8 reads the program from the buffer memory unit 4 and proceeds to its execution. In the process of executing the program, data can be exchanged between the universal processor 8 and the external memory chips through the memory controller 12.

If the heterogeneous processor performs the task of digital signal processing, then the program for the block for the accelerated execution of digital signal processing algorithms 16 is transmitted from external communication lines 2 through the input / output unit 1 to the buffer memory unit 4. The universal processor 8 reads the program for the block from the buffer memory block 4 accelerated execution of digital signal processing algorithms 16 and writes it to the program memory 20 of the accelerated execution block of digital signal processing algorithms 16, after which it transfers control to control section of computing sections 24. The control section of computing sections 24 controls the following processes:

- controls the controller of direct access to the memory 28 for transferring data from the buffer memory unit 4 to the external memory chips via the memory controller 12 and vice versa;

- controls the controller of direct access to the memory 28 to transfer data from the local RAM unit of the computing sections 34 to the external memory chips through the memory controller 12 and vice versa;

- controls the exchange between the local RAM unit of the computing sections 34 and the blocks of the register file of the computing sections 31.

All of the above operations are performed simultaneously.

The block of the arithmetic-logical device 33, which is part of the computing section when performing an operation of the form B ± C × D, where B, C and D are complex numbers, the real and imaginary parts of which are 32-bit floating point numbers, works as follows:

three complex numbers B, C and D are read from the register file block 31 and written through the input ports 38, 39, 40 to the blocks of the input registers 35, 36, 37, while the number C is sent from the port 38 to the register 35, from the port 39 to register 36 receives the number D, from port 40 the register 37 receives the number B. The operation of multiplying complex numbers C and D requires four multiplications, one addition and one subtraction, which are performed in blocks of multipliers 41, 42, 43, 44 and adder blocks 45 and 46 respectively. The operation of adding complex numbers requires two addition operations, which are performed by adder blocks 47 and 48, and the subtraction of complex numbers requires two subtraction operations, which are performed by adder blocks 49 and 50, respectively. The result of the operation B + C × D is stored in the block of the output register 51, the result of the operation B-C × D is stored in the block of the output register 52, and from their output ports 53 and 54, the results are recorded in the register file 31.

Thus, due to the possibility of performing an operation of the form B ± C × D, where B, C and D are complex numbers, the real and imaginary parts of which are 32-bit floating point numbers every clock cycle, while doing one reading of the command code, one read from the register file and one write to the register file, it reduces power consumption per unit of performance and improves processor performance.

Claims (1)

A heterogeneous processor, including a universal processor with a port, an input / output unit with a port, a memory controller with a port and an accelerated block of digital signal processing algorithms with a port, characterized in that the processor is equipped with a buffer memory unit with ports, one of which is connected to the unit I / O, and the universal processor, the unit for accelerated execution of digital signal processing algorithms and the memory controller are equipped with additional ports each, while the universal processor and OK, the accelerated execution of digital signal processing algorithms through their ports are connected to the ports of the buffer memory block and the ports of the RAM controller, and the accelerated execution block of digital signal processing algorithms consists of a direct memory access controller, a program memory block, and a control unit for computing sections, each of which consists of a block of a register file with ports connected to a port of a control unit for computing sections, a block of local RAM and a block of arithmetic-logical device consisting of blocks of input registers, blocks of output registers, blocks of multipliers and blocks of adders, set in an amount sufficient to perform the operation B ± C × D every cycle, where B, C and D are complex numbers, real and imaginary, parts which are 32-bit floating point numbers.

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