PT2430555E - Translation of input/output addresses to memory addresses - Google Patents

Translation of input/output addresses to memory addresses Download PDF

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Publication number
PT2430555E
PT2430555E PT107763500T PT10776350T PT2430555E PT 2430555 E PT2430555 E PT 2430555E PT 107763500 T PT107763500 T PT 107763500T PT 10776350 T PT10776350 T PT 10776350T PT 2430555 E PT2430555 E PT 2430555E
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PT
Portugal
Prior art keywords
bits
addresses
address
translation
input
Prior art date
Application number
PT107763500T
Other languages
Portuguese (pt)
Inventor
David Craddock
Thomas Gregg
Dan Greiner
Eric Norman Lais
Original Assignee
Ibm
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Ibm filed Critical Ibm
Publication of PT2430555E publication Critical patent/PT2430555E/en

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Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/10—Address translation
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/0223—User address space allocation, e.g. contiguous or non contiguous base addressing
    • G06F12/0292—User address space allocation, e.g. contiguous or non contiguous base addressing using tables or multilevel address translation means
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/20—Employing a main memory using a specific memory technology
    • G06F2212/206—Memory mapped I/O
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/34—Addressing or accessing the instruction operand or the result ; Formation of operand address; Addressing modes
    • G06F9/355—Indexed addressing

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
  • Bus Control (AREA)
  • Executing Machine-Instructions (AREA)
  • Memory System (AREA)

Abstract

An address provided in a request issued by an adapter is converted to an address directly usable in accessing system memory. The address includes a plurality of bits, in which the plurality of bits includes a first portion of bits and a second portion of bits. The second portion of bits is used to index into one or more levels of address translation tables to perform the conversion, while the first portion of bits are ignored for the conversion. The first portion of bits are used to validate the address.
PT107763500T 2010-06-23 2010-11-08 Translation of input/output addresses to memory addresses PT2430555E (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US12/821,170 US8635430B2 (en) 2010-06-23 2010-06-23 Translation of input/output addresses to memory addresses

Publications (1)

Publication Number Publication Date
PT2430555E true PT2430555E (en) 2013-10-03

Family

ID=43805638

Family Applications (1)

Application Number Title Priority Date Filing Date
PT107763500T PT2430555E (en) 2010-06-23 2010-11-08 Translation of input/output addresses to memory addresses

Country Status (20)

Country Link
US (3) US8635430B2 (en)
EP (1) EP2430555B1 (en)
JP (1) JP5636097B2 (en)
KR (1) KR101455544B1 (en)
CN (1) CN102906719B (en)
AU (1) AU2010355813B2 (en)
BR (1) BR112012033815B1 (en)
CA (1) CA2800636C (en)
DK (1) DK2430555T3 (en)
ES (1) ES2428822T3 (en)
HK (1) HK1180793A1 (en)
HR (1) HRP20130820T1 (en)
MX (1) MX2012014859A (en)
PL (1) PL2430555T3 (en)
PT (1) PT2430555E (en)
RU (1) RU2547705C2 (en)
SG (1) SG186098A1 (en)
SI (1) SI2430555T1 (en)
WO (1) WO2011160722A1 (en)
ZA (1) ZA201209649B (en)

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