KR890002477B1 - Time-delayed relay - Google Patents

Time-delayed relay

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Publication number
KR890002477B1
KR890002477B1 KR1019860007319A KR860007319A KR890002477B1 KR 890002477 B1 KR890002477 B1 KR 890002477B1 KR 1019860007319 A KR1019860007319 A KR 1019860007319A KR 860007319 A KR860007319 A KR 860007319A KR 890002477 B1 KR890002477 B1 KR 890002477B1
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South Korea
Prior art keywords
output
inverting buffer
delay time
flip
signal
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KR1019860007319A
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Korean (ko)
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KR880004518A (en
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배명운
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금성기전 주식회사
홍종선
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Priority to KR1019860007319A priority Critical patent/KR890002477B1/en
Publication of KR880004518A publication Critical patent/KR880004518A/en
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Publication of KR890002477B1 publication Critical patent/KR890002477B1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01H—ELECTRIC SWITCHES; RELAYS; SELECTORS; EMERGENCY PROTECTIVE DEVICES
    • H01H47/00—Circuit arrangements not adapted to a particular application of the relay and designed to obtain desired operating characteristics or to provide energising current
    • H01H47/02—Circuit arrangements not adapted to a particular application of the relay and designed to obtain desired operating characteristics or to provide energising current for modifying the operation of the relay
    • H01H47/18—Circuit arrangements not adapted to a particular application of the relay and designed to obtain desired operating characteristics or to provide energising current for modifying the operation of the relay for introducing delay in the operation of the relay

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  • Electronic Switches (AREA)
  • Relay Circuits (AREA)

Abstract

The relay is drived with certain time delay at on/off operation for preventing the damage caused by over current. An inverting buffer output is applied to an input terminal of "on" delay time setting circuit (1) which output is connected to a R-S Flip-flop (U3) input terminal (R). A shunted output of the inverting buffer is connected to the "off" delay time setting circuit (2) which output terminal is connected to the R-S Flip-flop (U3) input terminal through a non- inverting buffer. The output terminal of the R-S flip-flop is connected to a transistor (TR1) for driving a relay (RY1).

Description

시간 지연 계전기Time delay relay

제1도는 본 발명의 회로도.1 is a circuit diagram of the present invention.

제2도는 발면의 회로 동작 설명도.2 is an explanatory diagram of the circuit operation of the foot surface.

* 도면의 주요 부분에 대한 부호의 설명* Explanation of symbols for the main parts of the drawings

1 : 온지연시간 세팅회로 2 : 오프지연 시간 세팅회로1: On delay time setting circuit 2: Off delay time setting circuit

U1-1U1-2:인버팅 버퍼소자 U2-1,U2-2: 넌인버팅버퍼소자U 1-1 U 1-2 : Inverting buffer element U 2-1 , U 2-2 : Non-inverting buffer element

U3: R-S플립플롭 R1,R2,R3: 고정저항U 3 : RS flip-flop R 1 , R 2 , R 3 : Fixed resistance

VR1,VR2: 가변저항 C1,C2: 콘덴서VR 1 , VR 2 : Variable resistor C 1 , C 2 : Capacitor

D1,D2,D3: 다이오드 RY1: 릴레이D 1 , D 2 , D 3 : Diode RY 1 : Relay

TR1: 트랜지스터 A,B,C : 접점TR 1 : Transistor A, B, C: Contact

t1: 온지연시간 t2: 오프지연시간t 1 : On delay time t 2 : Off delay time

본 발명은 기기의 전원을'온,오프'시 과전압,과전류가 기기에 곧바로 유입되어 발생하는 기기의 소손 및 전기 안전사고를 미연에 방지 하기 위하여 사용자가 원하는 시간만큼 '온,오프'시간을 지연시켜 일정한 시간 경과후 신호를 발생토록 하여 기기를 안전하게 동작할 수 있도록한 시간지연 장치에 관한 것이다. 이러한 장치는 여러 전기기계에 사용 응용될 수 있으며, 특히 전기기계에 있어서 과전압 과전류등의 이상사태 검출회로와 더불어 구성할 경우 일시적인 과전압, 과전류에서는 동작하지 않는 안전성이 보장된 우수한 계진기를 구성할 수가 있게 되는 것이다.The present invention delays the 'on, off' time by the user's desired time in order to prevent damage to the device and electrical safety accidents caused by overvoltage and overcurrent flowing into the device immediately when the device is powered on or off. The present invention relates to a time delay device capable of safely operating a device by generating a signal after a predetermined time elapses. Such a device can be used for various electric machines, and especially when configured with an abnormal state detection circuit such as an overvoltage or overcurrent in an electric machine, it is possible to construct an excellent gauging device that guarantees safety that does not operate under temporary overvoltage or overcurrent. Will be.

종래에도 기기의 지연동작을 위한 계전기 회로(일본 실용신안공보소 43-31137)가 안출된 바 있었으나, 이는 -Vcc, oV, Vbb와 같은 쌍전원이 필요하며, '온'시의 지연동작만이 가능하고, 또한 지연시간도 조정이 불가능하여 실사용에 있어서 그 효용가치를 기대할 수 없는 문제가 있었다. 이하, 본 발명을 첨부도면에 의거 상세히 설명하면 다음과 같다.In the past, a relay circuit (Japanese Utility Model Publication No. 43-31137) for delaying operation of a device has been proposed, but this requires a double power supply such as -Vcc, oV, and Vbb, and only delay operation at 'on' time. There was a problem that the useful value could not be adjusted and the delay time could not be adjusted. Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

제1도의 회로에 도시된 바와 같이 외부에서 들어오는 신호가 센서(도시생략)에 감지되어 인버팅 버퍼소자(U1-1)의 입력에 인가되면 그 신호는 반전 출력되어 다이오드(D1)의 캐소드에 인가됨과 동시에, 인버팅버퍼소자(U1-1)의 출력은 분기되어 인버팅버퍼소자(U1-1)의 입력에 인가되고 그 출력은 다시 반전되어 다이오드(D2)의 캐소드에 인가된다. 한편, 가변저항(VR1)과 고정저항(R1)및 콘덴서(C1)로 구성되는 온지연 시간 세팅회로(1)는, 상기 인버팅버퍼소자(U1-1)에 연결된 다이오드(D1)의 에노드에 연결되며, 콘덴서(C1)의 +단자측은 넌인버팅버퍼소자(U2-1)의 입력에 인가되고, 그의 출력은 다시 R-S플립플롭(U3)의 입력단자(R)에 인가된다. 또한, 가변저항(VR2)과 고정저항(R2)및 콘덴서(C2)로 구성되는 오프지연시간 세팅회로(2)는 상기한 인버팅버퍼소자(U1-2)에 연결된 다이오드(D2)의 에노드에 연결되며, 콘덴서(C2)의 +단자는 넌인버팅버소자(U2-2)의 입력에 인가되고 그의 출력은 R-S 플리플롭(U3)의 입력단자(S)에 인가된다.As shown in the circuit of FIG. 1, when an external signal is detected by a sensor (not shown) and applied to the input of the inverting buffer device U 1-1 , the signal is inverted and output to the cathode of the diode D 1 . At the same time, the output of the inverting buffer element U 1-1 is branched and applied to the input of the inverting buffer element U 1-1 and its output is inverted again and applied to the cathode of the diode D 2 . do. On the other hand, the ON delay time setting circuit (1) consisting of a variable resistor (VR 1 ), a fixed resistor (R 1 ) and a capacitor (C 1 ), the diode (D) connected to the inverting buffer element (U 1-1 ) 1 ), the + terminal side of the capacitor C 1 is applied to the input of the non-inverting buffer element U 2-1 , and its output is again input terminal R of the RS flip-flop U 3 . Is applied. In addition, the off delay time setting circuit 2 including the variable resistor VR 2 , the fixed resistor R 2 , and the capacitor C 2 is connected to the inverting buffer element U 1-2 . 2 ), the + terminal of the capacitor C 2 is applied to the input of the non-inverting bus element U 2-2 and its output is connected to the input terminal S of the RS flip-flop U 3 . Is approved.

R-S플립플톱(U3)의 입력단자(R)(S)에 인가된 신호는 그의 출력단자(Q)로 출력되고, 고정저항(R3)을 통하여 트랜지스터(TR1)의 베이스에 인가되어 릴레이(RY1)을 구동하게 된다. 이 릴레이(RY1)의 구동에 의하여 접점(A)와 접점(C)이 붙게 되고, 접점(B)와 접점(C)는 떨어지게 되는 것이다. 제2도에 의해서 본 발명을 설명하면, 인버팅버퍼소자(U1-1)의 입력에 인가되는 신호를 a라하면, 인버팅버퍼소자(U1-1)의 출력에는 a신호와 180°위상이 반전된 b신호가 출력되게 되며, 즉 센서 감지된 외부 신호(a)가 '하이'에서 '로우'로 떨어지면 b신호는 로우에서 하이로 올라가게 되나, 가변저항(VR1), 고정저항(R1), 콘덴서(C1)로 구성되는 온지연시간 세팅회로(1)에 의해 온지연시간(t1)만큼 지연되어 넌인버팅버퍼소자(U2-1)를 거쳐 출력되게 된다.The signal applied to the input terminal R (S) of the RS flip-top U 3 is output to its output terminal Q, and is applied to the base of the transistor TR 1 through the fixed resistor R 3 to relay It will drive (RY 1 ). The contact A and the contact C are attached by the driving of the relay RY 1 , and the contact B and the contact C are separated. When describing the present invention by FIG. 2, the inverting buffer element when (U 1-1) the signal applied to the input of a called, an inverting buffer device has a 180 ° signal and the output of the (U 1-1) When the b signal whose phase is reversed is output, that is, when the sensor-detected external signal (a) falls from 'high' to 'low', the b signal goes up from low to high, but the variable resistor (VR 1 ) and the fixed resistor It is delayed by the on delay time t 1 by the on delay time setting circuit 1 composed of (R 1 ) and the condenser C 1 , and is output through the non-inverting buffer element U 2-1 .

즉, C신호가 출력되어 R-S필립플톱(U3)의 입력(R)에 인가되는 것이다. 또한, 인버팅버퍼소자(U1-1)에서 출력된 b신호는 인버팅버퍼소자(U1-2)에 인가되어 180°위상에 반전되어 인버팅버퍼소자(U1-2)의 출력으로 b'신호가 나오게 된다. 이 b'는 가변저항(VR2)과 고정저항(R2) 및 콘덴서(C2)로 구성되는 오프 지연시간 세팅회로(2)에 의해서 로우에서 하이로 될때 오프지연시간(t2)만큼 지연되어 C'의 신호가 넌인버팅버퍼소자(U2-2)로부터 출력되는 것이다. 즉, 오프지연시간(t2)만큼 지연되어 R-S플립플롭(U3)의 입력단자(S)에 인가되는 것이다.That is, the C signal is output and applied to the input R of the RS Philliptop U 3 . Further, as the output of the inverting buffer element is an inverting buffer the signal b element inverting buffer device (1-2 U) is applied to (1-2 U) is inverted to a 180 ° phase output at the (U 1-1) b 'signal comes out. This b 'is delayed by the off delay time (t 2 ) when it goes from low to high by an off delay time setting circuit (2) consisting of a variable resistor (VR 2 ), a fixed resistor (R 2 ), and a capacitor (C 2 ). The signal of C 'is output from the non-inverting buffer element U 2-2 . That is, it is delayed by the off delay time t 2 and applied to the input terminal S of the RS flip-flop U 3 .

여기서 C'신호에서의 초기지연시간(t2)은 전원을 '온'할때의 초기 시간으로, 본 발명의 기기동작에는 전혀 영향을 미치지 않는다. R-S플립플톱(U3)의 입력단자 (R)(S)에 인가된 신호는 출력단자(Q)로 d신호와 같이 출력되며, 즉, 외부 입력신호(a)가 하이에서 로우로 되면 온지연시간(t1)만큼 경과후 로우에서 하이로 되며, 외부 입력신호(a)가 다시 로우에서 하이로 되면 오프지연시간(t2)만큼 경과후 하이에서 로우로 떨어지게 된다. 이 d신호는 고정저항(R3)을 거쳐 트랜지스터(TR1)의 베이스에 인가되어 릴레이(RY1)을 구동시키게 되는데, 이때 트랜지스터(TR1)의 콜레터측 출력신호는 R-S플립플톱(U3)의 출력신호(d)와 180°위상이 반전된 e의 신호가 출력되어 릴레이 (RY1)를 구동시키게 되는 것이다. 즉, 외부입력신호(a)가 하이에서 로우로 떨어지면 온지연시간(t1)만큼 경과후 트랜지스터(TR1)의 출력신호(e)가 하이에서 로우로 떨어지게 되며,(릴레이(RY1)의 접점(A)와 접점(C)가 온지연시간(t1)경과후 '오프'에서 '온'으로 됨), 다시 외부입력신호(a)가 로우에서 하이로 올라가면 오프지연시간(t2)만큼 경과후 트랜지스터(TR1)의 출력신호(e)가 로우에서 하이로 올라간다(릴레이(RY1)의 접점(A)와 접점(C)가 오프지연시간(t2) 경과후 '온'에서 '오프'로 됨).Here, the initial delay time t 2 in the C 'signal is an initial time when the power is'on', and does not affect the operation of the apparatus of the present invention. The signal applied to the input terminal R (S) of the RS flip-top U 3 is outputted as the d signal to the output terminal Q. That is, when the external input signal a goes from high to low, the delay is on. After the time t 1 has elapsed, it goes low to high, and when the external input signal a goes low to high again, it goes from high to low after elapsed by the off delay time t 2 . The signal d is applied to the base of the transistor TR 1 via a fixed resistor R 3 to drive the relay RY 1 , where the output signal of the transistor side of the transistor TR 1 is the RS flip-top U. The output signal d of 3 ) and the signal of e whose 180 ° phase is inverted are output to drive the relay RY 1 . That is, an external input signal (a) becomes the output signal (e) of after the transistor (TR 1) as in the high-low-to-fall-on delay time (t 1) falls from high to low, (relay (RY 1) Contact A and contact C become 'ON' from 'OFF' after elapse of ON delay time (t 1 ), and OFF delay time (T 2 ) when external input signal a rises from low to high After elapse of time, the output signal e of the transistor TR 1 goes from low to high (contact A and relay C of the relay RY 1 become 'on' after the off delay time t 2 ). 'Off').

이와 같이 본 발명은 단일 전원에 의하여 회로의 구동이 가능토록 함과 동시에 '온'시나, '오프'시 공히 일정한 지연시간 경과후 릴레이가 구동토록 함으로써 '온,오프'시 발생하는 과전압, 과전류로 부터 기기를 보호할 수 있는 신규의 발명으로, 본 장치를 외부 입력신호 검출회로(센서)와 연결하여 각종 전기 기기에 다방면으로 활용할 수 있는 것이다.As described above, the present invention allows the circuit to be driven by a single power supply, and at the same time, the relay is driven after a certain delay time has elapsed at the time of 'on' or 'off'. It is a novel invention that can protect the device from, by connecting the device with an external input signal detection circuit (sensor), it can be utilized in various fields in various electrical equipment.

Claims (1)

인버팅버퍼소자(U1-1)의 출력을 다이오드(D1)를 거쳐, 가변저항(VR1)과 고정저항(R1)및 콘덴서(C1)로 구성되는 온지연시간 세팅회로(1)의 입력측에 인가하고, 그의 출력측을 넌인버팅버퍼소자(U2-1)를 거쳐 R-S플립플롭(U3)의 입력단자(R)에 인가함과 동시에, 상기 인버팅버퍼소자(U1-1)의 분기출력은 인버팅버퍼소자(U1-2)와 다이오드(D2)를 거쳐 가변저항(VR2)과 고정저항(R2)및 콘덴서(C2)로 구성되는 오프지연시간세팅회로(2)의 입력측에 인가하여 그의 출력측을 넌인버팅버퍼소자(U2-2)를 거쳐 R-S플립플롭(U3)의 입력단자(S)에 인가시켜, 이 R-S플립플롭(U3)의 출력단자(Q)를 릴레이 (RY1)구동용 트랜지스터(TR1)에 연결하여 온, 오프지연이 가능토록 함을 특징으로 하는 시간지연 계전기.An on-delay time setting circuit 1 composed of a variable resistor VR 1 , a fixed resistor R 1 , and a capacitor C 1 through the output of the inverting buffer element U 1-1 through a diode D 1 . ) And the output side thereof is applied to the input terminal (R) of the RS flip-flop (U 3 ) via the non-inverting buffer element (U 2-1 ), and the inverting buffer element (U 1-). The branch output of 1 ) is set through the inverting buffer elements (U 1-2 ) and the diode (D 2 ), which is an off delay time setting consisting of a variable resistor (VR 2 ), a fixed resistor (R 2 ), and a capacitor (C 2 ). It was applied to the input terminal (S) of the circuit (2) RS flip-flop (U 3) is applied to the input side neonin its output side through the inverting buffer element (U 2-2) of, in the RS flip-flop (U 3) A time delay relay characterized in that the output terminal (Q) is connected to the relay (RY 1 ) driving transistor (TR 1 ) to enable on and off delay.
KR1019860007319A 1986-09-02 1986-09-02 Time-delayed relay KR890002477B1 (en)

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KR1019860007319A KR890002477B1 (en) 1986-09-02 1986-09-02 Time-delayed relay

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Application Number Priority Date Filing Date Title
KR1019860007319A KR890002477B1 (en) 1986-09-02 1986-09-02 Time-delayed relay

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KR880004518A KR880004518A (en) 1988-06-04
KR890002477B1 true KR890002477B1 (en) 1989-07-10

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104485258A (en) * 2014-12-19 2015-04-01 陕西群力电工有限责任公司 Miniature determined time sequential hybrid time delay relay without biasing end

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104485258A (en) * 2014-12-19 2015-04-01 陕西群力电工有限责任公司 Miniature determined time sequential hybrid time delay relay without biasing end
CN104485258B (en) * 2014-12-19 2017-01-11 陕西群力电工有限责任公司 Miniature determined time sequential hybrid time delay relay without biasing end

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