KR20240157510A - Operating method of nonvolatile memory device - Google Patents

Abstract

A method for operating a nonvolatile memory device including a plurality of memory blocks formed in a direction perpendicular to a substrate according to an embodiment of the present disclosure and having a plurality of strings connected between bit lines and a common source line, the method comprising: detecting first memory cells having an erase state among memory cells connected to a first word line; detecting second memory cells having a sixth program state or a seventh program state among memory cells connected to a second word line adjacent to the first word line; detecting target bit lines including both the first memory cell and the second memory cell; detecting target bits corresponding to the target bit line and corresponding to the erase state in write data to be programmed to a third word line adjacent to the second word line; generating flip bit position data based on the target bits; generating flipped data by flipping the target bits among the write data; and programming the flipped data and the flip bit position data to the third word line, wherein each of the plurality of strings includes a plurality of memory cells, the plurality of memory cells are divided into a first region and a second region, and the first region is divided into first to third portions. The memory cells are divided, and the write data includes first to third page data, and each of the plurality of memory cells is programmed to have one of an erase state and first to seventh program states, and when first sub-target bits of the target bits correspond to a first portion, second sub-target bits of the target bits correspond to a second portion, and third sub-target bits of the target bits correspond to a third portion, data corresponding to the first sub-target bits of the first page data is flipped, data corresponding to the second sub-target bits of the second page data is flipped, and data corresponding to the third sub-target bits of the third page data is flipped.

Description

OPERATING METHOD OF NONVOLATILE MEMORY DEVICE

The present disclosure relates to semiconductor memory, and more specifically, to an operating method of a nonvolatile memory device.

Semiconductor memory is divided into volatile memory devices such as SRAM and DRAM, which lose stored data when power is cut off, and nonvolatile memory devices such as flash memory devices, PRAM, MRAM, RRAM, and FRAM, which retain stored data even when power is cut off.

In order to increase the capacity of nonvolatile memory devices, three-dimensional structures are being introduced into nonvolatile memory devices. Due to the characteristics of the process for manufacturing the three-dimensional structure, the memory cells of the three-dimensional nonvolatile memory device may experience accelerated lateral diffusion in a specific pattern. There is a need for a device or method for preventing errors due to a specific pattern of states of vertically adjacent memory cells.

The present disclosure provides a method of operating a nonvolatile memory device with improved reliability.

A method for operating a nonvolatile memory device including a plurality of memory blocks formed in a direction perpendicular to a substrate according to an embodiment of the present disclosure and having a plurality of strings connected between bit lines and a common source line, the method comprising: detecting first memory cells having an erase state among memory cells connected to a first word line; detecting second memory cells having a sixth program state or a seventh program state among memory cells connected to a second word line adjacent to the first word line; detecting target bit lines including both the first memory cell and the second memory cell; detecting target bits corresponding to the target bit line and corresponding to the erase state in write data to be programmed to a third word line adjacent to the second word line; generating flip bit position data based on the target bits; generating flipped data by flipping the target bits among the write data; and programming the flipped data and the flip bit position data to the third word line, wherein each of the plurality of strings includes a plurality of memory cells, the plurality of memory cells are divided into a first region and a second region, and the first region is divided into first to third portions. The memory cells are divided, and the write data includes first to third page data, and each of the plurality of memory cells is programmed to have one of an erase state and first to seventh program states, and when first sub-target bits of the target bits correspond to a first portion, second sub-target bits of the target bits correspond to a second portion, and third sub-target bits of the target bits correspond to a third portion, data corresponding to the first sub-target bits of the first page data is flipped, data corresponding to the second sub-target bits of the second page data is flipped, and data corresponding to the third sub-target bits of the third page data is flipped.

A method for operating a nonvolatile memory device including a plurality of memory blocks formed in a direction perpendicular to a substrate according to an embodiment of the present disclosure, the memory blocks including a plurality of memory cells and having a plurality of strings connected between bit lines and a common source line, the method comprising: performing a first sensing operation on a first word line using a first read voltage to generate a first bitmap indicating a first memory cell corresponding to an erase state among memory cells connected to the first word line; performing a second sensing operation on a second word line adjacent to the first word line using a sixth read voltage to generate a second bitmap indicating second memory cells having a sixth program state or a seventh program state among memory cells connected to the second word line; performing an AND operation on the first bitmap and the second bitmap to generate a third bitmap indicating target bit lines including both the first memory cell and the second memory cell; receiving write data to be programmed into memory cells connected to the third word line adjacent to the second word line from the outside; performing an AND operation on the third bitmap and the write data. The method comprises the steps of: generating a fourth bitmap (BM4) indicating target bits corresponding to a weak pattern; generating flip bit position data based on the fourth bitmap; generating encoded data by performing a flip operation based on the write data and the flip bit position data; and programming the encoded data into memory cells connected to a third word line.

A method for operating a nonvolatile memory device including a plurality of memory blocks formed in a direction perpendicular to a substrate according to an embodiment of the present disclosure and having a plurality of strings connected between bit lines and a common source line, the method comprising: detecting first memory cells having an erase state among memory cells connected to a first word line; detecting second memory cells having a sixth program state or a seventh program state among memory cells connected to a second word line adjacent to the first word line; detecting target bit lines including both the first memory cell and the second memory cell; detecting target bits corresponding to the target bit line and corresponding to the erase state in write data to be programmed in memory cells connected to a third word line adjacent to the second word line; generating flip bit position data based on the target bits; generating flipped data by flipping target bits among the write data and flipping target neighboring bits included in the same chunk as the target bits; and programming the flipped data and the flip bit position data to the third word line, wherein the write data includes a plurality of chunks.

According to an embodiment of the present disclosure, a nonvolatile memory device can detect a pattern weak to lateral diffusion and perform an encoding operation to remove the weak pattern. Accordingly, a method of operating a nonvolatile memory device with enhanced reliability is provided.

FIG. 1 illustrates a nonvolatile memory device according to an embodiment of the present disclosure.
FIG. 2 is a circuit diagram showing a memory block according to one embodiment of the present disclosure.
FIG. 3 is a diagram for explaining the operation of a nonvolatile memory device according to one embodiment of the present disclosure.
FIGS. 4A and 4B are drawings for explaining lateral diffusion of a nonvolatile memory device according to one embodiment of the present disclosure.
FIGS. 5A and 5B are drawings for explaining an encoding operation according to one embodiment of the present disclosure.
FIG. 6 is a flowchart showing the operation of a nonvolatile memory device according to one embodiment of the present disclosure.
FIG. 7 is a flowchart showing the operation of a nonvolatile memory device according to one embodiment of the present disclosure.
FIGS. 8A to 8C are drawings for explaining the operation of a nonvolatile memory device according to one embodiment of the present disclosure.
FIG. 9 is a flowchart showing the operation of a nonvolatile memory device according to one embodiment of the present disclosure.
FIGS. 10A and 10B are drawings for explaining the operation of a nonvolatile memory device according to one embodiment of the present disclosure.
FIGS. 11A to 11D are drawings for explaining a first flip operation of a nonvolatile memory device according to one embodiment of the present disclosure.
FIGS. 12A and 12B are drawings for explaining a second flip operation of a nonvolatile memory device according to one embodiment of the present disclosure.
FIGS. 13A to 13G are drawings for explaining a write operation of a nonvolatile memory device according to an embodiment of the present disclosure.
FIG. 14 is a diagram for explaining a write operation of a nonvolatile memory device according to an embodiment of the present disclosure.
FIGS. 15A to 15C are drawings for explaining a read operation of a nonvolatile memory device according to an embodiment of the present disclosure.
FIG. 16 is a block diagram showing an SSD system to which a storage device according to the present disclosure is applied.
FIG. 17 is a drawing for explaining a memory device (500) according to an embodiment of the present invention.

Hereinafter, embodiments of the present disclosure will be described clearly and in detail to such an extent that a person skilled in the art can easily practice the present disclosure.

FIG. 1 illustrates a nonvolatile memory device according to an embodiment of the present disclosure.

Referring to FIG. 1, a nonvolatile memory device (100) may include a memory cell array (110), a row decoder (120), a page buffer circuit (130), an input/output circuit (140), a voltage generator (150), and a control logic circuit (160). Although not shown in FIG. 1, the nonvolatile memory device (100) may further include column logic, a pre-decoder, a temperature sensor, a command decoder, an address decoder, and the like. In one embodiment, the nonvolatile memory device (100) may be a nonvolatile memory device such as a NAND flash memory device, but the scope of the present disclosure is not limited thereto.

For example, the memory cell array (110) may be a core of a nonvolatile memory device (100). The row decoder (120), the page buffer circuit (130), the input/output circuit (140), and the control logic circuit (160) may be peripheral circuits of the nonvolatile memory device (100). The peripheral circuits may be configured to access the core.

The memory cell array (110) may include a plurality of memory blocks. Each of the plurality of memory blocks may include a plurality of memory cells. The memory cell array (110) may be connected to a page buffer circuit (130) through bit lines (BL) and may be connected to a row decoder (120) through word lines (WL), string select lines (SSL), and ground select lines (GSL). The configuration of each of the plurality of memory blocks is described in more detail with reference to FIG. 2.

In an exemplary embodiment, the memory cell array (110) may include a three-dimensional memory cell array, and the three-dimensional memory cell array may include a plurality of strings. Each string may include memory cells respectively connected to word lines vertically stacked on the substrate. U.S. Patent Publication No. 7,679,133, U.S. Patent Publication No. 8,553,466, U.S. Patent Publication No. 8,654,587, U.S. Patent Publication No. 8,559,235, and U.S. Patent Application Publication No. 2011/0233648 are herein incorporated by reference in their entirety.

The row decoder (120) can receive a row address (X-ADDR) from the control logic circuit (160). The row decoder (120) can decode the row address (X-ADDR) and, based on the decoding result, control or drive the voltages of the string select lines (SSL), the word lines (WL), and the ground select lines (GSL). For example, the row decoder (120) can provide a corresponding operating voltage to each of the string select lines (SSL), the word lines (WL), and the ground select lines (GSL), based on the decoding result.

The row decoder (120) can select one of a plurality of word lines (WL) and one of a plurality of string select lines (SSL) in response to a row address (X-ADDR). For example, during a program operation, the row decoder (360) can apply a program voltage and a program verify voltage to the selected word line, and during a read operation, the row decoder (360) can apply a read voltage to the selected word line.

The page buffer circuit (130) may be connected to the memory cell array (110) via bit lines (BL). The page buffer circuit (130) may select at least one bit line among the bit lines (BL) in response to a column address (Y-ADDR). The page buffer circuit (130) may operate as a write driver or a sense amplifier depending on the operation mode. For example, the page buffer circuit (130) may receive data (DATA) from the input/output circuit (140) and temporarily store the received data (DATA). The page buffer circuit (130) may control the voltage of the bit lines (BL) so that the temporarily stored data (DATA) is stored in the memory cell array (110). Alternatively, the page buffer circuit (130) may read the data (DATA) stored in the memory cell array (110) by detecting a voltage change of the bit lines (BL). The page buffer circuit (130) may transfer the read data (DATA) to the input/output circuit (140).

The page buffer circuit (130) may include a data latch (131) and a bit-level logic operation circuit (not shown). The page buffer circuit (130) may store data in the data latch (131). The data latch (131) may include first to fifth data latches. The page buffer circuit (130) may store a bitmap, data, etc. generated while performing a weak (or vulnerable) pattern detection operation or a flip operation on the data latch (131). The bit-level logic operation circuit may perform a logic operation on the data stored in the data latch.

The input/output circuit (140) can exchange data (DATA) with an external device (e.g., a storage controller). In one embodiment, the input/output circuit (140) can output data (DATA) to an external device or receive data (DATA) from an external device in synchronization with a data strobe signal.

The voltage generator (150) can generate various types of voltages for performing program, read, and erase operations based on a voltage control signal (CTRL_vol). For example, the voltage generator (150) can generate a program voltage, a read voltage, a program verify voltage, an erase voltage, etc. as a word line voltage (VWL).

The control logic circuit (160) can control various operations within the memory device (100) in general. The control logic circuit (160) can output various control signals in response to a command (CMD) and/or an address (ADDR) from a storage controller (not shown). For example, the control logic circuit (160) can output a voltage control signal (CTRL_vol), a row address (X-ADDR), and a column address (Y-ADDR).

The control logic circuit (160) may include an FBP engine (161), an ECC engine (162), and an FBP buffer (163). The FBP engine (161) may generate flip bit position (FBP; FLIP BIT POISION) data. The FBP engine (161) may generate a flip bit flag indicating a bit to be flipped, which is used for a flip operation or a re-flip operation.

The ECC engine (162) can perform an error detection and correction function for FBP data (or sub FBP data) received from the FBP buffer (163). For example, the ECC engine (126) can generate parity bits for FBP data (or sub FBP data) to be stored in the memory cell array (110). The generated parity bits can be stored in the memory cell array (110) together with the FBP data (or sub FBP data). Thereafter, during a decoding operation, the ECC engine (162) can correct errors in the encoded FBP data (or encoded sub FBP data) using the parity bits, and output the encoded FBP data (or encoded sub FBP data) whose errors have been corrected.

The FBP buffer (163) can store FBP data. The FBP buffer (163) can receive FBP data from the FBP engine (161). The FBP buffer (163) can store the received FBP data. The FBP data (163) can output the stored FBP data to the FBP engine (161) or the ECC engine (162).

A nonvolatile memory device (100) including a three-dimensional memory cell array causes lateral charge diffusion between memory cells sharing a charge capture layer. In particular, as charge diffusion is accelerated in a specific data pattern (or weak pattern), bit errors increase. A nonvolatile memory device (100) according to an embodiment of the present disclosure can remove a weak pattern by performing a weak pattern detection operation and an encoding operation. The weak pattern can include a first pattern (e.g., E-P7-E) or a second pattern (e.g., E-P6-E).

A weak pattern detection operation may refer to an operation of detecting a weak pattern to remove a weak pattern between vertically adjacent cells. The nonvolatile memory device (100) may detect a weak pattern based on data programmed in memory cells connected to first and second word lines programmed in the memory cell array (110) and write data to be programmed in memory cells connected to a third word line received by the nonvolatile memory device (100) before the last erase state (E) is programmed. The nonvolatile memory device (100) may prevent a weak pattern from occurring by converting data before a weak pattern occurs.

An encoding operation may refer to an operation of converting data to be programmed into a memory cell array (110). The encoding operation may include an FBP data generation operation and a flip operation. The FBP data generation operation may generate FBP data indicating bits to be flipped based on data programmed into memory cells connected to first and second word lines and write data to be programmed into memory cells connected to a third word line received in a nonvolatile memory device (100). The FBP data may be information about positions of flipped bits in flipped data generated by performing the flip operation.

A flip operation may refer to an operation of flipping write data based on FBP data. The flip operation may include a first flip operation and a second flip operation. The first flip operation may be performed in bit units, and the second flip operation may be performed in chunk units. The nonvolatile memory device (100) may perform the flip operation to generate flipped data. The nonvolatile memory device (100) may add FBP data to the flipped data to generate encoded data. The nonvolatile memory device (100) may program the encoded data into the memory cell array (110). The nonvolatile memory device (100) may perform a vulnerable pattern detection operation, an encoding operation, and a program operation in response to a write command.

The nonvolatile memory device (100) can perform a sensing operation and a decoding operation in response to a read command. The nonvolatile memory device (100) can perform a sensing operation to read encoded data. The nonvolatile memory device (100) can perform a decoding operation to convert encoded data into decoded data. The nonvolatile memory device (100) can perform a re-flip operation to flip flipped bits again. The nonvolatile memory device (100) can generate decoded data from which FBP data is removed.

As described above, the nonvolatile memory device according to the embodiment of the present disclosure can prevent errors due to a specific pattern of states of vertically adjacent memory cells. In addition, a nonvolatile memory device with improved reliability and a method of operating the nonvolatile memory device are provided. The vulnerable pattern detection operation, the encoding operation, and the decoding operation are described in more detail with reference to the drawings below.

FIG. 2 is a circuit diagram showing a memory block according to one embodiment of the present disclosure.

The memory block (BLKa) of FIG. 2 can be applied to the nonvolatile memory device of FIG. 1. The memory block (BLKa) of FIG. 2 can be an example of one of the memory blocks of FIG. 1. When the nonvolatile memory device of FIG. 1 is implemented with a flash memory of the 3D V-NAND type, each of the plurality of memory blocks constituting the storage module can be expressed by an equivalent circuit as illustrated in FIG. 1.

Referring to FIGS. 1 and 2, a plurality of cell strings (CS) may be arranged in rows and columns on a substrate (SUB). A memory block (BLKa) represents a three-dimensional memory block formed in a three-dimensional structure on the substrate (SUB). For example, a plurality of cell strings (CS) included in the memory block (BLKa) may be formed in a direction perpendicular to the substrate. The plurality of cell strings (CS) may be connected between bit lines and a common source line (CSL). The plurality of cell strings (CS) may be commonly connected to a common source line (CSL) formed on (or in) the substrate (SUB). In FIG. 2, the position of the substrate (SUB) is exemplarily shown to help understand the structure of the memory block (BLKa).

In FIG. 2, a common source line (CSL) is illustrated as being connected to the bottom of the cell strings (CS). However, the common source line (CSL) is sufficiently electrically connected to the bottom of the cell strings (CS), and is not limited to being physically located at the bottom of the cell strings (CS). For example, in FIG. 2, the cell strings (CS) are illustrated as being arranged in a 4X4 array, but the memory block (BLKa) may include a smaller or larger number of cell strings.

The cell strings of each row can be commonly connected to a ground select line (GSL1 or GSL2). For example, the cell strings of the first and second rows can be commonly connected to the first ground select line (GSL1), and the cell strings of the third and fourth rows can be commonly connected to the second ground select line (GSL2).

The cell strings of each row can be connected to corresponding string selection lines among the first to fourth string selection lines (SSL1 to SSL4). The cell strings of each column can be connected to corresponding bit lines among the first to fourth bit lines (BL1 to BL4). To avoid complicating the drawing, the cell strings connected to the second and third string selection lines (SSL2, SSL3) are depicted in a faint manner.

Each cell string may include at least one ground select transistor (GST) connected to a ground select line (GSL1 or GSL2), a plurality of memory cells (MC1 to MC8) each connected to a plurality of word lines (WL1 to WL8), and string select transistors (SST) each connected to a string select line (SSL1, SSL2, SSL3 or SSL4).

In each cell string, a ground select transistor (GST), memory cells (MC1 to MC8), and string select transistors (SST) may be connected in series along a direction perpendicular to a substrate (SUB) and sequentially stacked along a direction perpendicular to the substrate (SUB). In each cell string (CS), at least one of the memory cells (MC1 to MC8) may be used as a dummy memory cell. The dummy memory cell may be unprogrammed (e.g., program inhibited) or programmed differently from the memory cells (MC1 to MC8).

For example, memory cells of cell strings of each row located at the same height can form one physical page. Memory cells of one physical page can be connected to one sub-word line. Sub-word lines of physical pages located at the same height can be commonly connected to one word line (one of WL1 to WL8).

For example, sub-word lines of physical pages positioned at the same height may be connected to each other at the height at which the sub-word lines are formed. As another example, sub-word lines of physical pages positioned at the same height may be indirectly connected to each other at another layer having a different height from the height at which the sub-word lines are formed, such as a metal layer.

For example, when implementing a memory block (BLKa) in a three-dimensional structure, the characteristics of the memory cells (MC) may be implemented differently depending on the height of the memory cells (MC). For example, the sizes of the memory cells (MC) may be different depending on the height of the memory cells (MC).

FIG. 3 is a diagram for explaining the operation of a nonvolatile memory device according to one embodiment of the present disclosure.

Referring to FIG. 3, a threshold voltage distribution diagram of a memory cell and a table of bits per page corresponding to the threshold voltage distribution are illustrated. The horizontal axis of the distribution diagram of FIG. 3 indicates threshold voltages of memory cells, and the vertical axis indicates the number of memory cells. For example, changes in threshold voltages when 3 bits are written to each memory cell are illustrated in FIG. 3. A word line (WL) can store first to third page data (PD1, PD2, PD3). The first page data (PD1) can indicate a least significant bit (LSB) page, the second page data (PD2) can indicate a center significant bit (CSB) page, and the third page data (PD3) can indicate a most significant bit (MSB) page.

A nonvolatile memory device (100) can store or program data in memory cells by converting threshold voltages of a plurality of memory cells (MC) included in a memory cell array (110). Memory cells connected to a word line (WL) can be programmed to have an erase state (E) and one of first to seventh program states (P1 to P7).

The first read voltage (VRD1) may be a voltage for distinguishing between the erase state (E) and the first program state (P1). The second read voltage (VRD1) may be a voltage for distinguishing between the first program state (P1) and the second program state (P2). The third read voltage (VRD3) may be a voltage for distinguishing between the second program state (P2) and the third program state (P3). The fourth read voltage (VRD4) may be a voltage for distinguishing between the third program state (P3) and the fourth program state (P4). The fifth read voltage (VRD5) may be a voltage for distinguishing between the fourth program state (P4) and the fifth program state (P5). The sixth read voltage (VRD6) may be a voltage for distinguishing between the fifth program state (P5) and the sixth program state (P6). The seventh read voltage (VRD7) may be a voltage for distinguishing between the sixth program state (P6) and the seventh program state (P7).

For example, when the values of the page data (PD1, PD2, PD3) corresponding to the memory cell are [1, 1, 1], the memory cell can be programmed to have an erase state (E). When the values of the page data (PD1, PD2, PD3) corresponding to the memory cell are [0, 1, 1], the memory cell can be programmed to have a first program state (P1). When the values of the page data (PD1, PD2, PD3) corresponding to the memory cell are [0, 0, 1], the memory cell can be programmed to have a second program state (P2). When the values of the page data (PD1, PD2, PD3) corresponding to the memory cell are [0, 0, 0], the memory cell can be programmed to have a third program state (P3). When the values of the page data (PD1, PD2, PD3) corresponding to the memory cell are [0, 1, 0], the memory cell can be programmed to have a fourth program state (P4). When the values of the page data (PD1, PD2, PD3) corresponding to the memory cell are [1, 1, 0], the memory cell can be programmed to have a fifth program state (P5). When the values of the page data (PD1, PD2, PD3) corresponding to the memory cell are [1, 0, 0], the memory cell can be programmed to have a sixth program state (P6). When the values of the page data (PD1, PD2, PD3) corresponding to the memory cell are [1, 0, 1], the memory cell can be programmed to have a seventh program state (P7).

FIGS. 4A and 4B are drawings for explaining lateral diffusion of a nonvolatile memory device according to one embodiment of the present disclosure.

Referring to FIG. 4a, lateral spreading may occur in a nonvolatile memory device (100). Lateral spreading refers to a phenomenon in which charges captured in insulating films spread in a third direction or in a direction opposite to the third direction. When lateral spreading occurs, threshold voltages of memory cells may change, and data reliability may deteriorate.

In a nonvolatile memory device including a three-dimensional memory cell array, memory cells connected to the same bit line share a charge trapping layer. Accordingly, charges stored in a memory cell can easily move (or diffuse) to vertically adjacent neighboring cells to which the charge trapping layer is directly connected, and the charge loss rate can significantly increase.

In particular, when a memory cell corresponding to a first word line (WL1) among memory cells connected to the same bit line is in the erase state (E), a memory cell corresponding to a second word line (WL2) is in the seventh program state (P7) or the sixth program state (P6), and a memory cell corresponding to a third word line (WL3) is in the erase state (E), lateral diffusion may be accelerated. That is, when adjacent cells sharing a phone capture layer are in the erase state (E), the seventh program state (P7), and the erase state (E), or the erase state (E), the sixth program state (P6), and the erase state (E) in that order, the reliability of data may be significantly degraded.

Referring to FIG. 4b, it shows how the amount of threshold voltage shift is affected by the state of the adjacent cell. When the memory cell of the seventh program state (P7) and the sixth program state (P6) has an adjacent upper cell in an erase state (E) and an adjacent lower cell in an erase state (E), the amount of threshold voltage shift is the largest. That is, a data error may occur in a weak pattern, and the reliability of the nonvolatile memory device may be degraded. The nonvolatile memory device according to the embodiment of the present disclosure can improve reliability by removing a weak pattern by performing a weak pattern detection operation and an encoding operation.

FIGS. 5A and 5B are drawings for explaining an encoding operation according to one embodiment of the present disclosure.

FIG. 5a illustrates a programmed state without an encoding operation, and FIG. 5b illustrates a programmed state after performing an encoding operation according to one embodiment of the present disclosure.

For the sake of simplicity of the drawing and convenience of explanation, it is assumed that the memory cell array (110) includes a plurality of memory cells (MC11 to MC39) connected to first to third word lines (WL1 to WL3) and first to ninth bit lines (BL1 to BL9). However, the scope of the present disclosure is not limited thereto.

Referring to FIG. 1 and FIG. 5A, a memory cell array (110) may include a plurality of memory cells (MC11 to MC39). Each of the plurality of memory cells (MC11 to MC39) may be connected to word lines (WL1 to WL3) and bit lines (BL1 to BL9). Each of the plurality of memory cells (MC11 to MC39) may be connected to a row decoder (120) through the word lines (WL1 to WL3). Each of the plurality of memory cells (MC11 to MC39) may be connected to a page buffer circuit (130) through the bit lines (BL1 to BL9).

For example, a first word line (WL1) may be connected to memory cells (MC11 to MC19), a second word line (WL2) may be connected to memory cells (MC21 to MC29), and a third word line (WL3) may be connected to memory cells (MC31 to MC39). A first bit line (BL1) is connected to memory cells (MC11, MC21, MC31), a second bit line (BL2) is connected to memory cells (MC12, MC22, MC32), a third bit line (BL3) is connected to memory cells (MC13, MC23, MC33), a fourth bit line (BL4) is connected to memory cells (MC14, MC24, MC34), a fifth bit line (BL5) is connected to memory cells (MC15, MC25, MC35), a sixth bit line (BL6) is connected to memory cells (MC16, MC26, MC36), a seventh bit line (BL7) is connected to memory cells (MC17, MC27, MC37), an eighth bit line (BL8) is connected to memory cells (MC18, MC28, MC38), and a ninth bit line (BL9) is connected to memory cells (MC13, MC23, MC33). It can be connected to cells (MC19, MC29, MC39).

In one embodiment, a plurality of memory cells may be divided into a first area (AREA1) (e.g., a user area) and a second area (AREA2) (e.g., a spare area). For example, memory cells connected to the first to sixth bit lines (BL1 to BL6) may be a first area (AREA1), and memory cells connected to the seventh to ninth bit lines (BL7 to BL9) may be a second area (AREA2). User data provided from an external host may be stored in the first area (AREA1). Meta data, etc. may be stored in the second area (AREA2). The first area (AREA1) may be used by the external host, and the second area (AREA2) may not be used by the external host.

For example, a memory cell (MC11) may have an erase state (E), a memory cell (MC12) may have a fifth program state (P5), a memory cell (MC13) may have a seventh program state (P7), a memory cell (MC14) may have an erase state (E), a memory cell (MC15) may have a fourth program state (P4), and a memory cell (MC16) may have an erase state (E). A memory cell (MC21) may have a seventh program state (P7), a memory cell (MC22) may have a second program state (P2), a memory cell (MC23) may have a sixth program state (P6), a memory cell (MC24) may have a seventh program state (P7), a memory cell (MC25) may have a third program state (P3), and a memory cell (MC26) may have a sixth program state (P6). A memory cell (MC31) can have an erase state (E), a memory cell (MC32) can have a first program state (P1), a memory cell (MC33) can have a sixth program state (P6), a memory cell (MC34) can have an erase state (E), a memory cell (MC35) can have an erase state (E), and a memory cell (MC36) can have an erase state (E).

Since the memory cell (MC11) connected to the first bit line (BL1) is in an erased state (E), the memory cell (MC21) connected to the first bit line (BL1) is in a seventh program state (P7), and the memory cell (MC31) connected to the first bit line (BL1) is in an erased state (E), the memory cell array (110) can include a first weak pattern (W1) in the first bit line (BL1). Since the memory cell (MC14) connected to the fourth bit line (BL4) is in an erased state (E), the memory cell (MC24) connected to the fourth bit line (BL4) is in a seventh program state (P7), and the memory cell (MC34) connected to the fourth bit line (BL4) is in an erased state (E), the memory cell array (110) can include a second weak pattern (W2) in the fourth bit line (BL4). Since the memory cell (MC16) connected to the sixth bit line (BL6) is in an erased state (E), the memory cell (MC26) connected to the sixth bit line (BL6) is in a sixth program state (P6), and the memory cell (MC36) connected to the sixth bit line (BL6) is in an erased state (E), the memory cell array (110) can include a third weak pattern (W3) in the sixth bit line (BL6).

In other words, the nonvolatile memory device (100) may include weak patterns (W1 to W3). Accordingly, errors may occur and the reliability of the nonvolatile memory device may be degraded.

Referring to FIG. 1 and FIG. 5b, a memory cell (MC11) may have an erase state (E), a memory cell (MC12) may have a fifth program state (P5), a memory cell (MC13) may have a seventh program state (P7), a memory cell (MC14) may have an erase state (E), a memory cell (MC15) may have a fourth program state (P4), and a memory cell (MC16) may have an erase state (E). A memory cell (MC21) may have a seventh program state (P7), a memory cell (MC22) may have a second program state (P2), a memory cell (MC23) may have a sixth program state (P6), a memory cell (MC24) may have a seventh program state (P7), a memory cell (MC25) may have a third program state (P3), and a memory cell (MC26) may have a sixth program state (P6). A memory cell (MC31) may have a non-erased state (~E), a memory cell (MC32) may have a first program state (P1), a memory cell (MC33) may have a sixth program state (P6), a memory cell (MC34) may have a non-erased state (~E), a memory cell (MC35) may have an erased state (E), and a memory cell (MC36) may have a non-erased state (~E). The non-erased state (~E) refers to a state other than the erased state (E) and may refer to one of a plurality of program states (P1 to P7).

The nonvolatile memory device (100) according to the embodiment of the present disclosure can detect a weak pattern and convert and store write data by performing a weak pattern detection operation and an encoding operation before performing a program operation for a third word line (WL3). That is, the nonvolatile memory device (100) can store flipped data. The memory cells (MC31, MC34, MC36) can have a non-erased state (~E). Accordingly, the memory cell array (110) may not include weak patterns. The reliability of the nonvolatile memory device can be improved.

In one embodiment, memory cells (MC34, MC35, M336) connected to the third word line can store FBP data (FBP). The FBP data can point to the positions of flipped bits in the flipped data. The FBP data can be used to re-flip the flipped data when performing a read operation.

That is, the memory cells (MC31, MC34, MC36) of FIG. 5A may have an erased state (E), while the memory cell array (110) may include weak patterns (W1, W2, W3). On the other hand, the memory cells (MC31, MC34, MC36) of FIG. 5B may have a non-erased state (~E), while the memory cell array (110) may not include a weak pattern. The nonvolatile memory device (100) may perform an encoding operation to remove a weak pattern. The nonvolatile memory device (100) may perform a weak pattern detection operation to detect a weak pattern before programming data to the third word line (WL3). The nonvolatile memory device (100) may perform the weak pattern detection operation based on data stored in the first word line (WL1), data stored in the second word line (WL2), and write data to be programmed to the third word line (WL3) stored in the page buffer. When a weak pattern is detected through a weak pattern detection operation, the nonvolatile memory device (100) can perform an encoding operation on the write data. The nonvolatile memory device (100) can change (or convert, modify) the write data to be programmed in the third word line (WL3) by performing the encoding operation. The nonvolatile memory device (100) can change one of the erase states included in the weak pattern to a non-erased state.

FIG. 6 is a flowchart showing the operation of a nonvolatile memory device according to one embodiment of the present disclosure.

Referring to FIGS. 1 and 6, at step S10, the nonvolatile memory device (100) can perform a weak pattern detection operation. The nonvolatile memory device (100) can detect a weak pattern based on data stored in a first word line (WL1), data stored in a second word line (WL2), and data to be stored in a third word line (WL3).

The second word line (WL2) is adjacent to the first word line (WL1), and the third word line (WL3) is adjacent to the second word line (WL2). The memory cells connected to the first word line (WL1) are in a state where data is stored, that is, the memory cells connected to the first word line (WL1) can have either an erased state (E) or one of a plurality of program states (P1 to P7). The memory cells connected to the second word line (WL2) are in a state where data is stored, that is, the memory cells connected to the second word line (WL2) can have either an erased state (E) or one of a plurality of program states (P1 to P7). The memory cells connected to the third word line (WL3) are in a state where data is not stored, that is, the memory cells connected to the third word line (WL3) can have an erased state (E). The nonvolatile memory device (100) can detect a first pattern (e.g., E-P7-E) or a second pattern (e.g., E-P6-E).

In step S20, the nonvolatile memory device (100) can perform an encoding operation. In one embodiment, the nonvolatile memory device (100) can generate FBP data (FBP) and convert write data based on the FBP data. That is, the encoding operation can include an FBP data generation operation and a flip operation. The nonvolatile memory device (100) can convert write data (or user data) and add FBP data to the user data by performing the encoding operation. The nonvolatile memory device (100) can perform an encoding operation on the first write data (WD1) to generate second write data (WD2). The second write data (WD2) can include the flipped first write data (WD1) and the FBP data.

For example, the nonvolatile memory device (100) can convert data to be programmed in the third word line (WL3). The nonvolatile memory device (100) can convert the data so that memory cells corresponding to the target bits are in a non-erased state in order to remove a weak pattern. The nonvolatile memory device (100) can flip or invert the target bits based on the FBP data (FBP) to generate flipped data. The nonvolatile memory device (100) can add the FBP data to the flipped data to generate encoded data (i.e., the second write data (WD2)).

At step S30, the nonvolatile memory device (100) can perform a program operation. The nonvolatile memory device (100) can program the flipped data and the FBP data (FBP). The nonvolatile memory device (100) can store the flipped data and the FPB data (FBP) in the third word line (WL3). That is, the nonvolatile memory device (100) can program the encoded data (i.e., the second write data (WD2)). The nonvolatile memory device (100) can store the flipped data in the first area, and store the FBP data (FBP) in the second area. For example, the nonvolatile memory device (100) can program the flipped data in memory cells corresponding to the first area (AREA1) of the third word line (WL3), and program the FBP data in memory cells corresponding to the second area (AREA2) of the third word line (WL3).

FIG. 7 is a flowchart showing the operation of a nonvolatile memory device according to an embodiment of the present disclosure. FIGS. 8A to 8C are drawings for explaining the operation of a nonvolatile memory device according to an embodiment of the present disclosure.

Referring to FIG. 8A, the memory cell array (110) may include a plurality of memory cells (MC11 to MC3n) connected to first to third word lines (WL1 to WL3) and first to n-th bit lines (BL1 to BLn). The memory cells connected to the first to k-th bit lines (BL1 to BLk) may be a first area (AREA1), and the memory cells connected to the k+1-th to n-th bit lines (BLk+1 to BLn) may be a second area (AREA2). The memory cells connected to the first word line (WL1) may be in a state in which programming has been completed, the memory cells connected to the second word line (WL2) may be in a state in which programming has been completed, and the memory cells connected to the third word line (WL3) may be in a state before being programmed after erasing.

For example, a memory cell (MC11) may have an erase state (E), a memory cell (MC12) may have a fifth program state (P5), a memory cell (MC13) may have a seventh program state (P7), a memory cell (MC14) may have an erase state (E), a memory cell (MC15) may have a fourth program state (P4), a memory cell (MC16) may have an erase state (E), and a memory cell (MC1k) may have a seventh program state (P7). A memory cell (MC21) can have a seventh program state (P7), a memory cell (MC22) can have a second program state (P2), a memory cell (MC23) can have a sixth program state (P6), a memory cell (MC24) can have a seventh program state (P7), a memory cell (MC25) can have a third program state (P3), a memory cell (MC26) can have a sixth program state (P6), and a memory cell (MC2k) can have a fifth program state (P5). The memory cells (MC31 to MC3k) connected to the third word line (WL3) can have an erase state (E).

Referring to FIGS. 1, 7, and 8A to 8C, at step S110, the nonvolatile memory device (100) can detect first memory cells having an erase state (E) in the first word line (WL1). For example, the nonvolatile memory device (100) can check the first word line (WL1) (①). The nonvolatile memory device (100) can detect memory cells having an erase state in the first area (AREA1) of the first word line (WL1) to find a weak pattern. The nonvolatile memory device (100) can sense the first word line (WL1) and detect the first memory cells (MC11, MC14, MC16) having the erase state (E). That is, the first memory cells may include memory cells (MC11, MC14, MC16) among the memory cells (MC11 to MC1k) connected to the first word line (WL1).

At step S120, the nonvolatile memory device (100) can detect second memory cells having a sixth program state (P6) or a seventh program state (P7) in the second word line (WL2). For example, the nonvolatile memory device (100) can check the second word line (WL2) (②). In order to find a weak pattern, the nonvolatile memory device (100) can detect memory cells having a sixth program state (P6) or a seventh program state (P7) in the first area (AREA1) of the second word line (WL2). The nonvolatile memory device (100) can sense the second word line (WL2) to detect second memory cells (MC21, MC23, MC24, MC26) having the sixth program state (P6) or the seventh program state (P7). That is, the second memory cells may include memory cells (MC21, MC23, MC24, MC26) among the memory cells (MC21 to MC2k) connected to the second word line (WL2).

In step S130, the nonvolatile memory device (100) can detect target bit lines including both the first memory cell and the second memory cell. For example, the nonvolatile memory device (100) can check the target bit lines (③). Since the memory cell (MC11) of the nonvolatile memory device (100) is a first memory cell and the memory cell (MC21) is a second memory cell, the nonvolatile memory device (100) can detect the first bit line (BL1) as the target bit line. Since the memory cell (MC14) of the nonvolatile memory device (100) is a first memory cell and the memory cell (MC24) is a second memory cell, the nonvolatile memory device (100) can detect the fourth bit line (BL4) as the target bit line. Since the memory cell (MC16) of the nonvolatile memory device (100) is a first memory cell and the memory cell (MC26) is a second memory cell, the nonvolatile memory device (100) can detect the sixth bit line (BL6) as the target bit line. That is, the nonvolatile memory device (100) can detect the first bit line (BL1), the fourth bit line (BL4), and the sixth bit line (BL6) as target bit lines.

In step S140, the nonvolatile memory device (100) can detect target bits corresponding to the target bit line and corresponding to the erase state. For example, the page buffer circuit (130) can receive first write data (WD1) from the input/output circuit (140) (④). The page buffer circuit (130) can store the first write data (WD1) in the data latch (131). The page buffer circuit (130) can confirm the first write data (WD1) (⑤).

Referring to FIG. 8B, the first write data (WD1) may include first to third page data (PD1, PD2, PD3). A first bit (B1) of the first page data (PD1) may be '1', a second bit (B2) of the first page data (PD1) may be '0', a third bit (B3) of the first page data (PD1) may be '1', a fourth bit (B4) of the first page data (PD1) may be '1', a fifth bit (B5) of the first page data (PD1) may be '1', a sixth bit (B6) of the first page data (PD1) may be '1', and a kth bit (Bk) of the first page data (PD1) may be '1'. The first bit (B1) of the second page data (PD2) may be '1', the second bit (B2) of the second page data (PD2) may be '1', the third bit (B3) of the second page data (PD2) may be '0', the fourth bit (B4) of the second page data (PD2) may be '1', the fifth bit (B5) of the second page data (PD2) may be '1', the sixth bit (B6) of the second page data (PD2) may be '1', and the kth bit (Bk) of the second page data (PD2) may be '0'. The first bit (B1) of the third page data (PD3) may be '1', the second bit (B2) of the third page data (PD3) may be '1', the third bit (B3) of the third page data (PD3) may be '0', the fourth bit (B4) of the third page data (PD3) may be '1', the fifth bit (B5) of the third page data (PD3) may be '1', the sixth bit (B6) of the third page data (PD3) may be '1', and the k-th bit (Bk) of the third page data (PD3) may be '1'. That is, the value of the portion corresponding to the first area (AREA1) of the first page data (PD1) (or the user data of the first page data (PD1)) may be a k-bit stream [101111 1], and the value of the part corresponding to the first area (AREA1) of the second page data (PD2) (or the user data of the second page data (PD2)) is a k bit stream [110111 0], and the value of the part corresponding to the first area (AREA1) of the third page data (PD3) (or the user data of the third page data (PD3)) is a k bit stream [110111 1] It could be.

The values of page data (PD1, PD2, PD3) corresponding to the memory cell may be referred to as bit data. The first bit data (BD1) refers to the values of the page data (PD1, PD2, PD3) corresponding to the memory cell connected to the first bit line (BL1), and the second bit data (BD2) refers to the values of the page data (PD1, PD2, PD3) corresponding to the memory cell connected to the second bit line (BL2). The remaining bit data (BD3 to BDn) are the same, and therefore, a detailed description is omitted. The first to k-th bit data (BD1 to BDk) may be data to be stored in the first area (AREA1), and the k+1 to n-th bit data (BDk+1 to BDn) may be data to be stored in the second area (AREA2). The first to kth bit data (BD1 to BDk) can correspond to user data, and the k+1 to nth bit data (BDk+1 to BDn) can correspond to metadata.

For example, the first bit data (BD1) may be [1, 1, 1], the second bit data (BD2) may be [0, 1, 1], the third bit data (BD3) may be [1, 0, 0], the fourth bit data (BD4) may be [1, 1, 1], the fifth bit data (BD5) may be [1, 1, 1], the sixth bit data (BD6) may be [1, 1, 1], and the k-th bit data (BDk) may be [1, 0, 1]. The first bit data (BD1) may correspond to an erase state (E), the second bit data (BD2) may correspond to a first program state (P1), the third bit data (BD3) may correspond to a sixth program state (P6), the fourth bit data (BD4) may correspond to an erase state (E), the fifth bit data (BD5) may correspond to an erase state (E), the sixth bit data (BD6) may correspond to an erase state (E), and the k-th bit data (BDk) may correspond to a seventh program state (BD7).

A nonvolatile memory device (100) can detect target bit data corresponding to target bit lines (BL1, BL4, BL6) and corresponding to an erase state (E) among a plurality of bit data (BD1 to BDk) of a first area (AREA1). The nonvolatile memory device (100) can detect target bits corresponding to the target bit data.

For example, since the first bit data (BD1) corresponds to the target bit line (BL1) and the first bit data (BD1) corresponds to the erase state (E), the first bit data (BD1) is target bit data, and the first bit (B1) corresponding to the first bit data (BD1) is a target bit. Since the second bit data (BD2) does not correspond to one of the target bit lines and is in the first program state (P1), the second bit (B2) is not a target bit. Since the third bit data (BD3) does not correspond to one of the target bit lines and is in the sixth program state (P6), the third bit (B3) is not a target bit. Since the fourth bit data (BD4) corresponds to the target bit line (BL4) and corresponds to the erase state (E), the fourth bit data (BD4) is target bit data, and the fourth bit (B4) corresponding to the fourth bit data (BD4) is a target bit. The fifth bit data (BD5) is in an erased state (E) but does not correspond to one of the target bit lines, so the fifth bit (B5) is not a target bit. The sixth bit data (BD6) corresponds to the target bit line (BL6) and corresponds to the erased state (E), so the sixth bit data (BD6) is target bit data, and the sixth bit (B6) corresponding to the sixth bit data (BD6) is a target bit. The k-th bit data (BDk) does not correspond to one of the target bit lines and is in a seventh program state (P7), so the k-th bit (Bk) is not a target bit. That is, the nonvolatile memory device (100) can detect the target bits (B1, B4, B6).

At step S150, the nonvolatile memory device (100) can generate FBP data based on the target bits. The control logic circuit (160) can generate FBP data based on the target bits. The FBP data can include information about the positions of the target bits. For example, the FBP data can include information indicating the target bits (B1, B4, B6). The control logic circuit (160) can transmit the FBP data to the page buffer circuit (130) (⑥).

In step S160, the nonvolatile memory device (100) can flip or invert target bits based on the FBP data to generate flipped data (⑦). For example, the page buffer circuit (130) can flip the first bit data (BD1), the fourth bit data (BD4), and the sixth bit data (BD6) in response to the FBP data to convert them to correspond to a non-erased state (~E). The page buffer circuit (130) can flip the target bits to generate flipped data. The page buffer circuit (130) can set the FBP data to the value of the k+1-th bit data (BDk+1) to the n-th bit data (BDn) corresponding to the second area (AREA2). In the present disclosure, the k+1-th bit data (BDk+1) to the n-th bit data (BDn) may include FBP data, but the scope of the present disclosure is not limited thereto. The k+1-th bit data (BDk+1) to the n-th bit data (BDn) may further include metadata.

At step S170, the nonvolatile memory device (100) can program the flipped data and FBP data to the third word line (WL3) (⑧). That is, the nonvolatile memory device (100) can store the second write data (WD2) including the flipped data and FBP data in the memory cells connected to the third word line (WL3). For example, the row decoder (120) can apply a program voltage and a program verification voltage to the third word line (WL3). The page buffer circuit (130) can control the voltage of the bit lines (BL) so that the write data (WD) is stored in the third word line (WL3).

The program result, the flipped data, and the FBP data may be stored in the third word line (WL3). The flipped data may be stored in the first area (AREA1) of the third word line (WL3), and the FBP data may be stored in the second area (AREA2) of the third word line (WL3). For example, the memory cell (MC31) may have a non-erased state (~E), the memory cell (MC32) may have a first program state (P1), the memory cell (MC33) may have a sixth program state (P6), the memory cell (MC34) may have a non-erased state (~E), the memory cell (MC35) may have an erased state (E), the memory cell (MC36) may have a non-erased state (~E), and the memory cell (MC3k) may have a seventh program state (P7). That is, memory cells (MC31 to MC3k) can store flipped data (or flipped user data). Memory cells (MC3k+1 to MC3n) can store FBP data.

FIG. 9 is a flowchart showing the operation of a nonvolatile memory device according to one embodiment of the present disclosure. FIGS. 10A and 10B are drawings for explaining the operation of a nonvolatile memory device according to one embodiment of the present disclosure.

For convenience of explanation, detailed descriptions of the components illustrated in FIGS. 8A to 8C are omitted. Referring to FIGS. 9, 10A and 10B, memory cells connected to the first word line (WL1) may be in a program-completed state, memory cells connected to the second word line (WL2) may be in a program-completed state, and memory cells connected to the third word line (WL3) may be in a program-completed state.

For example, a memory cell (MC11) may have an erase state (E), a memory cell (MC12) may have a fifth program state (P5), a memory cell (MC13) may have a seventh program state (P7), a memory cell (MC14) may have an erase state (E), a memory cell (MC15) may have a fourth program state (P4), a memory cell (MC16) may have an erase state (E), and a memory cell (MC1k) may have a seventh program state (P7). A memory cell (MC21) can have a seventh program state (P7), a memory cell (MC22) can have a second program state (P2), a memory cell (MC23) can have a sixth program state (P6), a memory cell (MC24) can have a seventh program state (P7), a memory cell (MC25) can have a third program state (P3), a memory cell (MC26) can have a sixth program state (P6), and a memory cell (MC2k) can have a fifth program state (P5). A memory cell (MC31) can have a non-erased state (~E), a memory cell (MC32) can have a first program state (P1), a memory cell (MC33) can have a sixth program state (P6), a memory cell (MC34) can have a non-erased state (~E), a memory cell (MC35) can have an erased state (E), a memory cell (MC36) can have a non-erased state (~E), and a memory cell (MC3k) can have a seventh program state (P7).

At step S210, the nonvolatile memory device (100) can read the flipped data and FBP data from the third word line (WL3) in response to the read command (⑨). The nonvolatile memory device (100) can perform a read operation. For example, the row decoder (120) can apply a read voltage to the third word line (WL3). The page buffer circuit (130) can detect a voltage change of the bit lines (BL) and store the read data (RD) in the data latch (131).

For example, the nonvolatile memory device (100) may store read data stored in the third word line (WL3) in the data latch (131). As a result of performing the read operation, read data (RD) may be stored in the page buffer circuit (130). The read data (RD) may include first to n-th bit data (BD1 to BDn). The first bit data (BD1) may correspond to a non-erased state (~E), the second bit data (BD2) may correspond to a first program state (P1), the third bit data (BD3) may correspond to a sixth program state (P6), the fourth bit data (BD4) may correspond to a non-erased state (~E), the fifth bit data (BD5) may correspond to an erased state (E), the sixth bit data (BD6) may correspond to a non-erased state (~E), and the k-th bit data (BDk) may correspond to a seventh program state (P7).

The page buffer circuit (130) can output FBP data to the control logic circuit (160) (⑩). The control logic circuit (160) can determine the positions of flipped bits based on the FBP data. The control logic circuit (160) can transmit a flip bit flag to the page buffer circuit (130).

At step S220, the nonvolatile memory device (100) can flip the flipped bits of the flipped data again. The nonvolatile memory device (100) can perform a decoding operation based on the FBP data to generate decoded data. The nonvolatile memory device (100) can perform a re-flip operation based on the FBP data. The nonvolatile memory device (100) can flip the flipped bits again to remove a weak pattern. The nonvolatile memory device (100) can flip the flipped bits of the flipped data based on the FBP data to generate decoded data. The nonvolatile memory device (100) can transmit the decoded data to an external storage controller.

For example, the page buffer circuit (130) can perform a re-flip operation based on a flip bit flag (⑪). The page buffer circuit (130) can convert data corresponding to a non-erased state (~E) into data corresponding to an erased state (E). Accordingly, the first bit data (BD1) can correspond to the erased state (E), the second bit data (BD2) can correspond to the first program state (P1), the third bit data (BD3) can correspond to the sixth program state (P6), the fourth bit data (BD4) can correspond to the erased state (E), the fifth bit data (BD5) can correspond to the erased state (E), the sixth bit data (BD6) can correspond to the erased state (E), and the k-th bit data (BDk) can correspond to the seventh program state (P7). The page buffer circuit (130) can output the read data (RD) to the input/output circuit (140) (⑫).

FIGS. 11A to 11D are drawings for explaining a first flip operation of a nonvolatile memory device according to one embodiment of the present disclosure.

For the sake of simplicity of the drawing and convenience of explanation, it is assumed that the memory cell array (110) includes a plurality of memory cells (MC11 to MC39) connected to first to third word lines (WL1 to WL3) and first to ninth bit lines (BL1 to BL9). However, the scope of the present disclosure is not limited thereto. In addition, detailed descriptions of the components described above are omitted.

For example, memory cells connected to the first to sixth bit lines (BL1 to BL6) may be a first area (AREA1), and memory cells connected to the seventh to ninth bit lines (BL7 to BL9) may be a second area (AREA2). Memory cell (MC11) may have an erase state (E), memory cell (MC12) may have a fifth program state (P5), memory cell (MC13) may have a seventh program state (P7), memory cell (MC14) may have an erase state (E), memory cell (MC15) may have a fourth program state (P4), and memory cell (MC16) may have an erase state (E). A memory cell (MC21) can have a seventh program state (P7), a memory cell (MC22) can have a second program state (P2), a memory cell (MC23) can have a sixth program state (P6), a memory cell (MC24) can have a seventh program state (P7), a memory cell (MC25) can have a third program state (P3), and a memory cell (MC26) can have a sixth program state (P6). Memory cells (MC31 to MC36) of a first area (AREA1) connected to a third word line (WL3) can have an erase state (E).

In one embodiment, the first area (AREA1) may be divided into a plurality of portions (S1 to S3). The first area (AREA1) may include first to third portions (S1 to S3). For example, the number of the plurality of portions may be equal to the number of bits stored in the cell. When the plurality of memory cells (MC11 to MC39) are triple level cells (TLCs) that store information corresponding to three bits, the first area (AREA1) may be divided into three portions. The first portion (S1) may include memory cells connected to the first and second bit lines (BL1, BL2), the second portion (S2) may include memory cells connected to the third and fourth bit lines (BL3, BL4), and the third portion (S3) may include memory cells connected to the fifth and sixth bit lines (BL5, BL6). Alternatively, the first portion (S1) may correspond to the first and second bit lines (BL1, BL2), the second portion (S2) may correspond to the third and fourth bit lines (BL3, BL4), and the third portion (S3) may correspond to the fifth and sixth bit lines (BL5, BL6).

The page buffer circuit (130) can receive the first write data (WD1). The page buffer circuit (130) can store the first write data (WD1) in the data latch (131). The first write data (WD1) can include first to third page data (PD1 to PD3). Similar to FIG. 8B, a value of a portion corresponding to the first area (AREA1) of the first page data (PD1) (or user data of the first page data (PD1)) can be [101111], a value of a portion corresponding to the first area (AREA1) of the second page data (PD2) (or user data of the second page data (PD2)) can be [110111], and a value of a portion corresponding to the first area (AREA1) of the third page data (PD3) (or user data of the third page data (PD3)) can be [110111].

The first bit data (BD1) may correspond to an erase state (E), the second bit data (BD2) may correspond to a first program state (P1), the third bit data (BD3) may correspond to a sixth program state (P6), the fourth bit data (BD4) may correspond to an erase state (E), the fifth bit data (BD5) may correspond to an erase state (E), and the sixth bit data (BD6) may correspond to an erase state (E).

Referring to FIG. 11b, when a weak pattern is detected in the first portion (S1), the nonvolatile memory device (100) can convert (or flip) the bit data (BD) corresponding to the erase state (E) to the bit data (BD) corresponding to the first program state (P1). That is, when target bits are detected in the bits (B1, B2) corresponding to the first portion (S1), they can be changed from [1, 1, 1] to [0, 1, 1]. That is, the nonvolatile memory device (100) can flip the target bit corresponding to the first portion (S1) to the data corresponding to the first page data (PD1) (e.g., the LSB page).

When a weak pattern is detected in the second portion (S2), the nonvolatile memory device (100) can convert (or flip) the bit data (BD) corresponding to the erase state (E) to the bit data (BD) corresponding to the seventh program state (P7). That is, when target bits are detected in the bits (B1, B2) corresponding to the second portion (S2), they can be changed from [1, 1, 1] to [1, 0, 1]. That is, the nonvolatile memory device (100) can flip the target bit corresponding to the second portion (S2) to the data corresponding to the second page data (PD2) (e.g., the CSB page).

If a weak pattern is detected in the third portion (S3), the nonvolatile memory device (100) can convert (or flip) the bit data (BD) corresponding to the erase state (E) to the bit data (BD) corresponding to the fifth program state (P5). That is, if target bits are detected in the bits (B1, B2) corresponding to the third portion (S3), they can be changed from [1, 1, 1] to [1, 1, 0]. That is, the nonvolatile memory device (100) can flip the target bit corresponding to the third portion (S3) to the data corresponding to the third page data (PD3) (e.g., the MSB page).

Referring again to FIG. 11A, the nonvolatile memory device (100) can perform an encoding operation on the first write data (WD1) to generate the second write data (WD2). The nonvolatile memory device (100) can perform a flip operation on data corresponding to the first area (AREA1) of the first write data (WD1) to generate the flipped first write data (WD1). The nonvolatile memory device (100) can add FBP data to the flipped first write data (WD1) to generate the second write data (WD2).

The nonvolatile memory device (100) can detect the first memory cells (MC11, MC14, MC16) by sensing the first word line (WL1). The nonvolatile memory device (100) can detect the second memory cells (MC21, MC23, MC24, MC26) by sensing the second word line (WL2). The nonvolatile memory device (100) can detect the target bit lines based on the first memory cells (MC11, MC14, MC16) and the second memory cells (MC21, MC23, MC24, MC26). Since the first bit line (BL1) includes the first memory cell (MC11) and the second memory cell (MC21), the nonvolatile memory device (100) can detect the first bit line (BL1) as the target bit line. Since the fourth bit line (BL4) includes the first memory cell (MC14) and the second memory cell (MC24), the nonvolatile memory device (100) can detect the fourth bit line (BL4) as a target bit line. Since the sixth bit line (BL6) includes the first memory cell (MC16) and the second memory cell (MC26), the nonvolatile memory device (100) can detect the sixth bit line (BL6) as a target bit line.

If it is determined that the bit data (BD) corresponding to the target bit line corresponds to the erase state, the nonvolatile memory device (100) can determine the bit corresponding to the bit data (BD) as the target bit. The nonvolatile memory device (100) can check the bit data (BD) of the target bit lines (BL1, BL4, BL6). Since the first bit data (BD1) corresponding to the first bit line (BL1) corresponds to the erase state (E), the nonvolatile memory device (100) can determine the first bit (B1) as the target bit. Since the fourth bit data (BD4) corresponding to the fourth bit line (BL4) corresponds to the erase state (E), the nonvolatile memory device (100) can determine the fourth bit (B4) as the target bit. Since the sixth bit data (BD6) corresponding to the sixth bit line (BL6) corresponds to the erase state (E), the nonvolatile memory device (100) can determine the sixth bit (B6) as the target bit. That is, the nonvolatile memory device (100) can detect the target bits (B1, B4, B6).

The target bits may include first to third sub-target bits (STB1, STB2, STB3). Alternatively, the target bits may be divided into first to third sub-target bits (STB1, STB2, STB3). The first sub-target bits (STB1) may indicate bits corresponding to a first portion (S1) of the target bits, the second sub-target bits (STB2) may indicate bits corresponding to a second portion (S2) of the target bits, and the third sub-target bits (STB3) may indicate bits corresponding to a third portion (S3) of the target bits. The target bits and the sub-target bits may be as shown in Table 1.

TB STB1 B1 STB2 B4 STB3 B6

Referring to Table 1, the target bits (TB) may include first, fourth, and sixth bits (B1, B4, B6). The first sub-target bits (STB1) may include a first bit (B1), the second sub-target bits (STB2) may include a fourth bit (B4), and the third sub-target bits (STB3) may include a sixth bit (B6). The nonvolatile memory device (100) may perform an encoding operation based on the target bits. The nonvolatile memory device (100) may flip the target bits to generate flipped first write data. The nonvolatile memory device (100) may add FBP data to the flipped first write data to generate second write data (WD2).

Since the first bit (B1) corresponds to the first portion (S1) (i.e., the first bit line (BL1) corresponding to the first bit (B1) is included in the first portion (S1)), the nonvolatile memory device (100) can convert the erase state (E) into the first program state (P1). That is, the nonvolatile memory device (100) can flip the first bit (B1) of the first page data (PD1). For example, the nonvolatile memory device (100) can flip the first bit (B1) of the first page data (PD1) from '1' to '0'.

Since the fourth bit (B4) corresponds to the second portion (S2) (i.e., the fourth bit line (BL4) corresponding to the fourth bit (B4) is included in the second portion (S2)), the nonvolatile memory device (100) can convert the erase state (E) to the seventh program state (P7). That is, the nonvolatile memory device (100) can flip the fourth bit (B4) of the second page data (PD2). For example, the nonvolatile memory device (100) can flip the fourth bit (B4) of the second page data (PD2) from '1' to '0'.

Since the sixth bit (B6) corresponds to the third portion (S3) (i.e., the sixth bit line (BL6) corresponding to the sixth bit (B6) is included in the third portion (S3)), the nonvolatile memory device (100) can convert the erase state (E) into the fifth program state (P5). That is, the nonvolatile memory device (100) can flip the sixth bit (B6) of the third page data (PD3). For example, the nonvolatile memory device (100) can flip the sixth bit (B6) of the third page data (PD3) from '1' to '0'.

In one embodiment, the nonvolatile memory device (100) can flip the first sub-target bits (STB1) in the first page data (PD1). Alternatively, the nonvolatile memory device (100) can flip data corresponding to the first sub-target bits (STB1) in the first page data (PD1). The nonvolatile memory device (100) can flip the second sub-target bits (STB2) in the second page data (PD2). Alternatively, the nonvolatile memory device (100) can flip data corresponding to the second sub-target bits (STB2) in the second page data (PD2). The nonvolatile memory device (100) can flip the third sub-target bits (STB3) in the third page data (PD3). Alternatively, the nonvolatile memory device (100) can flip data corresponding to the third sub-target bits (STB3) in the third page data (PD3).

For example, since the first sub-target bits (STB1) are the first bit (B1), the nonvolatile memory device (100) can flip the first bit (B1) of the first page data (PD1) from '1' to '0'. Since the second sub-target bits (STB2) are the fourth bit (B4), the nonvolatile memory device (100) can flip the fourth bit (B4) of the second page data (PD2) from '1' to '0'. Since the third sub-target bits (STB3) are the sixth bit (B6), the nonvolatile memory device (100) can flip the sixth bit (B6) of the third page data (PD3) from '1' to '0'.

Referring to FIG. 11c, the nonvolatile memory device (100) can generate FBP data. The page buffer circuit (130) can output target bits (or locations of weak patterns) to the control logic circuit (160). The control logic circuit (160) can generate FBP data based on the target bits (or locations of weak patterns). The FBP data can include first to third sub-FBP data (FBP_SUB1, FBP_SUB2, FBP_SUB3). The control logic circuit (160) can output the FBP data (i.e., the first to third sub-FBP data (FBP_SUB1, FBP_SUB2, FBP_SUB3)) to the page buffer circuit (130).

For example, the nonvolatile memory device (100) can generate first sub FBP data (FBP_SUB1) corresponding to the first page data (PD1). The nonvolatile memory device (100) can generate second sub FBP data (FBP_SUB2) corresponding to the second page data (PD2). The nonvolatile memory device (100) can generate third sub FBP data (FBP_SUB3) corresponding to the third page data (PD3).

In one embodiment, the nonvolatile memory device (100) can flip first page data (PD1) of the first write data (WD1) to generate first flipped page data, and add first sub FBP data (FBP_SUB1) to the first flipped page data to generate first encoded page data (EPD1). The nonvolatile memory device (100) can flip second page data (PD2) of the first write data (WD1) to generate second flipped page data, and add second sub FBP data (FBP_SUB2) to the second flipped page data to generate second encoded page data (EPD2). The nonvolatile memory device (100) can flip third page data (PD3) of the first write data (WD1) to generate third flipped page data, and add third sub FBP data (FBP_SUB3) to the third flipped page data to generate third encoded page data (EPD3).

Page data (PD) may include user data (UD) corresponding to the first area (AREA1) and data corresponding to the second area (AREA2). The user data may include first sub-user data corresponding to the first part (S1), second sub-user data corresponding to the second part (S2), and third sub-user data corresponding to the third part (S3).

The first write data (WD1) may include first to third page data (PD1 to PD3). The first page data (PD1) may include user data (UD1) corresponding to the first area (AREA1) and data corresponding to the second area (AREA2). The user data (UD1) of the first page data (PD1) may include first sub-user data (UD1_S1), second sub-user data (UD1_S2), and third sub-user data (UD1_S3). The second page data (PD2) may include user data (UD2) corresponding to the first area (AREA1) and data corresponding to the second area (AREA2). The user data (UD2) of the second page data (PD2) may include first sub-user data (UD2_S1), second sub-user data (UD2_S2), and third sub-user data (UD2_S3). The third page data (PD3) may include user data (UD3) corresponding to the first area (AREA1) and data corresponding to the second area (AREA2). The user data (UD3) of the third page data (PD3) may include first sub-user data (UD3_S1), second sub-user data (UD3_S2), and third sub-user data (UD3_S3).

The nonvolatile memory device (100) can perform a flip operation on the first sub-user data (UD1_S1) of the first page data (PD1) to generate the flipped first sub-user data (F_UD1_S1). That is, the nonvolatile memory device (100) can convert the first sub-user data (UD1_S1) into the flipped first sub-user data (F_UD1_S1). The nonvolatile memory device (100) can perform a flip operation on the second sub-user data (UD2_S2) of the second page data (PD2) to generate the flipped second sub-user data (F_UD2_S2). That is, the nonvolatile memory device (100) can convert the second sub-user data (UD2_S2) into the flipped second sub-user data (F_UD2_S2). The nonvolatile memory device (100) can perform a flip operation on the third sub-user data (UD3_S3) of the third page data (PD3) to generate flipped third sub-user data (F_UD3_S3). That is, the nonvolatile memory device (100) can convert the third sub-user data (UD3_S3) into flipped third sub-user data (F_UD3_S3).

The first sub FBP data (FBP_SUB1) may correspond to the flipped first sub-user data (F_UD1_S1), the second sub FBP data (FBP_SUB2) may correspond to the flipped second sub-user data (F_UD2_S2), and the third sub FBP data (FBP_SUB3) may correspond to the flipped third sub-user data (F_UD3_S3).

The first sub FBP data (FBP_SUB1) may point to flip bit position information for the first page data (PD1), the second sub FBP data (FBP_SUB2) may point to flip bit position information for the second page data (PD2), and the third sub FBP data (FBP_SUB3) may point to flip bit position information for the third page data (PD3).

Alternatively, the first sub FBP data (FBP_SUB1) may point to position information of flipped bits in the flipped first sub-user data (F_UD1_S1), the second sub FBP data (FBP_SUB2) may point to position information of flipped bits in the flipped second sub-user data (F_UD2_S2), and the third sub FBP data (FBP_SUB3) may point to position information of flipped bits in the flipped third sub-user data (F_UD3_S3).

The nonvolatile memory device (100) can generate second write data (WD2) by adding FBP data to the flipped first write data. That is, the nonvolatile memory device (100) can generate second write data (WD2) based on the first write data (WD1), the flipped first sub-user data (F_UD1_S1), the flipped second sub-user data (F_UD2_S2), the flipped third sub-user data (F_UD3_S3), the first sub-FBP data (FBP_SUB1), the second sub-FBP data (FBP_SUB2), and the third sub-FBP data (FBP_SUB3).

The second write data (WD2) may include first to third page data (PD1 to PD3). The first page data (PD1) may include flipped first user data (FUD1) and first sub FBP data (FBP_SUB1). The flipped first user data (FUD1) may include flipped first sub-user data (F_UD1_S1), second sub-user data (UD1_S2), and third sub-user data (UD1_S3). The second page data (PD2) may include flipped second user data (FUD2) and second sub FBP data (FBP_SUB2). The flipped second user data (FUD2) may include first sub-user data (UD2_S1), flipped second sub-user data (F_UD2_S2), and third sub-user data (UD2_S3). The third page data (PD3) may include flipped third user data (FUD3) and third sub FBP data (FBP_SUB3). The flipped third user data (FUD3) may include first sub-user data (UD3_S1), second sub-user data (UD3_S2), and flipped third sub-user data (F_UD3_S3).

Referring to FIG. 11d, the nonvolatile memory device (100) can receive a read command for the first page data (PD1). In response to the read command, the nonvolatile memory device (100) can read only the first encoded page data (EPD1) and provide the decoded data to the storage controller. Since the first sub-FBP data indicates information about the positions of flipped bits in the flipped first user data (FUD1), the nonvolatile memory device (100) can perform a re-flip operation even without reading other sub-FBP data.

That is, the nonvolatile memory device (100) can perform a re-flip operation by reading the first encoded page data (EPD1) to provide decoded data. Similarly, the second page data (PD2) and the third page data (PD3) can be performed by the nonvolatile memory device (100) to read the second encoded page data (EPD2) to perform a decoding operation to output decoded data. The nonvolatile memory device (100) can read the third encoded page data (EPD3) to perform a decoding operation to output decoded data.

In one embodiment, the nonvolatile memory device (100) can store FBP data corresponding to page data in encoded page data corresponding to the page data. For example, the nonvolatile memory device (100) only stores FBP data indicating flipped bits for the second page data (PD2) in the second encoded page data (EPD2), and does not store it in the first encoded page data (EPD1) or the third encoded page data (EPD3), so that there is no need to read other page data for the FBP data. The nonvolatile memory device according to an embodiment of the present disclosure can remove a weak pattern by performing a weak pattern detection operation and an encoding operation. Accordingly, the lifespan and read delay time of a storage device including the nonvolatile memory device can be significantly improved.

FIGS. 12A and 12B are drawings for explaining a second flip operation of a nonvolatile memory device according to one embodiment of the present disclosure.

Referring to FIGS. 12A and 12B, the nonvolatile memory device (100) may perform a second flip operation instead of the first flip operation. FIG. 12A illustrates a programmed state after performing the first flip operation (or bit flip operation) described in FIGS. 11A and 11B. FIG. 12B illustrates a programmed state after performing the second flip operation (or chunk flip operation).

For convenience of explanation, FIGS. 12A and 12B illustrate only memory cells connected to the third word line (WL3), and detailed descriptions or reference numbers for components identical or similar to the components described above are omitted. The components omitted below can be implemented through each of the overall embodiments described in the detailed description of the present invention or a combination thereof. It is assumed that the target bits are the first, fifth, and ninth bits (B1, B5, B9).

The memory cell array (110) may include memory cells (MC31 to MC3n) connected to a third word line (WL3). The memory cells (MC31 to MC3C) may be included in a first area (AREA1), and the memory cells (MC3D to MC3n) may be included in a second area (AREA2). The memory cells (MC31 to MC34) may be included in a first portion (S1), the memory cells (MC35 to MC38) may be included in a second portion (S2), and the memory cells (MC39 to MC3C) may be included in a third portion (S3).

The nonvolatile memory device (100) can store second write data (WD2) in the third word line (WL3). The nonvolatile memory device (100) can store flipped user data (FUD) in the first area (AREA1) and FBP data in the second area (AREA2).

Referring to FIG. 12A, a memory cell (MC31) may have a first program state (P1), a memory cell (MC32) may have a sixth program state (P6), a memory cell (MC33) may have a fifth program state (P5), a memory cell (MC34) may have a second program state (P2), a memory cell (MC35) may have a seventh program state (P7), a memory cell (MC36) may have a third program state (P3), a memory cell (MC37) may have a fourth program state (P4), a memory cell (MC38) may have a seventh program state (P7), a memory cell (MC39) may have a fifth program state (P5), a memory cell (MC3A) may have a first program state (P1), a memory cell (MC3B) may have an erase state (E), and a memory cell (MC3C) may have a sixth program state (P6).

Since the first bit (B1) is a target bit and the first bit (B1) corresponds to the first portion (S1), the nonvolatile memory device (100) can perform a flip operation to convert the first bit data (BD1) from data corresponding to the erase state (E) to data corresponding to the first program state (P1). Therefore, the memory cell (MC31) can have the first program state (P1). Since the fifth bit (B5) is a target bit and the fifth bit (B5) corresponds to the second portion (S2), the nonvolatile memory device (100) can perform a flip operation to convert the fifth bit data (BD5) from data corresponding to the erase state (E) to data corresponding to the seventh program state (P7). Therefore, the memory cell (MC35) can have the seventh program state (P7). Since the ninth bit (B9) is a target bit and the ninth bit (B9) corresponds to the third portion (S3), the nonvolatile memory device (100) can perform a flip operation to convert the ninth bit data (BD9) from data corresponding to the erase state (E) to data corresponding to the fifth program state (P5). Accordingly, the memory cell (MC39) can have the fifth program state (P5).

Referring to FIG. 12b, the nonvolatile memory device (100) can perform a second flip operation. The nonvolatile memory device (100) can perform a second flip operation on the first write data (WD1) to generate third write data (WD3). The second flip operation can refer to an operation of flipping all chunks to which a target bit belongs.

In one embodiment, the write data may include a plurality of chunks. Data corresponding to a first area of the write data may be divided into a plurality of chunks. For example, the first write data (WD1) may include first to sixth chunks (C1 to C6). The first chunk (C1) may include first and second bit data (BD1, BD2), the second chunk (C2) may include third and fourth bit data (BD3, BD4), the third chunk (C3) may include fifth and sixth bit data (BD5, BD6), the fourth chunk (C4) may include seventh and eighth bit data (BD7, BD8), the fifth chunk (C5) may include ninth and tenth bit data (BD9, BDA), and the sixth chunk (C6) may include eleventh and twelfth bit data (BDB, BDC). That is, the first chunk (C1) may correspond to the first and second bits (B1, B2), the second chunk (C2) may correspond to the third and fourth bits (B3, B4), the third chunk (C3) may correspond to the fifth and sixth bits (B5, B6), the fourth chunk (C4) may correspond to the seventh and eighth bits (B7, B8), the fifth chunk (C5) may correspond to the ninth and tenth bits (B9, B10), and the sixth chunk (C6) may correspond to the eleventh and twelfth bits (B11, B12).

The nonvolatile memory device (100) can perform a second flip operation. The second flip operation can refer to an operation of flipping data corresponding to all bits included in a chunk including a target bit. The second flip operation can be a chunk flip operation. The target neighboring bits can refer to bits included in the same chunk as the target bit, but are not the target bit (i.e., do not correspond to the target bit). For example, the nonvolatile memory device (100) can flip data corresponding to the target bits. The nonvolatile memory device (100) can flip data corresponding to the target neighboring bits.

For example, the target bits may include the first, fifth, and ninth bits (B1, B5, B9). The target neighboring bits may include the second, sixth, and tenth bits (B2, B6, B10). The nonvolatile memory device (100) may flip data corresponding to the target bits and may also flip data corresponding to the target neighboring bits.

The target bits may include first to third sub-target bits (STB1 to STB3). The first sub-target bits (STB1) may include a first bit (B1), the second sub-target bits (STB2) may include a fifth bit (B5), and the third sub-target bits (STB3) may include a ninth bit (B9). The nonvolatile memory device (100) may flip data corresponding to the first sub-target bit (i.e., the first bit (B1)) of the first page data (PD1), flip data corresponding to the second sub-target bit (i.e., the fifth bit (B5)) of the second page data (PD2), and flip data corresponding to the third sub-target bit (i.e., the ninth bit (B9)) of the third page data (PD3).

In one embodiment, the target neighboring bits (TNB) may include first to third sub-neighboring bits (SNB1 to SNB3). Alternatively, the target neighboring bits (TNB) may be divided into first to third sub-neighboring bits (SNB1 to SNB3). The first sub-neighboring bits (SNB1) may indicate bits corresponding to a first portion (S1) of the target neighboring bits (TNB), the second sub-neighboring bits (SNB2) may indicate bits corresponding to a second portion (S2) of the target neighboring bits (TNB), and the third sub-neighboring bits (SNB3) may indicate bits corresponding to a third portion (S3) of the target neighboring bits (TNB). The target neighboring bits and the sub-neighboring bits may be as shown in Table 2.

TNB SNB1 B2 SNB2 B6 SNB3 B10

Referring to Table 2, the target neighboring bits (TNB) may include the second, sixth, and tenth bits (B2, B6, B10). The first sub-neighboring bits (SNB1) may include the second bit (B2), the second sub-neighboring bits (SNB2) may include the sixth bit (B6), and the third sub-neighboring bits (SNB3) may include the tenth bit (B10). The nonvolatile memory device (100) may flip data corresponding to the first sub-neighboring bit (i.e., the second bit (B2)) of the first page data (PD1), flip data corresponding to the second sub-neighboring bit (i.e., the sixth bit (B6)) of the second page data (PD2), and flip data corresponding to the third sub-neighboring bit (i.e., the tenth bit (B10)) of the third page data (PD3). The nonvolatile memory device (100) can flip the entire first chunk (C1) corresponding to the first bit (B1) since the first bit (B1) is a target bit. That is, the nonvolatile memory device (100) can convert the first and second bit data (BD1, BD2). Since the first and second bits (B1, B2) correspond to the first portion (S1), the bit corresponding to the first page data (PD1) can be flipped. Accordingly, the nonvolatile memory device (100) can convert the first bit data (BD1) from a value corresponding to the erase state (E) (e.g., [1, 1, 1]) to a value corresponding to the first program state (P1) (e.g., [0, 1, 1]). The nonvolatile memory device (100) can convert the second bit data (BD2) from a value corresponding to the sixth program state (P6) (e.g., [1, 0, 0]) to a value corresponding to the third program state (P3) (e.g., [0, 0, 0]).

The nonvolatile memory device (100) can flip the entire third chunk (C3) corresponding to the fifth bit (B5) since the fifth bit (B5) is a target bit. That is, the nonvolatile memory device (100) can convert the fifth and sixth bit data (BD5, BD6). Since the fifth and sixth bits (B5, B6) correspond to the second portion (S2), the bit corresponding to the second page data (PD2) can be flipped. Accordingly, the nonvolatile memory device (100) can convert the fifth bit data (BD5) from a value corresponding to the erase state (E) (e.g., [1, 1, 1]) to a value corresponding to the seventh program state (P7) (e.g., [1, 0, 1]). The nonvolatile memory device (100) can convert the sixth bit data (BD6) from a value corresponding to the third program state (P3) (e.g., [0, 0, 0]) to a value corresponding to the fourth program state (P4) (e.g., [0, 1, 0]).

The nonvolatile memory device (100) can flip the entire sixth chunk (C6) corresponding to the ninth bit (B9) since the ninth bit (B9) is a target bit. That is, the nonvolatile memory device (100) can convert the ninth and tenth bit data (BD9, BDA). Since the ninth and tenth bits (B9, B10) correspond to the third portion (S3), the bit corresponding to the third page data (PD3) can be flipped. Accordingly, the nonvolatile memory device (100) can convert the ninth bit data (BD9) from a value corresponding to the erase state (E) (e.g., [1, 1, 1]) to a value corresponding to the fifth program state (P7) (e.g., [1, 1, 0]). The nonvolatile memory device (100) can convert the 10-bit data (BDA) from a value corresponding to the first program state (P1) (e.g., [0, 1, 1]) to a value corresponding to the fourth program state (P4) (e.g., [0, 1, 0]).

A nonvolatile memory device (100) can perform a chunk flip operation to flip the first, third, and fifth chunks (C1, C3, C5) to generate chunk-flipped first write data. The nonvolatile memory device (100) can add FBP data to the chunk-flipped first write data to generate third write data (WD3). The nonvolatile memory device (100) can store the third write data (WD3) in a third word line (WL3). Accordingly, the memory cell (MC31) connected to the third word line (WL3) can have a first program state (P1), the memory cell (MC32) can have a third program state (P3), the memory cell (MC33) can have a fifth program state (P5), the memory cell (MC34) can have a second program state (P2), the memory cell (MC35) can have a seventh program state (P7), the memory cell (MC36) can have a fourth program state (P4), the memory cell (MC37) can have a fourth program state (P4), the memory cell (MC38) can have a seventh program state (P7), the memory cell (MC39) can have a fifth program state (P5), the memory cell (MC3A) can have a fourth program state (P4), the memory cell (MC3B) can have an erase state (E), and the memory cell (MC3C) can have a sixth program state (P6).

As described above, the nonvolatile memory device (100) can perform the second flip operation. By performing the flip in chunk units, the size of the FBP data can be reduced. The nonvolatile memory device (100) can efficiently manage the storage space by performing the second flip operation.

FIGS. 13A to 13G are drawings for explaining a write operation of a nonvolatile memory device according to an embodiment of the present disclosure.

For the sake of simplicity of the drawing and convenience of explanation, it is assumed that the memory cell array (110) includes a plurality of memory cells (MC11 to MC39) connected to first to third word lines (WL1 to WL3) and first to ninth bit lines (BL1 to BL9). However, the scope of the present disclosure is not limited thereto. Detailed descriptions or reference numbers for components identical or similar to the components described above are omitted. The components omitted below can be implemented through each of the overall embodiments described in the detailed description of the present invention or a combination thereof. The page buffer circuit (130) includes a data latch (131), and the data latch (131) can include first to fifth data latches (DL1 to DL5).

The nonvolatile memory device (100) uses a plurality of read voltages to read data stored in the memory cell array (110). For example, the nonvolatile memory device (100) can perform a read operation using the first and fifth read voltages (VRD1, VRD5) to read the first page data (PD1). The nonvolatile memory device (100) can perform a read operation using the second, fourth, and sixth read voltages (VRD2, VRD4, VRD6) to read the second page data (PD2). The nonvolatile memory device (100) can perform a read operation using the third and seventh read voltages (VRD3, VRD7) to read the third page data (PD3).

Unlike the read operation, when performing the weak pattern detection operation, there is no need to know the exact data value stored in the first word line (WL1). That is, since the nonvolatile memory device (100) only needs to find the first memory cells corresponding to the erase state (E1) in the first word line (WL1), sensing can be performed using only the first read voltage (VRD1). Unlike the read operation, when performing the weak pattern detection operation, there is no need to know the exact data value stored in the second word line (WL2). That is, since the nonvolatile memory device (100) only needs to find the first memory cells corresponding to the sixth program state (P6) or the seventh program state (P7) in the second word line (WL2), sensing can be performed using only the sixth read voltage (VRD1).

Referring to FIGS. 13A to 13G, the nonvolatile memory device (100) can perform a weak pattern detection operation. In step S310, the nonvolatile memory device can perform a first sensing operation on a first word line (WL1) using a first read voltage (VRD1). The nonvolatile memory device (100) can detect (or sense) the first word line (WL1) and detect first memory cells having an erase state (E1) in the first word line (WL1). The nonvolatile memory device (100) can perform the first sensing operation on the first word line (WL1) using only the first read voltage (VRD1). The nonvolatile memory device (100) can generate a first bitmap (BM1) through the first sensing operation. A nonvolatile memory device (100) can perform a first sensing operation to store a first bitmap (BM1) indicating first memory cells in a first data latch (DL1). The nonvolatile memory device (100) can detect a voltage change of a bit line (BL) using a first read voltage (VRD1) to determine whether a memory cell is in an erased state (E). Since memory cells (MC11, MC14, MC16) in the first word line (WL1) are first memory cells, the nonvolatile memory device (100) can store a first bitmap (BM1) (e.g., [1,0,0,1,0,1]) in the first data latch (DL1).

At step S320, the nonvolatile memory device (100) can perform a second sensing operation on the second word line (WL2) using the sixth read voltage (VRD6). The nonvolatile memory device (100) can sense the second word line (WL2) and detect second memory cells having the sixth program state (P6) or the seventh program state (P7) in the second word line (WL2). The nonvolatile memory device (100) can perform the second sensing operation on the second word line (WL2) using only the sixth read voltage (VRD6). The nonvolatile memory device (100) can generate a second bitmap (BM2) through the second sensing operation. The nonvolatile memory device (100) can perform the second sensing operation and store the second bitmap (BM2) indicating the second memory cells in the second data latch (DL2). The nonvolatile memory device (100) can detect a voltage change of the bit line (BL) using the sixth read voltage (VRD6) to determine whether the memory cell is in the sixth or seventh program states (P6, P7). Since the memory cells (MC21, MC23, MC24, MC26) in the second word line (WL2) are second memory cells, the nonvolatile memory device (100) can store the first bitmap (BM1) (e.g., [1,0,1,1,0,1]) in the second data latch (DL2).

In step S330, the nonvolatile memory device (100) can perform an AND operation on the first data latch (DL1) and the second data latch (DL2), and store the result in the first data latch (DL1). The nonvolatile memory device (100) can detect target bit lines by performing an AND operation on the first bitmap (BM1) and the second bitmap (BM2). That is, the nonvolatile memory device (100) can detect target bit lines including both the first memory cell and the second memory cell by performing a logical operation on data stored in the first data latch (DL1) and data stored in the second data latch (DL2).

For example, the nonvolatile memory device (100) may perform an AND operation on a first bitmap (BM1) (e.g., [1,0,0,1,0,1]) stored in a first data latch (DL1) and a second bitmap (BM2) (e.g., [1,0,1,1,0,1]) stored in a second data latch (DL2) to generate a third bitmap (BM3) (e.g., [1,0,0,1,0,1]). The nonvolatile memory device (100) may store the third bitmap (BM3) (e.g., [1,0,0,1,0,1]) in the first data latch (DL1). The third bitmap (BM3) may indicate target bit lines.

At step S340, the input/output circuit (140) can output the first write data (WD1) to the page buffer circuit (130). The nonvolatile memory device (100) can receive the first write data (WD1) from an external storage controller. The input/output circuit (140) can transmit the received first write data (WD1) to the page buffer circuit (130). The page buffer circuit (130) can store the first write data (WD1) in the data latch (131). The first write data (WD1) can include first to third page data (PD1 to PD3). The page buffer circuit (130) can store the first page data (PD1) (e.g., [1,0,1,1,1,1,0,0,0]) in the second data latch (DL2), the second page data (PD2) (e.g., [1,1,0,1,1,1,0,0,0]) in the third data latch (DL3), and the third page data (PD3) (e.g., [1,1,0,1,1,1,0,0,0]) in the fourth data latch (DL4).

At step S350, the nonvolatile memory device (100) can perform an AND operation on the first to fourth data latches (D1 to D4) and store the result in the fifth data latch (DL5). The nonvolatile memory device (100) can detect target bits by performing an AND operation on the first bitmap (BM1) and the first write data (WD1). The nonvolatile memory device (100) can detect target bits by performing an AND operation on the first bitmap (BM1), the first page data (PD1), the second page data (PD2), and the third page data (PD3). That is, the nonvolatile memory device (100) can detect target bits corresponding to a weak pattern by performing a logical operation on data stored in the first data latch (DL1), data stored in the second data latch (DL2), data stored in the third data latch (DL3), and data to be stored in the fourth data latch (DL4).

For example, the nonvolatile memory device (100) may perform an AND operation on a third bitmap (BM3) stored in a first data latch (DL1) (e.g., [1,0,0,1,0,1]), a first page data (PD1) stored in a second data latch (DL2) (e.g., [1,0,1,1,1,1,0,0,0]), a second page data (PD2) stored in a third data latch (DL3) (e.g., [1,1,0,1,1,1,0,0,0]), and a third page data (PD3) stored in a fourth data latch (DL4) (e.g., [1,1,0,1,1,1,0,0,0]), thereby generating a fourth bitmap (BM4) (e.g., [1,0,0,1,0,1,0,0,0]). The nonvolatile memory device (100) can store the fourth bitmap (BM4) (e.g., [1,0,0,1,0,1,0,0,0]) in the fifth data latch (DL5). The fourth bitmap (BM4) can indicate target bits (or information about the positions of the target bits). That is, the fourth bitmap (BM4) can include information about the position of a weak pattern. In this way, the nonvolatile memory device (100) can perform a weak pattern detection operation by performing steps S310 to S350.

The nonvolatile memory device (100) can perform an encoding operation by performing steps S360 to S389. The nonvolatile memory device (100) can perform an FBP data generation operation and a flip operation by performing steps S360 to S389 to convert the first write data (WD1) into the second write data (WD2). The nonvolatile memory device (100) can perform an encoding operation based on the first write data (WD1) and the FBP data to generate encoded data.

At step S360, the page buffer circuit (130) can output the fourth bitmap (BM4) to the control logic circuit (160). The FBP engine (161) can receive the fourth bitmap (BM4). The FBP engine (161) can generate FBP data based on the fourth bitmap (BM4). At step S370_1, the FBP engine (161) can output the generated FBP data to the FBP buffer (163). The FBP engine (161) can store the FBP data in the FBP buffer (163). At step S370_2, the FBP buffer (163) can output the FBP data to the FBP engine (161) and the ECC engine (162).

The nonvolatile memory device (100) can perform a flip operation by performing steps S381 to S389. The nonvolatile memory device (100) can perform a flip operation to generate second write data (WD2). The nonvolatile memory device (100) can convert first page data (PD1) into first encoded page data (EPD1) by performing steps S381 to S383.

In step S381, the nonvolatile memory device (100) may generate a first bit flip flag and store it in the fifth data latch (DL5). The FBP engine (161) may generate the first bit flip flag based on the FBP data (or the first sub FBP data (FBP_SUB1)). The first bit flip flag may indicate a bit to be flipped for the first page data (PD1). That is, the first bit flip flag may indicate information about the positions of bits to be flipped for the first page data (PD1). For example, since the first bit (B1) is a target bit and the first bit (B1) corresponds to the first portion (S1), the nonvolatile memory device (100) may flip data corresponding to the first page data (PD1) in the first bit data (BD1). Accordingly, the nonvolatile memory device (100) can generate a first bit flip flag (e.g., [1,0,0,0,0,0]) to flip the first bit (B1) of the first page data (PD1).

At step S382, the nonvolatile memory device (100) may generate first encoded sub FBP data (E_FBP_SUB1) and store it in the fifth data latch (DL5). The ECC engine (162) may perform encoding for error correction on the first sub FBP data (FBP_SUB1). In one embodiment, the ECC engine (162) may generate parity bits in the first sub FBP data (FBP_SUB1). The ECC engine (162) may add parity bits to the first sub FBP data (FBP_SUB1) to generate first encoded sub FBP data (E_FBP_SUB1). The ECC engine (162) may output the first encoded sub FBP data (E_FBP_SUB1) to the page buffer circuit (130). The page buffer circuit (130) can store the first sub FBP data (E_FBP_SUB1) (e.g., [A1, A2, A3]) in the fifth data latch (DL5).

The nonvolatile memory device (100) can store the first bit flip flag in bits corresponding to the first area (AREA1) and store the first encoded sub FBP data (E_FBP_SUB1) in bits corresponding to the second area (AREA2). The nonvolatile memory device (100) can add the first encoded sub FBP data (E_FBP_SUB1) to the first bit flip flag to generate a fifth bitmap (BM5) (e.g., [1,0,0,0,0,0,A1,A2,A3]) and store the fifth bitmap (BM5) in the fifth data latch (DL5).

At step S383, the nonvolatile memory device (100) can perform an XOR operation on the second data latch (DL2) and the fifth data latch (DL5), and store the result in the second data latch (DL2). The nonvolatile memory device (100) can perform an XOR operation on the first page data (PD1) (e.g., [1,0,1,1,1,0,0,0]) and the fifth bitmap (BM5) (e.g., [1,0,0,0,0,0,A1,A2,A3]), and generate the first encoded page data (EPD1) (e.g., [0,0,1,1,1,1,A1,A2,A3]). That is, the nonvolatile memory device (100) can perform a logical operation on the data stored in the second data latch (DL2) and the data stored in the fifth data latch (DL5) to store the first encoded page data (EPD1) including the flipped first page data and the first encoded sub FBP data (E_FBP_SUB1) in the second data latch (DL2). That is, the nonvolatile memory device (100) can flip the first bit (B1) of the first page data (PD1) and add flip bit position information (the first encoded sub FBP data (E_FBP_SUB1)) for the first page data (PD1) to generate the first encoded page data (EPD1).

The nonvolatile memory device (100) may generate second encoded page data (EPD2) by performing steps S384 to S386. In step S384, the nonvolatile memory device (100) may generate a second bit flip flag and store it in the fifth data latch (DL5). The FBP engine (161) may generate the second bit flip flag based on the FBP data (or the second sub FBP data (FBP_SUB2)). The second bit flip flag may indicate a bit to be flipped for the second page data (PD2). For example, since the fourth bit (B4) is a target bit and the fourth bit (B4) corresponds to the second portion (S2), the nonvolatile memory device (100) may flip data corresponding to the second page data (PD2) in the fourth bit data (BD4). Accordingly, the nonvolatile memory device (100) can generate a second bit flip flag (e.g., [0,0,0,1,0,0]) to flip the fourth bit (B4) of the second page data (PD2).

At step S385, the nonvolatile memory device (100) can generate second encoded sub FBP data (E_FBP_SUB2) and store it in the fifth data latch (DL5). The ECC engine (162) can perform encoding on the second sub FBP data (FBP_SUB2). In one embodiment, the ECC engine (162) can generate parity bits in the second sub FBP data (FBP_SUB2). The ECC engine (162) can add the parity bits to the second sub FBP data (FBP_SUB2) to generate second encoded sub FBP data (E_FBP_SUB2). The ECC engine (162) can output the second encoded sub FBP data (E_FBP_SUB2) to the page buffer circuit (130). The page buffer circuit (130) can store the second encoded sub FBP data (E_FBP_SUB2) (e.g., [B1 B2, B3]) in the fifth data latch (DL5).

The nonvolatile memory device (100) can store the second bit flip flag in bits corresponding to the first area (AREA1) and store the second encoded sub FBP data (E_FBP_SUB2) in bits corresponding to the second area (AREA2). The nonvolatile memory device (100) can add the second encoded sub FBP data (E_FBP_SUB2) to the second bit flip flag to generate a sixth bitmap (BM6) (e.g., [0,0,0,1,0,0,B1,B2,B3]) and store the sixth bitmap (BM6) in the fifth data latch (DL5).

At step S386, the nonvolatile memory device (100) can perform an XOR operation on the third data latch (DL3) and the fifth data latch (DL5), and store the result in the third data latch (DL3). The nonvolatile memory device (100) can perform an XOR operation on the second page data (PD2) (e.g., [1,1,0,1,1,1,0,0,0]) and the sixth bitmap (BM6) (e.g., [0,0,0,1,0,0,B1,B2,B3]) to generate the second encoded page data (EPD2) (e.g., [1,1,0,0,1,1,B1,B2,B3]). That is, the nonvolatile memory device (100) can perform a logical operation on the data stored in the third data latch (DL3) and the data stored in the fifth data latch (DL5) to store the second encoded page data (EPD2) including the flipped second page data and the second encoded sub FBP data (E_FBP_SUB2) in the third data latch (DL3). That is, the nonvolatile memory device (100) can flip the fourth bit (B4) of the second page data (PD2) and add flip bit position information (the second encoded sub FBP data (E_FBP_SUB2)) for the second page data (PD2) to convert the second page data (PD2) into the second encoded page data (EPD2).

The nonvolatile memory device (100) may generate third encoded page data (EPD3) by performing steps S387 to S389. In step S384, the nonvolatile memory device (100) may generate a third bit flip flag and store it in the fifth data latch (DL5). The FBP engine (161) may generate the third bit flip flag based on the FBP data (or the third sub FBP data (FBP_SUB3)). The third bit flip flag may indicate a bit to be flipped for the third page data (PD3). For example, since the sixth bit (B6) is a target bit and the sixth bit (B6) corresponds to the third portion (S3), the nonvolatile memory device (100) may flip data corresponding to the third page data (PD3) in the sixth bit data (BD6). Accordingly, the nonvolatile memory device (100) can generate a third bit flip flag (e.g., [0,0,0,0,0,1]) to flip the sixth bit (B6) of the third page data (PD3).

At step S388, the nonvolatile memory device (100) may generate third encoded sub FBP data (E_FBP_SUB3) and store it in the fifth data latch (DL5). The ECC engine (162) may perform encoding on the third sub FBP data (FBP_SUB3). In one embodiment, the ECC engine (162) may generate parity bits in the third sub FBP data (FBP_SUB3). The ECC engine (162) may add parity bits to the third sub FBP data (FBP_SUB3) to generate third encoded sub FBP data (E_FBP_SUB3). The ECC engine (162) may output the third encoded sub FBP data (E_FBP_SUB3) to the page buffer circuit (130). The page buffer circuit (130) can store the third encoded sub FBP data (E_FBP_SUB3) (e.g., [C1 C2, C3]) in the fifth data latch (DL5).

The nonvolatile memory device (100) can store the third bit flip flag in bits corresponding to the first area (AREA1) and store the third encoded sub FBP data (E_FBP_SUB3) in bits corresponding to the second area (AREA2). The nonvolatile memory device (100) can generate a seventh bitmap (BM7) (e.g., [0,0,0,0,0,1,C1,C2,C3]) by adding the third encoded sub FBP data (E_FBP_SUB3) to the third bit flip flag and store the seventh bitmap (BM7) in the fifth data latch (DL5).

At step S389, the nonvolatile memory device (100) can perform an XOR operation on the fourth data latch (DL4) and the fifth data latch (DL5), and store the result in the fourth data latch (DL4). The nonvolatile memory device (100) can perform an XOR operation on the third page data (PD3) (e.g., [1,1,0,1,1,1,0,0,0]) and the seventh bitmap (BM7) (e.g., [0,0,0,0,0,1,C1,C2,C3]) to generate the third encoded page data (EPD3) (e.g., [1,1,0,1,1,0,C1,C2,C3]). That is, the nonvolatile memory device (100) can perform a logical operation on the data stored in the fourth data latch (DL4) and the data stored in the fifth data latch (DL5) to store the third encoded page data (EPD3) including the flipped third page data and the third encoded sub FBP data (E_FBP_SUB3) in the fourth data latch (DL4). That is, the nonvolatile memory device (100) can flip the sixth bit (B6) of the third page data (PD3) and add flip bit position information (the third encoded sub FBP data (E_FBP_SUB3)) for the third page data (PD3) to convert the third page data (PD3) into the third encoded page data (EPD3).

At step S390, the nonvolatile memory device (100) can perform a program operation. The nonvolatile memory device (100) can program encoded data to a third word line (WL3). The page buffer circuit (130) can output second write data (WD2) to the memory cell array (110). The second write data (WD2) can include first to third encoded page data (EPD1 to EPD3). The second write data (WD2) may be programmed to the third word line (WL3), so that the memory cell (MC31) may have a first program state (P1), the memory cell (MC32) may have a first program state (P1), the memory cell (MC33) may have a sixth program state (P6), the memory cell (MC34) may have a seventh program state (P7), the memory cell (MC35) may have an erase state, and the memory cell (MC36) may have a fifth program state (P5). The nonvolatile memory device (100) may store encoded FBP data including first to third encoded sub FBP data (E_FBP_SUB1 to E_FBP_SUB3) in the memory cells (MC27, MC28, and MC29).

As described with reference to FIGS. 11A to 11D, the target bits may include a plurality of sub-target bits. The target bits may be first, fourth, and sixth bits (B1, B4, B6), and the first sub-target bits (STB1) may be the first bit (B1), the second sub-target bits (STB2) may be the fourth bit (B4), and the third sub-target bits (STB3) may be the sixth bit (B6).

The nonvolatile memory device (100) can program encoded data and FBP data to a third word line (WL3). The nonvolatile memory device (100) can program a memory cell corresponding to the first sub-target bits (STB1) to be in a first program state (P1). The nonvolatile memory device (100) can program a memory cell corresponding to the second sub-target bits (STB2) to be in a seventh program state (P7). The nonvolatile memory device (100) can program a memory cell corresponding to the third sub-target bits (STB3) to be in a fifth program state (P5).

That is, since the first sub-target bits (STB1) are the first bit (B1), the nonvolatile memory device (100) can program the memory cell (MC31) corresponding to the first bit (B1) to be in the first program state (P1) instead of the erased state (E). Since the second sub-target bits (STB2) are the fourth bit (B4), the nonvolatile memory device (100) can program the memory cell (MC34) corresponding to the fourth bit (B4) to be in the seventh program state (P7) instead of the erased state (E). Since the third sub-target bits (STB3) are the sixth bit (B6), the nonvolatile memory device (100) can program the memory cell (MC36) corresponding to the sixth bit (B6) to be in the fifth program state (P5) instead of the erased state (E).

In one embodiment, the first page data (PD1) of the second write data (WD2) may include first encoded sub FBP data (E_FBP_SUB1), the second page data (PD2) of the second write data (WD2) may include second encoded sub FBP data (E_FBP_SUB2), and the third page data (PD3) of the second write data (WD2) may include third encoded sub FBP data (E_FBP_SUB3). That is, the encoded FBP data may be stored in the second area (AREA2) of the third word line (WLD3).

In one embodiment, as described above with reference to FIG. 11C, the nonvolatile memory device (100) may store FBP data in the memory cell array (110) without performing encoding against the FBP data. The first page data (PD1) of the second write data (WD2) to be stored in the memory cell array (110) may include the first sub FBP data (FBP_SUB1) instead of the first encoded sub FBP data. The second page data (PD2) of the second write data (WD2) may include the second sub FBP data (FBP_SUB2), and the third page data (PD3) of the second write data (WD2) may include the third sub FBP data (FBP_SUB3). That is, the FBP data may be stored in the second area (AREA2) of the third word line (WL3).

FIG. 14 is a diagram for explaining a write operation of a nonvolatile memory device according to an embodiment of the present disclosure.

Referring to FIGS. 13A to 13G, steps S310 to S330 are illustrated as being performed before step S340, but the scope of the present disclosure is not limited thereto, and the operations of the steps may be performed simultaneously or in a reversed order.

Referring to FIG. 14, the nonvolatile memory device (100) can perform steps S310 and S320 from a first time point (t1) to a third time point (t3). The nonvolatile memory device (100) can perform step S340 from a first time point (t1) to a second time point (t2). That is, the nonvolatile memory device (100) can sense the first and second word lines (WL1, WL2) and simultaneously receive first write data (WD1) from the storage controller.

The nonvolatile memory device (100) performs data transmission operations and sensing operations simultaneously, so the latency of the weak pattern detection operation can be reduced.

FIGS. 15A to 15C are drawings for explaining a read operation of a nonvolatile memory device according to an embodiment of the present disclosure.

For the sake of simplicity of the drawing and convenience of explanation, it is assumed that the memory cell array (110) includes a plurality of memory cells (MC11 to MC39) connected to first to third word lines (WL1 to WL3) and first to ninth bit lines (BL1 to BL9). However, the scope of the present disclosure is not limited thereto. Detailed descriptions or reference numbers for components identical or similar to the components described above are omitted. The components omitted below can be implemented through each of the overall embodiments described in the detailed description of the present invention or a combination thereof. The page buffer circuit (130) includes a data latch (131), and the data latch (131) can include first to fifth data latches (DL1 to DL5).

At step S410, the nonvolatile memory device (100) can read the second encoded page data (EPD2) from the third word line (WL3) in response to the read command. The nonvolatile memory device (100) can read the second encoded page data (EPD2) stored in the third word line (WL3) by detecting a voltage change of the bit lines (BL). The nonvolatile memory device (100) can store the second encoded page data (EPD2) (e.g., [1,1,0,0,1,1,B1, B2, B3]) in the third data latch (DL3).

In one embodiment, the nonvolatile memory device (100) can copy the second encoded sub-FBP data (E_BFP_SUB2) stored in bits corresponding to the stored second area (AREA2) from the third data latch (DL3) to the fifth data latch (DL5). That is, the nonvolatile memory device (100) can store the second encoded sub-FBP data (E_BFP_SUB2) in the fifth data latch (DL5).

The nonvolatile memory device (100) can perform a decoding operation through steps S420 to S460. The nonvolatile memory device (100) can perform the decoding operation to convert encoded page data into page data (or decoded data). In step S420, the nonvolatile memory device (100) can transmit the second encoded sub-FBP data (E_BFP_SUB2) to the control logic circuit (160). The page buffer circuit (130) can output the second encoded sub-FBP data (E_BFP_SUB2) to the ECC engine (162).

At step S430, the nonvolatile memory device (100) can generate second sub FBP data (BFP_SUB2) and output it to the FBP buffer (163). The nonvolatile memory device (100) can perform a decoding operation on the second encoded sub FBP data (E_BFP_SUB2) to generate the second sub FBP data (BFP_SUB2). The ECC engine (162) can generate the second sub FBP data (BFP_SUB2) based on the second encoded sub FBP data (E_BFP_SUB2). The ECC engine (162) can correct an error of the second sub FBP data (BFP_SUB2) using the second encoded sub FBP data (E_BFP_SUB2) and output the second sub FBP data (BFP_SUB2) with the error corrected. The second sub FBP data (BFP_SUB2) can be stored in the FBP buffer (163).

At step S440, the FBP buffer (163) can output the second sub FBP data (BFP_SUB2) to the FBP engine (161). At step S450, the FBP engine (161) can generate a second flip bit flag and output it to the page buffer circuit (130). The FBP engine (161) can generate a second bit flip flag based on the second sub FBP data (FBP_SUB2). The second bit flip flag can indicate a bit to be flipped for the second page data (PD2). For example, in the second encoded page data (EPD2), the fourth bit (B4) is a flipped bit. The nonvolatile memory device (100) can generate the second bit flip flag (e.g., [0,0,0,1,0,0]) to flip the fourth bit (B4) of the second page data (PD2). The page buffer circuit (130) can store the second bit flip flag in the fifth data latch (DL5).

The nonvolatile memory device (100) can store the second bit flip flag in bits corresponding to the first area (AREA1) and store the second encoded sub FBP data (E_FBP_SUB2) in bits corresponding to the second area (AREA2). The nonvolatile memory device (100) can add the second encoded sub FBP data (E_FBP_SUB2) to the second bit flip flag to generate an eighth bitmap (BM8) (e.g., [0,0,0,1,0,0,B1,B2,B3]) and store the eighth bitmap (BM8) in the fifth data latch (DL5).

At step S460, the nonvolatile memory device (100) can perform an XOR operation on the third data latch (DL3) and the fifth data latch (DL5), and store the result in the third data latch (DL3). The nonvolatile memory device (100) can perform an XOR operation on the second encoded page data (PD2) (e.g., [1,1,0,0,1,1,B1,B2,B3]) and the sixth bitmap (BM6) (e.g., [0,0,0,1,0,0,B1,B2,B3]) to generate decoded data (DD) (e.g., [1,1,0,1,1,1,0,0,0]). That is, the nonvolatile memory device (100) can perform a logical operation on the data stored in the third data latch (DL3) and the data stored in the fifth data latch (DL5) to store the decoded data (DD) in the third data latch (DL3). That is, the nonvolatile memory device (100) can flip the fourth bit (B4) of the second encoded page data (EPD2) and remove the second encoded sub FBP data (E_BFP_SUB2) to convert the second encoded page data (EPD2) into the decoded data (DD). At step S470, the nonvolatile memory device (100) can output the decoded data (DD) to the input/output circuit (140).

FIG. 16 is a block diagram showing an SSD system to which a storage device according to the present disclosure is applied.

Referring to FIG. 16, the SSD system (1000) includes a host (1100) and an SSD (1200). The SSD (1200) exchanges a signal (SIG) with the host (1100) through a signal connector (1201) and receives power (PWR) through a power connector (1202). The SSD (1200) includes an SSD controller (1210), a plurality of flash memories (1221 to 122n), an auxiliary power supply (1230), and a buffer memory (1240).

The SSD controller (1210) can control a plurality of flash memories (1221 to 122n) in response to a signal (SIG) received from the host (1100). The plurality of flash memories (1221 to 122n) can operate under the control of the SSD controller (1210). The auxiliary power supply unit (1230) is connected to the host (1100) through the power connector (1002). The auxiliary power supply unit (1230) can receive power (PWR) from the host (1100) and charge it. The auxiliary power supply unit (1230) can provide power to the SSD (1200) when the power supply from the host (1100) is not smooth. The buffer memory (1240) operates as a buffer memory of the SSD (1200).

The SSD controller (1210) can receive a debugging data request from the host (1100) and transmit the debugging data request to a plurality of flash memories (1221 to 122n). The debugging circuit can generate debugging data for non-volatile memory and output the generated debugging data to the SSD controller (1210). The host (1100) can receive the debugging data from the SSD controller (1210) and check whether a problem has occurred between the SSD controller (1210) and the plurality of flash memories (1221 to 122n).

Each of the plurality of flash memories (1221 to 122n) according to an embodiment of the present disclosure can perform a weak pattern detection operation and an encoding operation to remove a weak pattern. Accordingly, the reliability and lifespan of the nonvolatile memory and storage device can be improved.

FIG. 17 is a drawing for explaining a memory device (500) according to an embodiment of the present invention.

Referring to FIG. 17, the memory device (500) may have a C2C (chip to chip) structure. Here, the C2C structure may mean that at least one upper chip including a cell region (CELL) and a lower chip including a peripheral circuit region (PERI) are manufactured, and then the at least one upper chip and the lower chip are connected to each other by a bonding method. For example, the bonding method may mean a method of electrically or physically connecting a bonding metal pattern formed on an uppermost metal layer of the upper chip and a bonding metal pattern formed on an uppermost metal layer of the lower chip. For example, when the bonding metal patterns are formed of copper (Cu), the bonding method may be a Cu-Cu bonding method. As another example, the bonding metal patterns may also be formed of aluminum (Al) or tungsten (W).

The memory device (500) may include at least one upper chip including a cell region. For example, as illustrated in FIG. 17, the memory device (500) may be implemented to include two upper chips. However, this is exemplary, and the number of upper chips is not limited thereto. When the memory device (500) is implemented to include two upper chips, a first upper chip including a first cell region (CELL1), a second upper chip including a second cell region (CELL2), and a lower chip including a peripheral circuit region (PERI) are manufactured, respectively, and then the memory device (500) may be manufactured by connecting the first upper chip, the second upper chip, and the lower chip to each other by a bonding method. The first upper chip may be inverted and connected to the lower chip by a bonding method, and the second upper chip may also be inverted and connected to the first upper chip by a bonding method. In the following description, the upper and lower portions of the first and second upper chips are defined based on a time before the first upper chip and the second upper chip are inverted. That is, in FIG. 17, the upper portion of the lower chip means the upper portion defined based on the +Z-axis direction, and the upper portions of each of the first and second upper chips mean the upper portions defined based on the -Z-axis direction. However, this is merely exemplary, and only one of the first upper chip and the second upper chip may be inverted and connected by a bonding method.

Each of the peripheral circuit area (PERI) and the first and second cell areas (CELL1, CELL2) of the memory device (500) may include an external pad bonding area (PA), a word line bonding area (WLBA), and a bit line bonding area (BLBA).

The peripheral circuit area (PERI) may include a first substrate (210) and a plurality of circuit elements (220a, 220b, 220c) formed on the first substrate (210). An interlayer insulating layer (215) including one or more insulating layers may be provided on the plurality of circuit elements (220a, 220b, 220c), and a plurality of metal wires connecting the plurality of circuit elements (220a, 220b, 220c) may be provided within the interlayer insulating layer (215). For example, the plurality of metal wires may include first metal wires (230a, 230b, 230c) each connected to a plurality of circuit elements (220a, 220b, 220c), and second metal wires (240a, 240b, 240c) formed on the first metal wires (230a, 230b, 230c). The plurality of metal wires may be formed of at least one of various conductive materials. For example, the first metal wires (230a, 230b, 230c) may be formed of tungsten having relatively high electrical resistivity, and the second metal wires (240a, 240b, 240c) may be formed of copper having relatively low electrical resistivity.

In this specification, only the first metal wiring (230a, 230b, 230c) and the second metal wiring (240a, 240b, 240c) are illustrated and described, but are not limited thereto, and at least one additional metal wiring may be further formed on the second metal wiring (240a, 240b, 240c). In this case, the second metal wiring (240a, 240b, 240c) may be formed of aluminum. In addition, at least some of the additional metal wirings formed on the second metal wiring (240a, 240b, 240c) may be formed of copper or the like having lower electrical resistivity than the aluminum of the second metal wiring (240a, 240b, 240c).

The interlayer insulating layer (215) is disposed on the first substrate (210) and may include an insulating material such as silicon oxide, silicon nitride, etc.

The first and second cell regions (CELL1, CELL2) may each include at least one memory block. The first cell region (CELL1) may include a second substrate (310) and a common source line (320). On the second substrate (310), a plurality of word lines (331-338; 330) may be stacked along a direction perpendicular to an upper surface of the second substrate (Z-axis direction) of the second substrate (310). String selection lines and ground selection lines may be arranged above and below the word lines (330), and a plurality of word lines (330) may be arranged between the string selection lines and the ground selection line. Similarly, the second cell region (CELL2) includes a third substrate (410) and a common source line (420), and a plurality of word lines (431-438: 430) may be stacked along a direction perpendicular to an upper surface of the third substrate (Z-axis direction) of the third substrate (410). The second substrate (310) and the third substrate (410) may be made of various materials, and may be, for example, a silicon substrate, a silicon-germanium substrate, a germanium substrate, or a substrate having a single-crystal epitaxial layer grown on a monocrystalline silicon substrate. A plurality of channel structures (CH) may be formed in each of the first and second cell regions (CELL1, CELL2).

In one embodiment, as illustrated in A1, a channel structure (CH) is provided in a bit line bonding area (BLBA) and may extend in a direction perpendicular to a top surface of a second substrate (310) to penetrate word lines (330), string selection lines, and ground selection lines. The channel structure (CH) may include a data storage layer, a channel layer, and a buried insulating layer, etc. The channel layer may be electrically connected to a first metal wiring (350c) and a second metal wiring (360c) in the bit line bonding area (BLBA). For example, the second metal wiring (360c) may be a bit line and may be connected to the channel structure (CH) through the first metal wiring (350c). The bit line (360c) may extend along a first direction (Y-axis direction) parallel to a top surface of the second substrate (310).

In one embodiment, as illustrated in A2, the channel structure (CH) may include a lower channel (LCH) and an upper channel (UCH) that are connected to each other. For example, the channel structure (CH) may be formed through a process for the lower channel (LCH) and a process for the upper channel (UCH). The lower channel (LCH) may extend in a direction perpendicular to the upper surface of the second substrate (310) and may penetrate the common source line (320) and the lower word lines (331, 332). The lower channel (LCH) may include a data storage layer, a channel layer, a buried insulating layer, and the like, and may be connected to the upper channel (UCH). The upper channel (UCH) may penetrate the upper word lines (333 to 338). The upper channel (UCH) may include a data storage layer, a channel layer, and a buried insulating layer, and the channel layer of the upper channel (UCH) may be electrically connected to the first metal wiring (350c) and the second metal wiring (360c). As the length of the channel increases, it may become difficult to form a channel having a constant width due to process reasons. The memory device (500) according to an embodiment of the present invention may have a channel having improved width uniformity through the lower channel (LCH) and the upper channel (UCH) formed through a sequential process.

When the channel structure (CH) is formed to include a lower channel (LCH) and an upper channel (UCH) as illustrated in A2, a word line located near a boundary between the lower channel (LCH) and the upper channel (UCH) may be a dummy word line. For example, the word line (332) and the word line (333) forming the boundary between the lower channel (LCH) and the upper channel (UCH) may be a dummy word line. In this case, data may not be stored in memory cells connected to the dummy word line. Alternatively, the number of pages corresponding to the memory cells connected to the dummy word line may be less than the number of pages corresponding to the memory cells connected to the general word line. A voltage level applied to the dummy word line may be different from a voltage level applied to a general word line, and thus, an impact of an uneven channel width between the lower channel (LCH) and the upper channel (UCH) on the operation of the memory device may be reduced.

Meanwhile, in A2, the number of lower word lines (331, 332) through which the lower channel (LCH) penetrates is illustrated as being less than the number of upper word lines (333 to 338) through which the upper channel (UCH) penetrates. However, this is exemplary and the present invention is not limited thereto. As another example, the number of lower word lines through which the lower channel (LCH) penetrates may be formed to be equal to or greater than the number of upper word lines through which the upper channel (UCH) penetrates. In addition, the structure and connection relationship of the channel structure (CH) arranged in the first cell region (CELL1) described above may be equally applied to the channel structure (CH) arranged in the second cell region (CELL2).

In the bit line bonding area (BLBA), a first through electrode (THV1) may be provided in the first cell area (CELL1), and a second through electrode (THV2) may be provided in the second cell area (CELL2). As illustrated in FIG. 17, the first through electrode (THV1) may penetrate the common source line (320) and the plurality of word lines (330). However, this is exemplary, and the first through electrode (THV1) may further penetrate the second substrate (310). The first through electrode (THV1) may include a conductive material. Alternatively, the first through electrode (THV1) may include a conductive material surrounded by an insulating material. The second through electrode (THV2) may also be provided with the same shape and structure as the first through electrode (THV1).

In one embodiment, the first through-electrode (THV1) and the second through-electrode (THV2) may be electrically connected through the first through-metal pattern (372d) and the second through-metal pattern (472d). The first through-metal pattern (372d) may be formed at a lower end of the first upper chip including the first cell region (CELL1), and the second through-metal pattern (472d) may be formed at an upper end of the second upper chip including the second cell region (CELL2). The first through-electrode (THV1) may be electrically connected to the first metal wiring (350c) and the second metal wiring (360c). A lower via (371d) may be formed between the first through-electrode (THV1) and the first through-metal pattern (372d), and an upper via (471d) may be formed between the second through-electrode (THV2) and the second through-metal pattern (472d). The first through-hole metal pattern (372d) and the second through-hole metal pattern (472d) can be connected by a bonding method.

In addition, in the bit line bonding area (BLBA), an upper metal pattern (252) may be formed on the uppermost metal layer of the peripheral circuit area (PERI), and an upper metal pattern (392) having the same shape as the upper metal pattern (252) may be formed on the uppermost metal layer of the first cell area (CELL1). The upper metal pattern (392) of the first cell area (CELL1) and the upper metal pattern (252) of the peripheral circuit area (PERI) may be electrically connected to each other by a bonding method. In the bit line bonding area (BLBA), the bit line (360c) may be electrically connected to a page buffer included in the peripheral circuit area (PERI). For example, some of the circuit elements (220c) of the peripheral circuit area (PERI) may provide a page buffer, and the bit line (360c) may be electrically connected to the circuit elements (220c) providing the page buffer through the upper bonding metal (370c) of the first cell area (CELL1) and the upper bonding metal (270c) of the peripheral circuit area (PERI).

Continuing, with reference to FIG. 17, in the word line bonding area (WLBA), the word lines (330) of the first cell area (CELL1) may extend along a second direction (X-axis direction) parallel to the upper surface of the second substrate (310) and may be connected to a plurality of cell contact plugs (341-347; 340). A first metal wiring (350b) and a second metal wiring (360b) may be sequentially connected to upper portions of the cell contact plugs (340) connected to the word lines (330). The cell contact plugs (340) may be connected to the peripheral circuit area (PERI) through the upper bonding metal (370b) of the first cell area (CELL1) and the upper bonding metal (270b) of the peripheral circuit area (PERI) in the word line bonding area (WLBA).

The cell contact plugs (340) may be electrically connected to a row decoder included in the peripheral circuit area (PERI). For example, some of the circuit elements (220b) of the peripheral circuit area (PERI) provide a row decoder, and the cell contact plugs (340) may be electrically connected to the circuit elements (220b) providing the row decoder through the upper bonding metal (370b) of the first cell area (CELL1) and the upper bonding metal (270b) of the peripheral circuit area (PERI). In one embodiment, the operating voltage of the circuit elements (220b) providing the row decoder may be different from the operating voltage of the circuit elements (220c) providing the page buffer. For example, the operating voltage of the circuit elements (220c) providing the page buffer may be higher than the operating voltage of the circuit elements (220b) providing the row decoder.

Similarly, in the word line bonding area (WLBA), the word lines (430) of the second cell area (CELL2) may extend along a second direction (X-axis direction) parallel to the upper surface of the third substrate (410) and may be connected to a plurality of cell contact plugs (441-447; 440). The cell contact plugs (440) may be connected to the peripheral circuit area (PERI) through the upper metal pattern of the second cell area (CELL2), the lower metal pattern and the upper metal pattern of the first cell area (CELL1), and the cell contact plug (348).

In the word line bonding area (WLBA), an upper bonding metal (370b) may be formed in the first cell area (CELL1), and an upper bonding metal (270b) may be formed in the peripheral circuit area (PERI). The upper bonding metal (370b) of the cell area (CELL1) and the upper bonding metal (270b) of the peripheral circuit area (PERI) may be electrically connected to each other by a bonding method. The upper bonding metal (370b) and the upper bonding metal (270b) may be formed of aluminum, copper, tungsten, or the like.

In the external pad bonding area (PA), a lower metal pattern (371e) may be formed on a lower portion of the first cell area (CELL1), and an upper metal pattern (472a) may be formed on an upper portion of the second cell area (CELL2). The lower metal pattern (371e) of the first cell area (CELL1) and the upper metal pattern (472a) of the second cell area (CELL2) may be connected by a bonding method in the external pad bonding area (PA). Similarly, the upper metal pattern (372a) may be formed on an upper portion of the first cell area (CELL1), and the upper metal pattern (272a) may be formed on an upper portion of the peripheral circuit area (PERI). The upper metal pattern (372a) of the first cell area (CELL1) and the upper metal pattern (272a) of the peripheral circuit area (PERI) may be connected by a bonding method.

Common source line contact plugs (380, 480) may be arranged in the external pad bonding area (PA). The common source line contact plugs (380, 480) may be formed of a conductive material such as a metal, a metal compound, or doped polysilicon. The common source line contact plug (380) of the first cell region (CELL1) may be electrically connected to the common source line (320), and the common source line contact plug (480) of the second cell region (CELL2) may be electrically connected to the common source line (420). A first metal wiring (350a) and a second metal wiring (360a) may be sequentially stacked on top of a common source line contact plug (380) of a first cell region (CELL1), and a first metal wiring (450a) and a second metal wiring (460a) may be sequentially stacked on top of a common source line contact plug (480) of a second cell region (CELL2).

Input/output pads (205, 405, 406) may be arranged in the external pad bonding area (PA). Referring to FIG. 17, a lower insulating film (201) may cover a lower surface of a first substrate (210), and a first input/output pad (205) may be formed on the lower insulating film (201). The first input/output pad (205) is connected to at least one of a plurality of circuit elements (220a) arranged in a peripheral circuit area (PERI) through a first input/output contact plug (203), and may be separated from the first substrate (210) by the lower insulating film (201). In addition, a side insulating film may be arranged between the first input/output contact plug (203) and the first substrate (210) to electrically separate the first input/output contact plug (203) and the first substrate (210).

An upper insulating film (401) covering an upper surface of the third substrate (410) may be formed on an upper portion of the third substrate (410). A second input/output pad (405) and/or a third input/output pad (406) may be arranged on the upper insulating film (401). The second input/output pad (405) may be connected to at least one of a plurality of circuit elements (220a) arranged in a peripheral circuit area (PERI) through second input/output contact plugs (403, 303), and the third input/output pad (406) may be connected to at least one of a plurality of circuit elements (220a) arranged in a peripheral circuit area (PERI) through third input/output contact plugs (404, 304).

In one embodiment, the third substrate (410) may not be disposed in the area where the input/output contact plug is disposed. For example, as illustrated in B, the third input/output contact plug (404) may be separated from the third substrate (410) in a direction parallel to the upper surface of the third substrate (410) and may be connected to the third input/output pad (406) by penetrating the interlayer insulating layer (415) of the second cell area (CELL2). In this case, the third input/output contact plug (404) may be formed by various processes.

For example, as illustrated in B1, the third input/output contact plug (404) may be formed to extend in the third direction (Z-axis direction) and have a diameter that increases as it goes toward the upper insulating film (401). That is, while the diameter of the channel structure (CH) described in A1 is formed to decrease as it goes toward the upper insulating film (401), the diameter of the third input/output contact plug (404) may be formed to increase as it goes toward the upper insulating film (401). For example, the third input/output contact plug (404) may be formed after the second cell region (CELL2) and the first cell region (CELL1) are bonded together.

In addition, as an example, as illustrated in B2, the third input/output contact plug (404) may be formed to extend in the third direction (Z-axis direction) and have a diameter that becomes smaller as it goes toward the upper insulating film (401). That is, the diameter of the third input/output contact plug (404) may be formed to become smaller as it goes toward the upper insulating film (401), similar to the channel structure (CH). For example, the third input/output contact plug (404) may be formed together with the cell contact plugs (440) before bonding of the second cell region (CELL2) and the first cell region (CELL1).

In another embodiment, the input/output contact plug may be arranged to overlap with the third substrate (410). For example, as illustrated in C, the second input/output contact plug (403) may be formed to penetrate the interlayer insulating layer (415) of the second cell region (CELL2) in the third direction (Z-axis direction), and may be electrically connected to the second input/output pad (405) through the third substrate (410). In this case, the connection structure of the second input/output contact plug (403) and the second input/output pad (405) may be implemented in various ways.

For example, as illustrated in C1, an opening (408) penetrating the third substrate (410) is formed, and the second input/output contact plug (403) can be directly connected to the second input/output pad (405) through the opening (408) formed in the third substrate (410). In this case, as illustrated in C1, the diameter of the second input/output contact plug (403) can be formed to increase as it goes toward the second input/output pad (405). However, this is exemplary, and the diameter of the second input/output contact plug (403) can also be formed to decrease as it goes toward the second input/output pad (405).

For example, as illustrated in C2, an opening (408) penetrating the third substrate (410) may be formed, and a contact (407) may be formed within the opening (408). One end of the contact (407) may be connected to the second input/output pad (405), and the other end may be connected to the second input/output contact plug (403). Accordingly, the second input/output contact plug (403) may be electrically connected to the second input/output pad (405) through the contact (407) within the opening (408). In this case, as illustrated in C2, the diameter of the contact (407) may be formed to increase toward the second input/output pad (405), and the diameter of the second input/output contact plug (403) may be formed to decrease toward the second input/output pad (405). For example, the third input/output contact plug (403) may be formed together with the cell contact plugs (440) before the bonding connection between the second cell region (CELL2) and the first cell region (CELL1), and the contact (407) may be formed after the bonding connection between the second cell region (CELL2) and the first cell region (CELL1).

In addition, as an example, as shown in C3, a stopper (409) may be further formed on the upper surface of the opening (408) of the third substrate (410) compared to C2. The stopper (409) may be a metal wiring formed in the same layer as the common source line (420). However, this is an example, and the stopper (409) may be a metal wiring formed in the same layer as at least one of the word lines (430). The second input/output contact plug (403) may be electrically connected to the second input/output pad (405) through the contact (407) and the stopper (409).

Meanwhile, similarly to the second and third input/output contact plugs (403, 404) of the second cell region (CELL2), the second and third input/output contact plugs (303, 304) of the first cell region (CELL1) may be formed so that their diameters become smaller as they go toward the lower metal pattern (371e), or larger as they go toward the lower metal pattern (371e).

Meanwhile, according to embodiments, a slit (slit, 411) may be formed in the third substrate (410). For example, the slit (411) may be formed at an arbitrary position in the external pad bonding area (PA). For example, as shown in D, the slit (411) may be positioned between the second input/output pad (405) and the cell contact plugs (440) when viewed from a planar view. However, this is exemplary, and the slit (411) may be formed such that the second input/output pad (405) is positioned between the slit (411) and the cell contact plugs (440) when viewed from a planar view.

For example, as shown in D1, a slit (411) may be formed to penetrate the third substrate (410). The slit (411) may be used, for example, to prevent the third substrate (410) from being finely cracked when forming the opening (408). However, this is exemplary, and the slit (411) may be formed to a depth of about 60 to 70% of the thickness of the third substrate (410).

In addition, as an example, a conductive material (412) may be formed within the slit (411), as illustrated in D2. The conductive material (412) may be used, for example, to discharge leakage current generated during operation of circuit elements within the external pad bonding area (PA) to the outside. In this case, the conductive material (412) may be connected to an external ground line.

In addition, as an example, as illustrated in D3, an insulating material (413) may be formed within the slit (411). The insulating material (413) may be formed, for example, to electrically isolate the second input/output pad (405) and the second input/output contact plug (403) disposed in the external pad bonding area (PA) from the word line bonding area (WLBA). By forming the insulating material (413) within the slit (411), it is possible to block a voltage provided through the second input/output pad (405) from affecting the metal layer disposed on the third substrate (410) within the word line bonding area (WLBA).

Meanwhile, according to embodiments, the first to third input/output pads (205, 405, 406) may be formed selectively. For example, the memory device (500) may be implemented to include only the first input/output pad (205) disposed on the upper portion of the first substrate (201), or only the second input/output pad (405) disposed on the upper portion of the third substrate (410), or only the third input/output pad (406) disposed on the upper portion of the upper insulating film (401).

Meanwhile, according to embodiments, at least one of the second substrate (310) of the first cell region (CELL1) and the third substrate (410) of the second cell region (CELL2) can be used as a sacrificial substrate and can be completely or partially removed before or after the bonding process. An additional film can be laminated after the substrate removal. For example, the second substrate (310) of the first cell region (CELL1) can be removed before or after bonding of the peripheral circuit region (PERI) and the first cell region (CELL1), and an insulating film covering the upper surface of the common source line (320) or a conductive film for connection can be formed. Similarly, the third substrate (410) of the second cell region (CELL2) can be removed before or after bonding of the first cell region (CELL1) and the second cell region (CELL2), and an upper insulating film (401) covering the upper surface of the common source line (420) or a conductive film for connection can be formed.

The memory device (500) can perform the weak pattern detection operation and encoding operation described with reference to FIGS. 1 to 16. The memory device (500) can improve reliability by removing weak patterns.

Where one or more embodiments may be implemented differently, the order of particular processes or steps may be performed differently from the order described. For example, two processes described sequentially may be performed substantially concurrently or in the reverse order from the order described.

The above-described contents are specific embodiments for carrying out the present disclosure. The present disclosure will include not only the above-described embodiments, but also embodiments that are simply designed or can be easily changed. In addition, the present disclosure will also include technologies that can be easily modified and implemented using the embodiments. Therefore, the scope of the present disclosure should not be limited to the above-described embodiments, but should be determined by the claims and their equivalents as well as the claims of this invention.

Claims (10)

A method of operating a nonvolatile memory device comprising a plurality of memory blocks formed in a direction perpendicular to a substrate and having a plurality of strings connected between bit lines and a common source line,
A step of detecting first memory cells having an erased state among memory cells connected to a first word line;
A step of detecting second memory cells having a sixth program state or a seventh program state among memory cells connected to a second word line adjacent to the first word line;
A step of detecting target bit lines including both a first memory cell and a second memory cell;
A step of detecting target bits corresponding to a target bit line and corresponding to an erase state in write data to be programmed in memory cells connected to a third word line adjacent to the second word line;
A step of generating flip bit position data based on the above target bits;
A step of generating flipped data by flipping the target bits among the above write data; and
A step of programming the flipped data and the flip bit position data into the third word line,
Each of the plurality of strings includes a plurality of memory cells, the plurality of memory cells are divided into a first region and a second region, the first region is divided into first to third portions, the write data includes first to third page data, and each of the plurality of memory cells is programmed to have one of an erase state and first to seventh program states.
An operating method in which, when the first sub-target bits of the target bits correspond to the first portion, the second sub-target bits of the target bits correspond to the second portion, and the third sub-target bits of the target bits correspond to the third portion, data corresponding to the first sub-target bits of the first page data are flipped, data corresponding to the second sub-target bits of the second page data are flipped, and data corresponding to the third sub-target bits of the third page data are flipped. In paragraph 1,
In response to a read command, reading the flipped data and the flip bit position data from the third word line; and
A method comprising the step of generating decoded data by flipping flipped bits among the flipped data based on the flip bit position data. In paragraph 1,
The step of programming the flipped data and the flip bit position data into the third word line is:
A step of programming the memory cells corresponding to the first sub-target bits to be in a first program state;
A step of programming the memory cell corresponding to the second sub-target bits to be in a seventh program state; and
An operating method comprising the step of programming a memory cell corresponding to the third sub-target bits to be in a fifth program state. In paragraph 1,
The step of programming the flipped data and the flip bit position data into the third word line is:
An operating method comprising the steps of programming the flipped data into memory cells corresponding to a first area of a third word line, and programming the flipped bit position data into memory cells corresponding to a second area of the third word line. In paragraph 1,
The above write data contains multiple chunks,
The step of generating flipped data by flipping the target bits among the above write data is:
A step of detecting bits included in the same chunk as the above target bits as target neighboring bits;
a step of flipping data corresponding to the above target bits; and
An operating method further comprising the step of flipping data corresponding to the target neighboring bits. In paragraph 5,
If the first sub-neighboring bits among the target neighboring bits correspond to the first part, the second sub-neighboring bits among the target neighboring bits correspond to the second part, and the third sub-neighboring bits among the target neighboring bits correspond to the third part,
An operating method in which data corresponding to the first sub-neighboring bits of the first page data are flipped, data corresponding to the second sub-neighboring bits of the second page data are flipped, and data corresponding to the third sub-neighboring bits of the third page data are flipped. In paragraph 1,
The step of detecting first memory cells having an erased state among memory cells connected to the first word line is:
Comprising a step of performing a first sensing operation on the first word line using a first read voltage,
The step of detecting second memory cells having a sixth program state or a seventh program state among memory cells connected to a second word line adjacent to the first word line is:
A method of operation comprising the step of performing a second sensing operation on a second word line using a sixth read voltage. In paragraph 7,
A step of storing a first bitmap generated by the first sensing operation in a first data latch;
A step of storing a second bitmap generated by the second sensing operation in a second data latch; and
An operating method further comprising the step of performing an AND operation on the first bitmap stored in the first data latch and the second bitmap stored in the second data latch to generate a third bitmap, and storing the third bitmap in the first data latch. In Article 8,
A step of receiving the above write data from an external source;
A step of storing the first page data in the second data latch;
A step of storing the second page data in a third data latch; and
An operating method comprising the step of storing the third page data in a fourth data latch. A method of operating a nonvolatile memory device comprising a plurality of memory blocks formed in a direction perpendicular to a substrate, comprising a plurality of memory cells, and having a plurality of strings connected between bit lines and a common source line,
A step of performing a first sensing operation on a first word line using a first read voltage to generate a first bitmap pointing to a first memory cell corresponding to an erase state among memory cells connected to the first word line;
A step of performing a second sensing operation on a second word line adjacent to the first word line using a sixth read voltage to generate a second bitmap indicating second memory cells having a sixth program state or a seventh program state among memory cells connected to the second word line;
A step of performing an AND operation on the first bitmap and the second bitmap to generate a third bitmap pointing to target bit lines including both the first memory cell and the second memory cell;
A step of receiving write data to be programmed into memory cells connected to a third word line adjacent to the second word line from the outside;
A step of generating a fourth bitmap (BM4) indicating target bits corresponding to a weak pattern by performing an AND operation on the third bitmap and the write data;
A step of generating flip bit position data based on the above fourth bitmap;
A step of generating encoded data by performing a flip operation based on the above write data and flip bit position data; and
An operational method comprising the step of programming the encoded data into memory cells connected to the third word line.

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