KR20120029266A - Liquid crystal display device - Google Patents

Liquid crystal display device Download PDF

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Publication number
KR20120029266A
KR20120029266A KR1020100091254A KR20100091254A KR20120029266A KR 20120029266 A KR20120029266 A KR 20120029266A KR 1020100091254 A KR1020100091254 A KR 1020100091254A KR 20100091254 A KR20100091254 A KR 20100091254A KR 20120029266 A KR20120029266 A KR 20120029266A
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South Korea
Prior art keywords
data
line
common voltage
lines
pixel
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KR1020100091254A
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Korean (ko)
Inventor
정영민
Original Assignee
엘지디스플레이 주식회사
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Priority to KR1020100091254A priority Critical patent/KR20120029266A/en
Publication of KR20120029266A publication Critical patent/KR20120029266A/en

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    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1345—Conductors connecting electrodes to cell terminals
    • G02F1/13454—Drivers integrated on the active matrix substrate
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136286—Wiring, e.g. gate line, drain line
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3648—Control of matrices with row and column drivers using an active matrix
    • G09G3/3659—Control of matrices with row and column drivers using an active matrix the addressing of the pixel involving the control of two or more scan electrodes or two or more data electrodes, e.g. pixel voltage dependant on signal of two data electrodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film

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  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Optics & Photonics (AREA)
  • Mathematical Physics (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Theoretical Computer Science (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Liquid Crystal (AREA)
  • Liquid Crystal Display Device Control (AREA)
  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)

Abstract

PURPOSE: An LCD is provided to offer a common voltage supplying line arranged in parallel to data line for a fixed pixel, and arrange a thin film transistor in an odd number horizontal line and an even number horizontal line in a zigzag pattern. CONSTITUTION: An LCD(100) comprises a common voltage supplying line for at least two or more neighboring pixel areas. The common voltage supplying line is arranged in parallel to a plurality of data line. A gate driver(110) supplies a scan signal to a plurality of gate lines. A data driver(120) supplies data voltage to a plurality of data lines. A timing controller(130) controls the gate driver and the data driver.

Description

[0001] Liquid crystal display device [0002]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display device, and more particularly, to a liquid crystal display device capable of improving image quality by providing an optimal common voltage for each pixel position.

In general, a liquid crystal display device includes a liquid crystal display panel in which a thin film transistor array substrate and a color filter substrate are bonded to a predetermined cell gap, and a liquid crystal layer is formed in a space between the cell gaps, and the liquid crystal display panel is driven. And a driving unit for displaying an image.

The thin film transistor array substrate has a plurality of gate lines formed in a lateral direction and a plurality of gate lines formed in a longitudinal direction intersecting with each other, and a plurality of regions defined by the intersection of the gate lines and the data lines are defined as pixels. do. The pixel includes a switching element and a pixel electrode.

In the color filter substrate, red, green, and blue color filters are formed at positions corresponding to the pixels, and a black matrix for preventing color interference of light passing through the pixels is formed in a net shape surrounding the color filter. Is formed. In addition, a common electrode for applying an electric field to the liquid crystal is formed on the front surface of the color filter substrate together with the pixel electrode of the thin film transistor array substrate.

BACKGROUND ART Liquid crystal display devices used in recent years generally adopt twisted nematic (TN) liquid crystals. The twisted nematic liquid crystal is driven by the vertical electric field of the pixel electrode formed on the thin film transistor array substrate and the common electrode formed on the color filter substrate, so that the light transmittance varies depending on the viewing angle. In particular, since the light transmittance is distributed asymmetrically with respect to the viewing angle in the vertical direction, a range in which the image is inverted in the vertical direction occurs and the viewing angle is narrowed. Therefore, when the twisted nematic liquid crystal is applied, a large area liquid crystal display device is limited.

In order to solve the above problems, a transverse electric field type liquid crystal display device for driving a liquid crystal by a horizontal electric field has been proposed.

The transverse electric field type liquid crystal display device can improve the viewing angle characteristics such as contrast, gray inversion, and color shift, compared to the liquid crystal display device driven by the vertical electric field, thereby securing a wide viewing angle. Is widely used in the production of liquid crystal display devices.

In general, a liquid crystal display device driven in a transverse electric field method includes a plurality of pixel regions defined by a plurality of gate lines and a plurality of data lines arranged to intersect the plurality of gate lines. It further includes a plurality of common voltage supply lines arranged in parallel with the plurality of gate lines and supplying a common voltage.

The liquid crystal cell positioned in the pixel area is driven by the potential difference between the data voltage provided to the data line and the common voltage Vcom provided to the common voltage supply line. The pixel region of the liquid crystal display includes a gate line controlling the thin film transistor, a data line providing a data voltage to the pixel electrode, and a common voltage supply line supplying a common voltage Vcom.

In particular, the common voltage supply line provided in the pixel region occupies an opening area of a predetermined region. In addition, since the common voltage Vcom having a predetermined level is supplied to the plurality of common voltage supply lines, a delay occurs due to line resistance or the like depending on the position of the pixel, and thus the common voltage (V) is provided to the pixel region according to the position. There is a problem that Vcom) is different.

When the common voltage Vcom is delayed due to line resistance or the like depending on the position of the pixel region, the image quality deteriorates.

According to the present invention, a common voltage supply line arranged in parallel along the data line is provided for each pixel, and thin film transistors positioned in the odd and even horizontal lines are arranged in a zigzag form, thereby optimizing the common common according to the position of the pixel region. An object of the present invention is to provide a liquid crystal display device capable of supplying a voltage Vcom.

A liquid crystal display according to an exemplary embodiment of the present invention includes a plurality of gate lines and a plurality of data lines that define a plurality of pixel regions, and the plurality of data lines for at least two adjacent pixel regions among the plurality of pixel regions. A liquid crystal display panel having a common voltage supply line arranged in parallel with each other, a gate driver supplying scan signals to the plurality of gate lines, a data driver supplying data voltages to the plurality of data lines, and the gate driver; A timing controller for controlling a data driver, wherein odd-numbered gate lines of the plurality of gate lines define a first horizontal line pixel portion as data lines positioned on a left side, and even-numbered gate lines on a right side Define a second horizontal line pixel portion with the first horizontal line The base portion includes first link lines electrically connected to the common voltage supply line, and the second horizontal line pixel portion includes second link lines electrically connected to a left data line arranged in at least two previous pixel regions. do.

The liquid crystal display according to the exemplary embodiment of the present invention includes one common voltage supply line parallel to the data line and connection lines electrically connected to the one common voltage supply line for each pixel area, and the odd and even horizontal lines are provided. By arranging the thin film transistors positioned in a line in a zigzag form, the common voltage Vcom may be supplied according to the position of the pixel region, and the common voltage Vcom may swing for each horizontal line.

1 is a view showing a liquid crystal display device according to an embodiment of the present invention.
FIG. 2 is a schematic view of the liquid crystal display panel of FIG. 1.
3 is a view showing another embodiment of the liquid crystal display panel of FIG. 1.

Hereinafter, embodiments according to the present invention will be described with reference to the accompanying drawings.

1 is a view showing a liquid crystal display device according to an embodiment of the present invention.

As shown in FIG. 1, in the liquid crystal display according to the exemplary embodiment of the present invention, a plurality of gate lines GL and a plurality of data lines DL intersect with each other to drive the liquid crystal cell Clc at an intersection thereof. A liquid crystal display panel 100 having a thin film transistor TFT, a gate driver 110 for supplying a scan signal to the gate line GL, and a data driver for supplying a data voltage to the data line DL. And a timing controller 130 for controlling the gate driver 110 and the data driver 120, and a backlight unit 160 for providing light to the liquid crystal display panel 100.

The liquid crystal panel 100 has a liquid crystal layer formed between two glass substrates, a plurality of gate lines GL and a plurality of data lines DL are formed on the lower glass substrate, and the plurality of gate lines GL. ) And a thin film transistor TFT are formed at the intersection of the plurality of data lines DL. The thin film transistor TFT supplies data from the data line DL to the liquid crystal cell Clc in response to a scan signal from the gate line GL.

To this end, the gate electrode of the thin film transistor TFT is connected to the gate line GL, the source electrode is connected to the data line DL, and the drain electrode is connected to the pixel electrode of the liquid crystal cell Clc.

In addition, a storage capacitor Cst is formed on the lower glass substrate of the liquid crystal display panel 100 to maintain the voltage of the liquid crystal cell Clc. The storage capacitor Cst may be formed between the liquid crystal cell Clc and the front gate line, or may be formed between the liquid crystal cell Clc and a separate common line.

On the upper glass substrate of the liquid crystal display panel 100, color filters of R, G, and B colors corresponding to each pixel area in which the thin film transistor TFT is formed, and each of them border the gate line GL, And a black matrix covering the data line DL and the thin film transistor TFT.

The gate driver 110 supplies a plurality of scan signals to the plurality of gate lines GL in response to the gate control signal GCS from the timing controller 130. These plurality of scan signals cause the plurality of gate lines GL to be sequentially enabled by one period of one horizontal synchronization signal. The gate driver 110 may include a plurality of gate driver integrated circuits.

The data driver 120 includes a data voltage generator 140 that provides data voltages to a plurality of data lines DL, and a common voltage generator 150 that provides a common voltage Vcom to the liquid crystal display panel 100. ).

The data voltage generator 140 generates a data voltage whenever one of the plurality of gate lines GL is enabled in response to the data control signals DCS from the timing controller 130. The plurality of data lines DL of the liquid crystal display panel 100 are respectively supplied.

The common voltage generator 150 generates a common voltage Vcom that swings by inverting polarity for each horizontal line and supplies it to the liquid crystal display panel 100.

The timing controller 130 may enable data synchronization and synchronization signals Vsync and Hsync supplied from an external system (for example, a graphic module of a computer system or an image demodulation module of a television reception system, not shown). The gate control signal GCS for controlling the gate driver 110 and the data control signal DCCS for controlling the data driver 120 are generated using the signal DE and the clock signal CLK.

In addition, the timing controller 130 arranges the image data V-data input from an external system and supplies the sorted data Data to the data driver 120.

The backlight unit 160 may include a light source (not shown) for generating light, an optical sheet for improving optical characteristics of the light emitted from the light source, and the like.

As shown in FIG. 2, the liquid crystal display panel 100 includes first to second gate lines GL1 and GL2 and first to second intersections with the first and second gate lines GL1 and GL2. And a common voltage supply line VL arranged in parallel with the four data lines DL1 to DL4 and the first to fourth data lines DL1 to DL4.

A plurality of pixel areas include the first and second gate lines GL1 and GL2 and the first to fourth data lines DL1 to DL4 arranged to intersect the first and second gate lines GL1 and GL2. And a thin film transistor (TFT), which is a switching element, is formed at the crossing portion.

Among the pixel areas, the pixel area defined by the first gate line GL1 (hereinafter, referred to as a “first horizontal line pixel part”) may be electrically connected to the common voltage supply line VL. Third link lines LL1 to LL3 are included. Each pixel area included in the first horizontal line pixel part further includes a storage capacitor Cst formed between the thin film transistor TFT and the first to third link lines LL1 to LL3.

The first link line LL1 includes a first pixel area P1 defined by a first gate line GL1 and a first data line DL1, a first gate line GL1, and a second data line The common voltage supply line VL across the second pixel region P2 defined by DL2 and the third pixel region P3 defined by the first gate line GL1 and the third data line DL3. And electrically connected.

The second link line LL2 is electrically connected to the common voltage supply line VL across the second and third pixel areas P2 and P3, and the third link line LL3 is connected to the third pixel area ( It is electrically connected to the common voltage supply line VL through P3).

Among the pixel areas, the pixel area defined by the second gate line GL2 (hereinafter, referred to as a “second horizontal line pixel portion”) may include fourth to fourth electrically connected to the first data line DL1. Sixth link lines LL4 to LL6 are included. Similarly, the second horizontal line pixel part includes a storage capacitor Cst formed between the thin film transistor TFT and the fourth to sixth link lines LL4 to LL6.

The sixth link line LL6 includes the sixth pixel region P6 defined by the second gate line GL2 and the third data line DL3, the second gate line GL2, and the second data line. The first data line DL1 across the fifth pixel region P5 defined by DL2 and the fourth pixel region P4 defined by the second gate line GL2 and the first data line DL1. Is electrically connected).

The fifth link line LL5 is electrically connected to the first data line DL1 over the fourth and fifth pixel areas P4 and P5, and the sixth link line LL6 is connected to the fourth pixel. It is electrically connected to the first data line DL1 over an area P4.

In this case, the thin film transistors TFT provided in the first horizontal line pixel portion are electrically connected to the data line positioned on the left side, and the thin film transistors TFT provided in the second horizontal line pixel portion are data positioned on the right side. It is electrically connected to the line. Therefore, the thin film transistor TFT positioned in the first horizontal line pixel portion defined by the first gate line GL1 and the thin film transistor positioned in the second horizontal line pixel portion defined by the second gate line GL2 may be formed. TFTs are arranged in a zigzag form.

The common voltage supply line VL is arranged in parallel with the data lines DL1 to DL4, one for each of three adjacent pixel areas. For convenience, in the exemplary embodiment of the present invention, the common voltage supply line VL is arranged in parallel with the data lines DL1 to DL4 for each of three adjacent pixel areas, but is not limited thereto.

The common voltage supply line VL electrically connected to the first to third pixel areas P1 to P3 provided in the first horizontal line pixel part may have a data driver when the odd-numbered gate line is driven. The common voltage Vcom of the positive polarity is provided from the common voltage generator 150 of 120.

The common voltage supply line VL is provided with a data voltage from the data voltage generator 140 of the data driver 120 when the even-numbered gate line is driven. When the positive common voltage Vcom is applied to the common voltage supply line VL, the common voltage Vcom of the positive polarity is applied through the first to third link lines LL1 to LL3. ) Are provided in the first to third pixel areas P1 to P3 electrically connected to the first horizontal line pixel part.

The first data line DL1 electrically connected to the fourth to sixth pixel areas P4 to P6 provided in the second horizontal line pixel part is the data driver 120 when the odd-numbered gate line is driven. The data voltage is provided from the data voltage generator 140.

When the even-numbered gate line is driven, the first data line DL1 is provided with a negative common voltage Vcom from the common voltage generator 150 of the data driver 120. When the negative common voltage Vcom is applied to the first data line DL1, the negative common voltage Vcom is applied through the fourth to sixth link lines LL4 to LL6. And the fourth to sixth pixel areas P4 to P6 of the second horizontal line pixel portion electrically connected to the DL1.

As such, when the first gate line GL1, which is the odd-numbered gate line, is driven, the first to third pixel areas P1 to 3 included in the first horizontal line pixel part defined by the first gate line GL1. The common voltage Vcom having a positive polarity is supplied to P3) through the common voltage supply line VL.

When the second gate line GL2, which is the even-numbered gate line, is driven, the fourth to sixth pixel regions P4 to P6 provided in the pixel portion of the second horizontal line defined by the second gate line GL2. The negative common voltage Vcom is supplied through the first data line DL1.

As a result, the liquid crystal display panel 100 is supplied with a common voltage Vcom having a polarity inverted for each horizontal line in a swinging manner. Since the common voltage supply line VL arranged in the liquid crystal display panel 100 is formed for each of three adjacent pixels, the aperture ratio is reduced compared to the conventional case in which the common voltage supply line arranged in parallel with the gate line is formed for each pixel. Can be.

In addition, the common voltage supply line (VL) and the common voltage whose polarity is inverted into the data line are supplied through the data driver (120 of FIG. 1) for each horizontal line. Compared to the conventional case in which a level common voltage is supplied and influenced by line resistance, the optimum common voltage can be supplied for each pixel position.

Thus, the liquid crystal display according to the present invention can improve the image quality as the optimum common voltage is provided according to the position of the pixel.

3 is a view showing another embodiment of the liquid crystal display panel of FIG. 1.

As shown in FIG. 1 and FIG. 3, the liquid crystal display panel 200 includes first and second gate lines GL1 and GL2 and first and second gate lines GL1 and GL2 intersecting the first and second gate lines GL1 and GL2. And a common voltage supply line VL arranged in parallel to the third to third data lines DL1 to DL3 and the first to third data lines DL1 to DL3.

A plurality of pixel areas include the first and second gate lines GL1 and GL2 and the first to third data lines DL1 to DL3 arranged to intersect the first and second gate lines GL1 and GL2. At the intersection thereof, a thin film transistor (TFT), which is a switching element, is formed.

Among the pixel areas, a pixel area defined by the first gate line GL1 (hereinafter, referred to as a “first horizontal line pixel portion”) may be electrically connected to the common voltage supply line VL. Second link lines LL1 and LL2 are included. Each pixel area included in the first horizontal line pixel part further includes a storage capacitor Cst formed between the thin film transistor TFT and the first and second link lines LL1 and LL2.

The first link line LL1 includes a first pixel area P1 defined by a first gate line GL1 and a first data line DL1, a first gate line GL1, and a second data line It is electrically connected to the common voltage supply line VL across the second pixel region P2 defined by DL2. The second link line LL2 is electrically connected to the common voltage supply line VL across the second pixel region P2.

Among the pixel areas, a pixel area defined by the second gate line GL2 (hereinafter, referred to as a “second horizontal line pixel portion”) may include a third and second electrical connection with the first data line DL1. Fourth link lines LL3 and LL4 are included. Similarly, the second horizontal line pixel part may include a storage capacitor Cst formed between the thin film transistor TFT and the third and fourth link lines LL3 and LL4.

The fourth link line LL4 is electrically connected to the first data line DL1 across the third and fourth pixel areas P3 and P4, and the third link line LL3 is connected to the third pixel. It is electrically connected to the first data line DL1 over an area P3.

In this case, the thin film transistors TFT provided in the first horizontal line pixel portion are electrically connected to the data line positioned on the left side, and the thin film transistors TFT provided in the second horizontal line pixel portion are data positioned on the right side. It is electrically connected to the line. Therefore, the thin film transistor TFT positioned in the first horizontal line pixel portion defined by the first gate line GL1 and the thin film transistor positioned in the second horizontal line pixel portion defined by the second gate line GL2 may be formed. TFTs are arranged in a zigzag form.

The common voltage supply line VL is arranged in parallel with the data lines DL1 to DL3 for each of two adjacent pixel areas.

The common voltage supply line VL electrically connected to the first and second pixel areas P1 and P2 provided in the first horizontal line pixel part is a data driver when the odd-numbered gate line is driven. The common voltage Vcom of the positive polarity is provided from the common voltage generator 150 of 120.

The common voltage supply line VL is provided with a data voltage from the data voltage generator 140 of the data driver 120 when the even-numbered gate line is driven. When a positive common voltage Vcom is applied to the common voltage supply line VL, the common voltage Vcom of the positive polarity is applied to the common voltage supply line VL through the first and second link lines LL1 and LL2. Are provided in the first and second pixel regions P1 and P2 electrically connected to the first horizontal line pixel portion.

The first data line DL1 electrically connected to the third and fourth pixel areas P3 and P4 of the second horizontal line pixel part may have a data driver 120 when the odd-numbered gate line is driven. The data voltage is provided from the data voltage generator 140.

When the even-numbered gate line is driven, the first data line DL1 is provided with a negative common voltage Vcom from the common voltage generator 150 of the data driver 120. When the negative common voltage Vcom is applied to the first data line DL1, the negative common voltage Vcom is applied to the first data line through third and fourth link lines LL3 and LL4. The third and fourth pixel regions P3 and P4 of the second horizontal line pixel portion electrically connected to the DL1 are provided.

As such, when the first gate line GL1, the odd-numbered gate line, is driven, the first and second pixel regions P1, which are provided in the pixel portion of the first horizontal line defined by the first gate line GL1, The common voltage Vcom of positive polarity is supplied to P2) through the common voltage supply line VL.

When the second gate line GL2, which is the even-numbered gate line, is driven, the third and fourth pixel regions P3 and P4 of the second horizontal line pixel portion defined by the second gate line GL2 are driven. The negative common voltage Vcom is supplied through the first data line DL1.

As a result, the liquid crystal display panel 100 is supplied with a common voltage Vcom having a polarity inverted for each horizontal line in a swinging manner. Since the common voltage supply lines VL arranged in the liquid crystal display panel 100 are formed in two adjacent pixel regions, the common voltage supply line VL has an aperture ratio compared to the conventional case in which the common voltage supply lines arranged in parallel with the gate lines are formed for each pixel. Can be reduced.

In addition, the common voltage supply line (VL) and the common voltage whose polarity is inverted into the data line are supplied through the data driver (120 of FIG. 1) for each horizontal line. Compared to the conventional case in which a level common voltage is supplied and influenced by line resistance, the optimum common voltage can be supplied for each pixel position.

Thus, the liquid crystal display according to the present invention can improve the image quality as the optimum common voltage is provided according to the position of the pixel.

100, 200: liquid crystal display panel 110: gate driver
120: data driver 130: timing controller
140: data voltage generator 150: common voltage generator
160: backlight unit

Claims (6)

A plurality of gate lines and a plurality of data lines defining a plurality of pixel regions are arranged, and a common voltage supply line is arranged in parallel with the plurality of data lines in at least two adjacent pixel regions among the plurality of pixel regions. One liquid crystal display panel;
A gate driver supplying scan signals to the plurality of gate lines;
A data driver supplying data voltages to the plurality of data lines; And
And a timing controller controlling the gate driver and the data driver.
The odd-numbered gate lines of the plurality of gate lines define a first horizontal line pixel portion with data lines positioned on the left side, and the even-numbered gate lines define a second horizontal line pixel portion with data lines positioned on the right side.
The first horizontal line pixel portion includes first link lines electrically connected to the common voltage supply line, and the second horizontal line pixel portion is electrically connected to a left data line arranged in at least two previous pixel regions. And two link lines. The method according to claim 1,
And the data driver supplies a positive common voltage to the common voltage supply line when the odd gate lines are driven. The method of claim 2,
And the data driver supplies a data voltage to a left data line arranged in the at least two pixel areas when the odd gate lines are driven. The method according to claim 1,
And the data driver supplies a negative common voltage to a left data line arranged in the at least two pixel areas when the even-numbered gate lines are driven. The method of claim 4, wherein
And the data driver supplies a data voltage to the common voltage supply line when the even-numbered gate lines are driven. The method according to claim 1,
And the thin film transistor formed on the first horizontal line pixel portion and the thin film transistor formed on the second horizontal line pixel portion are arranged in a zigzag shape.
KR1020100091254A 2010-09-16 2010-09-16 Liquid crystal display device KR20120029266A (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9568792B2 (en) 2013-02-05 2017-02-14 Samsung Display Co., Ltd. Liquid crystal display

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9568792B2 (en) 2013-02-05 2017-02-14 Samsung Display Co., Ltd. Liquid crystal display
US10146097B2 (en) 2013-02-05 2018-12-04 Samsung Display Co., Ltd. Liquid crystal display

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