KR20080108866A - Data output controlling circuit of semiconductor memory apparatus - Google Patents

Data output controlling circuit of semiconductor memory apparatus Download PDF

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Publication number
KR20080108866A
KR20080108866A KR1020070056960A KR20070056960A KR20080108866A KR 20080108866 A KR20080108866 A KR 20080108866A KR 1020070056960 A KR1020070056960 A KR 1020070056960A KR 20070056960 A KR20070056960 A KR 20070056960A KR 20080108866 A KR20080108866 A KR 20080108866A
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KR
South Korea
Prior art keywords
signal
buffer
output
write
driving signal
Prior art date
Application number
KR1020070056960A
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Korean (ko)
Inventor
김용미
Original Assignee
주식회사 하이닉스반도체
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Application filed by 주식회사 하이닉스반도체 filed Critical 주식회사 하이닉스반도체
Priority to KR1020070056960A priority Critical patent/KR20080108866A/en
Publication of KR20080108866A publication Critical patent/KR20080108866A/en

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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
    • G11C7/1057—Data output buffers, e.g. comprising level conversion circuits, circuits for adapting load
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
    • G11C7/1063—Control signal output circuits, e.g. status or busy flags, feedback command signals
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/22—Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management 
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2207/00—Indexing scheme relating to arrangements for writing information into, or reading information out from, a digital store
    • G11C2207/22—Control and timing of internal memory operations
    • G11C2207/2227—Standby or low power modes

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Abstract

A data output controlling circuit of semiconductor memory apparatus is provided to increase the reliability of a chip by controlling an operation in the unnecessary area. In a data output controlling circuit of semiconductor memory apparatus, a buffer driving signal generator generates a buffer drive signal in response to a light signal from an external clock. An output enable signal generator generates the out enable signal from the buffer drive signal in response to the burst signal and read signal. A data strobe buffer part(400) generates a data strobe buffer output signal in response to the light signal.

Description

Data Output Controlling Circuit of Semiconductor Memory Apparatus

1 is a block diagram of a data output control circuit of a semiconductor memory device according to the prior art;

2 is a block diagram of a data output control circuit of a semiconductor memory device according to the present invention;

FIG. 3 is a detailed circuit diagram of the buffer driving signal controller shown in FIG. 2.

<Description of the symbols for the main parts of the drawings>

100: clock buffer 200/210: driver

300: output enable signal generator

400: data strobe buffer

500: buffer driving signal generating unit 510: buffer driving signal control unit

The present invention relates to a semiconductor memory device, and more particularly to a data output control circuit.

In the current semiconductor memory device, a continuous read operation is used. The data output control circuit of the semiconductor memory device using the read operation generates an internal clock signal by buffering an external clock, and generates a buffer driving signal by driving the internal clock signal. The data output control circuit generates an output enable signal using a read signal enabled during a read operation, the buffer driving signal, an output enable reset signal, and a burst signal.

1 is a block diagram of a data output control circuit of a conventional semiconductor memory device.

Referring to FIG. 1, when a power-up signal pwrup is activated in a data output control circuit of a conventional semiconductor memory device, the clock buffer unit 100 receives an internal clock signal Internal_CLK from an external clock signal pair CLK and CLKB. Create

The driver 200 drives the internal clock signal Internal_CLK to generate a buffer driving signal DQ_CLKD. The buffer driving signal DQ_CLKD is a signal used by the output enable signal generator 300 during a read operation.

The output enable signal generator 300 uses the buffer driving signal DQ_CLKD, the output enable reset signal OE_RST, the burst signal YBST, and the read signal RDS during a read operation. Outputs the enable signal OE. Here, the buffer driving signal DQ_CLKD performs a continuous toggle. The data strobe buffer unit 400 is aligned at the rising / falling timing of the buffer driving signal DQ_CLKD during read operation, and the data of the data output buffer are output. During the write operation, the data strobe buffer unit 400 is aligned at the rising / falling timing of the data strobe signal DQS and data of the data input buffers are input.

However, during the write operation, since the buffer driving signal DQ_CLKD which is not used is continuously toggled and input to the data strobe buffer unit 400, unnecessary current is consumed.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-described problem, and an object thereof is to provide a data output control circuit of a semiconductor memory device which reduces current by controlling an operation in an unnecessary section.

According to another aspect of the present invention, a data output control circuit of a semiconductor memory device may include a buffer driving signal generator configured to generate a buffer driving signal from an external clock in response to a write signal; An output enable signal generator configured to generate an output enable signal from the buffer driving signal in response to a burst signal and a read signal; And a data strobe buffer unit configured to generate a data strobe buffer output signal from the buffer driving signal or the data strobe signal in response to the write signal.

DETAILED DESCRIPTION Hereinafter, exemplary embodiments of the present invention will be described with reference to the accompanying drawings so that those skilled in the art may easily implement the technical idea of the present invention.

2 is a block diagram of a data output control circuit of a semiconductor memory device according to the present invention.

Referring to FIG. 2, the data output control circuit according to the present invention buffers external clock signal pairs CLK and CLKB in response to a power-up signal pwrup to generate an internal clock signal Internal_CLK 100. In response to a write signal WTS, a buffer driving signal controller 510 which generates a buffer clock signal DQ_CLK from the internal clock signal Internal_CLK, and the buffer clock signal DQ_CLK are driven to drive a buffer driving signal DQ_CLKD. ) Is outputted to the driving unit 210 for outputting the buffer driving signal DQ_CLKD, the read signal RDS, the burst signal YBST, and the output enable reset signal OE_RST. Output strobe buffer output signal DQSIR from the buffer drive signal DQ_CLKD or the data output strobe signal DQS in response to an output enable signal generator 300 for outputting Day to print And a strobe buffer 400. The Here, the clock buffer unit 100, the buffer driving signal control unit 510, and the driving unit 210 may be referred to as a buffer driving signal generating unit 500.

The buffer driving signal generation unit 500 enables the buffer driving signal DQ_CLKD when the write signal WTS is disabled, that is, during a read operation. When the write signal WTS is enabled, that is, when the write operation is performed, the buffer driving signal DQ_CLKD is disabled. In the read operation, the output enable signal generator 300 outputs the output enable signal OE from the buffer driving signal DQ_CLKD. In the write operation, the data strobe buffer unit 400 outputs the data strobe buffer output signal DQSIR from the data strobe signal DQS.

3 is a circuit diagram of the buffer driving signal controller shown in FIG. 2.

Referring to FIG. 3, the buffer driving signal controller 510 includes the first to third inverters IV1 to IV3, first and second NMOS transistors N1 and N2, and first and second NMOS transistors P1. , P2). The first inverter IV1 receives the write signal WTS and applies an output signal to the gates of the second inverter IV2 and the second NMOS transistor N2. The second inverter IV2 receives the output signal of the first inverter IV1 and applies the output signal to the gate of the first PMOS transistor P1. The first PMOS transistor P1 includes a gate connected to the output of the second inverter IV2 and a source voltage VDD. The second PMOS transistor N2 includes a gate configured to receive the internal clock signal Internal_CLK, a source connected to the drain of the first PMOS transistor P1, and a drain connected to the first node S1. The first NMOS transistor N1 includes a gate receiving the internal clock signal Internal_CLK and a drain connected to the first node S1. The second NMOS transistor N2 includes a gate that receives an output signal of the first inverter IV1, a drain connected to a source of the first NMOS transistor N1, and a source connected to a ground voltage VSS terminal. .

In more detail, during the write operation, the write signal WTS is at a 'high' level. In this case, the output signal of the first inverter IV1 turns off the second NMOS transistor N2. In addition, the output signal of the second inverter IV2 turns off the first PMOS transistor P1. Therefore, during the write operation, the buffer clock signal DQ_CLK is disabled.

In a read operation, the write signal WTS is at a low level. In this case, the output signal of the first inverter IV1 turns on the second NMOS transistor N2. The output signal of the second inverter IV2 turns on the first PMOS transistor P1. Therefore, during the read operation, the buffer clock signal DQ_CLK is enabled.

In the read operation, the first NMOS transistor N1 and the second PMOS transistor P2 that receive an internal clock signal Internal_CLK after the first PMOS transistor P1 and the second NMOS transistor N2 are turned on. ) Generates the buffer clock signal DQ_CLK that toggles from the 'high' level to the 'low' level.

Therefore, when the write signal WTS is disabled during the read operation, the buffer clock signal DQ_CLK is enabled. Thereafter, the buffer clock signal DQ_CLK is driven by the driver 210 and output as a buffer driving signal DQ_CLKD.

In the write operation, when the write signal WTS is enabled, the buffer clock signal DQ_CLK and the buffer driving signal DQ_CLKD are disabled.

The data output control circuit of the semiconductor memory device according to the present invention implements the buffer driving signal controller 510 which can disable the buffer clock signal DQ_CLK in order to reduce unnecessary current consumption during a write operation. In the read operation, the buffer driving signal controller 510 enables the buffer clock signal DQ_CLK. The driver 200 drives the buffer clock signal DQ_CLK and outputs the buffer driving signal DQ_CLKD. In the write operation, the buffer driving signal controller 510 disables the buffer clock signal DQ_CLK. Therefore, the data output control circuit can reduce the current consumption by disabling the buffer driving signal DQ_CLKD which is not used during a write operation.

As such, those skilled in the art will appreciate that the present invention can be implemented in other specific forms without changing the technical spirit or essential features thereof. Therefore, the above-described embodiments are to be understood as illustrative in all respects and not as restrictive. The scope of the present invention is shown by the following claims rather than the detailed description, and all changes or modifications derived from the meaning and scope of the claims and their equivalents should be construed as being included in the scope of the present invention. do.

Data of the semiconductor memory device according to the present invention has an effect of increasing the reliability of the chip by controlling the operation in an unnecessary section.

Claims (6)

A buffer driving signal generator configured to generate a buffer driving signal from an external clock in response to the write signal; An output enable signal generator configured to generate an output enable signal from the buffer driving signal in response to a burst signal and a read signal; And And a data strobe buffer unit configured to generate a data strobe buffer output signal from the buffer driving signal or the data strobe signal in response to the write signal. The method of claim 1, The buffer driving signal generator, And disabling the buffer driving signal when the write signal is enabled, and enabling the buffer driving signal when the write signal is disabled. The method of claim 1, The buffer driving signal generator, A clock buffer unit which buffers the external clock to generate an internal clock; A buffer driving signal controller configured to receive the internal clock and generate a buffer clock signal in response to the write signal; And And a driving unit driving the buffer clock signal to generate the buffer driving signal. The method of claim 3, wherein The buffer drive signal control unit, And if the write signal is enabled, disable the buffer clock signal, and if the write signal is disabled, enable the buffer clock signal. The method of claim 1, The output enable signal generator, And outputting the output enable signal by using the buffer driving signal when the write signal is disabled. The method of claim 1, The data strobe buffer unit, The data strobe buffer output signal is output from the buffer driving signal when the write signal is disabled, and the data strobe buffer output signal is output from the data strobe signal when the write signal is enabled. Data output control circuit of the memory device.
KR1020070056960A 2007-06-11 2007-06-11 Data output controlling circuit of semiconductor memory apparatus KR20080108866A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1020070056960A KR20080108866A (en) 2007-06-11 2007-06-11 Data output controlling circuit of semiconductor memory apparatus

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1020070056960A KR20080108866A (en) 2007-06-11 2007-06-11 Data output controlling circuit of semiconductor memory apparatus

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KR20080108866A true KR20080108866A (en) 2008-12-16

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101047002B1 (en) * 2009-06-26 2011-07-06 주식회사 하이닉스반도체 Data Buffer Control Circuit and Semiconductor Memory Device

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101047002B1 (en) * 2009-06-26 2011-07-06 주식회사 하이닉스반도체 Data Buffer Control Circuit and Semiconductor Memory Device
US8248863B2 (en) 2009-06-26 2012-08-21 Hynix Semiconductor Inc. Data buffer control circuit and semiconductor memory apparatus including the same

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