KR20040053438A - Method of forming a floating gate in a flash memory device - Google Patents

Method of forming a floating gate in a flash memory device Download PDF

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KR20040053438A
KR20040053438A KR1020020079992A KR20020079992A KR20040053438A KR 20040053438 A KR20040053438 A KR 20040053438A KR 1020020079992 A KR1020020079992 A KR 1020020079992A KR 20020079992 A KR20020079992 A KR 20020079992A KR 20040053438 A KR20040053438 A KR 20040053438A
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South Korea
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layer
polysilicon
forming
cleaning process
floating gate
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KR1020020079992A
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Korean (ko)
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임태정
이승철
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주식회사 하이닉스반도체
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66825—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a floating gate
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42324—Gate electrodes for transistors with a floating gate

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Non-Volatile Memory (AREA)
  • Semiconductor Memories (AREA)

Abstract

PURPOSE: A method for forming a floating gate of a flash memory device is provided to completely remove a native oxide layer between the first and second polysilicon layer by carrying out an NF3 plasma treatment and a multi-step cleaning process. CONSTITUTION: A tunnel oxide layer(22) and the first polysilicon layer(23) are sequentially formed on a semiconductor substrate(21). The substrate is partially exposed by selectively etching the first polysilicon layer and the tunnel oxide layer. A trench is formed by etching the exposed substrate. An isolation layer(25) is formed in the trench. An NF3 plasma treatment and a three-step cleaning process are carried out on the resultant structure for removing a native oxide layer. The native oxide layer exists on the first polysilicon layer. The second polysilicon layer(26) is formed on the resultant structure. A floating gate is formed by selectively patterning the first and second polysilicon layer.

Description

플래쉬 메모리 소자의 플로팅 게이트 형성 방법{Method of forming a floating gate in a flash memory device}Method of forming a floating gate in a flash memory device

본 발명은 플래쉬 메모리 소자의 플로팅 게이트 형성 방법에 관한 것으로, 특히 소자 분리막을 형성한 후 NF3플라즈마 처리와 다단계 클리닝 공정으로 제 1 폴리실리콘막과 제 2 폴리실리콘막의 계면에 성장되는 자연 산화막을 제거함으로써 소자의 전기적 특성을 향상시킬 수 있는 플래쉬 메모리 소자의 플로팅 게이트 형성 방법에 관한 것이다.The present invention relates to a method of forming a floating gate of a flash memory device, and in particular, to remove a natural oxide film grown at an interface between a first polysilicon film and a second polysilicon film by an NF 3 plasma treatment and a multi-step cleaning process after forming a device isolation film. Therefore, the present invention relates to a method of forming a floating gate of a flash memory device capable of improving electrical characteristics of the device.

현재 개발중인 0.1㎛ 데이터 플래쉬 메모리 소자는 터널 산화막 및 제 1 폴리실리콘막을 적층한 후 이들 및 반도체 기판을 식각하여 소자 분리막을 형성하는 이른바 SA-STI(Self Aligned Shallow Trench Isolation) 구조를 이용하고, 제 1 폴리실리콘막과 제 2 폴리실리콘막을 적층하여 플로팅 게이트를 형성한다. 제 1 및 제 2 폴리실리콘막의 이중 폴리실리콘막으로 구성된 플로팅 게이트는 프로그램, 소거 등의 메커니즘에 의해 전자들이 이동되는 중요한 역할을 한다. 그러나, 제 1 및 제 2 폴리실리콘막은 익스시투 공정으로 형성되기 때문에 제 1 폴리실리콘막과 제 2 폴리실리콘막의 계면에 자연 산화막이 성장된다.The 0.1 μm data flash memory device currently being developed uses a so-called Self Aligned Shallow Trench Isolation (SA-STI) structure in which a tunnel oxide film and a first polysilicon film are stacked, and then the semiconductor substrate is etched to form an isolation layer. A floating gate is formed by laminating the first polysilicon film and the second polysilicon film. The floating gate composed of the double polysilicon film of the first and second polysilicon films plays an important role in which electrons are moved by a mechanism such as program and erase. However, since the first and second polysilicon films are formed by an excitu process, a native oxide film is grown at the interface between the first polysilicon film and the second polysilicon film.

그럼, 0.1㎛ 데이터 플래쉬 메모리 소자의 플로팅 게이트 형성 방법을 도 1(a) 내지 도 1(c)를 이용하여 설명하면 다음과 같다.A method of forming a floating gate of a 0.1 μm data flash memory device will now be described with reference to FIGS. 1A to 1C.

도 1(a)를 참조하면, 반도체 기판(11) 상부에 터널 산화막(12) 및 제 1 폴리실리콘막(13)을 형성한 후 그 상부에 질화막(14)을 형성한다. 소자 분리 마스크를이용한 리소그라피 공정 및 식각 공정으로 질화막(14)을 패터닝한다. 패터닝된 질화막(14)을 마스크로 제 1 폴리실리콘막(13) 및 터널 산화막(12)을 식각한 후 노출된 반도체 기판(11)을 소정 깊이로 식각하여 트렌치를 형성한다. 트렌치가 매립되도록 전체 구조 상부에 산화막(15)을 형성한다.Referring to FIG. 1A, a tunnel oxide film 12 and a first polysilicon film 13 are formed on a semiconductor substrate 11, and a nitride film 14 is formed on the tunnel oxide film 12. The nitride film 14 is patterned by a lithography process and an etching process using an element isolation mask. After the first polysilicon layer 13 and the tunnel oxide layer 12 are etched using the patterned nitride layer 14 as a mask, the exposed semiconductor substrate 11 is etched to a predetermined depth to form a trench. An oxide film 15 is formed over the entire structure to fill the trench.

도 1(b)를 참조하면, 산화막(15)을 연마한 후 제 1 폴리실리콘막(13) 상부의 질화막(14)을 식각하여 소자 분리막을 형성한다.Referring to FIG. 1B, after the oxide layer 15 is polished, the nitride layer 14 on the first polysilicon layer 13 is etched to form an isolation layer.

도 1(c)를 참조하면, 전체 구조 상부에 제 2 폴리실리콘막(16)을 형성한 후 제 2 폴리실리콘막(16) 및 제 1 폴리실리콘막(13)을 패터닝하여 플로팅 게이트를 형성한다. 그런데, 제 1 폴리실리콘막(13)과 제 2 폴리실리콘막(16)은 연속 공정으로 형성되는 것이 아니기 때문에 이들 사이의 계면에 자연 산화막(17)이 존재하게 된다.Referring to FIG. 1C, after forming the second polysilicon layer 16 on the entire structure, the second polysilicon layer 16 and the first polysilicon layer 13 are patterned to form a floating gate. . However, since the first polysilicon film 13 and the second polysilicon film 16 are not formed in a continuous process, the natural oxide film 17 is present at the interface between them.

상기한 바와 같은 공정으로 데이터 플래쉬 메모리 소자의 플로팅 게이트를 형성할 경우 제 1 폴리실리콘막과 제 2 폴리실리콘막의 계면에 수십Å 정도의 자연 산화막이 존재하게 된다. 이에 의해 소자 동작시 전자들이 자연 산화막에 트랩되는 문제가 발생하게 되어 셀의 문턱 전압이 떨어지는 비트 페일(bit fail)가 발생하게 되고, 자연 산화막이 기생 캐패시터로 작용하게 되어 초기 인가된 전압이 떨어지는 현상이 발생되는등 소자의 전기적 특성에 악영향을 미치게 된다.When the floating gate of the data flash memory device is formed by the above-described process, there are about tens of nanometers of natural oxide film at the interface between the first and second polysilicon films. As a result, a problem occurs in that electrons are trapped in the natural oxide layer during operation of the device, thereby causing a bit fail in which the threshold voltage of the cell decreases. This will adversely affect the electrical characteristics of the device.

본 발명의 목적은 제 1 폴리실리콘막과 제 2 폴리실리콘막의 계면에 존재하는 자연 산화막을 완전히 제거하여 소자의 전기적 특성을 향상시킬 수 있는 플래쉬 메모리 소자의 플로팅 게이트 형성 방법을 제공하는데 있다.SUMMARY OF THE INVENTION An object of the present invention is to provide a method of forming a floating gate of a flash memory device capable of improving the electrical characteristics of a device by completely removing a native oxide film present at an interface between a first polysilicon film and a second polysilicon film.

본 발명의 다른 목적은 NF3플라즈마 처리와 다단계 클리닝 공정으로 제 1 폴리실리콘막 상부에 성장되는 자연 산화막을 제거함으로써 소자의 전기적 특성을 향상시킬 수 있는 플래쉬 메모리 소자의 플로팅 게이트 형성 방법을 제공하는데 있다.Another object of the present invention is to provide a method of forming a floating gate of a flash memory device capable of improving the electrical characteristics of the device by removing a native oxide film grown on the first polysilicon film by NF 3 plasma treatment and a multi-step cleaning process. .

도 1(a) 내지 도 1(c)는 종래의 플래쉬 메모리 소자의 플로팅 게이트 형성 방법을 설명하기 위해 순서적으로 도시한 소자의 단면도.1 (a) to 1 (c) are cross-sectional views of devices sequentially shown to explain a method of forming a floating gate of a conventional flash memory device.

도 2(a) 내지 도 2(d)는 본 발명에 따른 플래쉬 메모리 소자의 플로팅 게이트 형성 방법을 설명하기 위해 순서적으로 도시한 소자의 단면도.2 (a) to 2 (d) are cross-sectional views of devices sequentially shown for explaining a method of forming a floating gate of a flash memory device according to the present invention.

<도면의 주요 부분에 대한 부호의 설명><Explanation of symbols for the main parts of the drawings>

11 및 21 : 반도체 기판 12 및 22 : 터널 산화막11 and 21: semiconductor substrate 12 and 22: tunnel oxide film

13 및 23 : 제 1 폴리실리콘막 14 및 24 : 질화막13 and 23: first polysilicon film 14 and 24: nitride film

15 및 25 : 산화막 26 및 26 : 제 2 폴리실리콘막15 and 25: oxide film 26 and 26: second polysilicon film

17 : 자연 산화막17: natural oxide film

본 발명에 따른 플래쉬 메모리 소자의 플로팅 게이트 형성 방법은 반도체 기판 상부에 터널 산화막 및 제 1 폴리실리콘막을 형성하는 단계와, 상기 제 1 폴리실리콘막 및 상기 터널 산화막의 소정 영역을 식각한 후 노출된 상기 반도체 기판을 소정 깊이로 식각하여 트렌치를 형성하는 단계와, 상기 트렌치가 매립되도록 전체 구조 상부에 산화막을 형성한 후 상기 산화막을 연마하여 소자 분리막을 형성하는 단계와, NF3플라즈마 처리를 실시한 후 클리닝 공정을 실시하여 상기 제 1 폴리실리콘막 상부에 성장되는 자연 산화막을 제거하는 단계와, 전체 구조 상부에 제 2 폴리실리콘막을 형성한 후 상기 제 2 및 제 1 폴리실리콘막을 패터닝하여 플로팅 게이트를 형성하는 단계를 포함하여 이루어진 것을 특징으로 한다.According to another aspect of the present invention, there is provided a method of forming a floating gate of a flash memory device, the method comprising: forming a tunnel oxide layer and a first polysilicon layer on a semiconductor substrate, and etching the predetermined region of the first polysilicon layer and the tunnel oxide layer and then exposing the tunnel oxide layer and the first polysilicon layer; Etching the semiconductor substrate to a predetermined depth to form a trench; forming an oxide film over the entire structure to fill the trench; polishing the oxide film to form an isolation layer; and performing NF 3 plasma treatment. Performing a process to remove the native oxide film grown on the first polysilicon film, forming a second polysilicon film on the entire structure, and then patterning the second and first polysilicon films to form a floating gate. Characterized in that it comprises a step.

여기서, 상기 클리닝 공정은 H2SO4및 H2O2의 혼합 용액을 이용하여 1차 클리닝 공정을 실시하고 NH4OH, H2O2및 H2O의 혼합 용액을 이용하여 2차 클리닝 공정을 실시한 후 BOE 용액을 이용하여 3차 클리닝 공정을 실시하는 것을 특징으로 한다.Here, the cleaning process is a first cleaning process using a mixed solution of H 2 SO 4 and H 2 O 2 and a second cleaning process using a mixed solution of NH 4 OH, H 2 O 2 and H 2 O After performing the third cleaning process using a BOE solution is characterized in that.

이하, 첨부된 도면을 참조하여 본 발명의 바람직한 실시 예를 설명함으로써 본 발명을 상세히 설명한다. 그러나, 본 발명은 이하에서 개시되는 실시 예에 한정되는 것이 아니라 서로 다른 다양한 형태로 구현될 것이며, 단지 본 실시 예는 본 발명의 개시가 완전하도록 하며, 이 기술 분야에서 통상의 지식을 가진자에게 발명의 범주를 완전하게 알려주기 위해 제공되는 것이다. 또한, 도면상에서 동일 부호는 동일 요소를 지칭한다.Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. However, the present invention is not limited to the embodiments disclosed below, but may be implemented in various forms, and only the present embodiments are intended to complete the present disclosure and to those skilled in the art. It is provided to fully inform the scope of the invention. In addition, in the drawings, like reference numerals refer to like elements.

도 2(a) 내지 도 2(d)는 본 발명에 따른 플래쉬 메모리 소자의 플로팅 게이트 형성 방법을 설명하기 위해 순서적으로 도시한 소자의 단면도이다.2 (a) to 2 (d) are cross-sectional views of devices sequentially shown to explain a method of forming a floating gate of a flash memory device according to the present invention.

도 2(a)를 참조하면, 반도체 기판(21) 상부에 터널 산화막(22) 및 제 1 폴리실리콘막(23)을 형성한 후 그 상부에 질화막(24)을 형성한다. 소자 분리 마스크를 이용한 리소그라피 공정 및 식각 공정으로 질화막(24)을 패터닝한다. 패터닝된 질화막(24)을 마스크로 제 1 폴리실리콘막(23) 및 터널 산화막(22)을 식각한 후 노출된 반도체 기판(21)을 소정 깊이로 식각하여 트렌치를 형성한다. 트렌치가 매립되도록 전체 구조 상부에 산화막(25)을 형성한다.Referring to FIG. 2A, a tunnel oxide film 22 and a first polysilicon film 23 are formed on a semiconductor substrate 21, and a nitride film 24 is formed thereon. The nitride film 24 is patterned by a lithography process and an etching process using an element isolation mask. After etching the first polysilicon layer 23 and the tunnel oxide layer 22 using the patterned nitride layer 24 as a mask, the exposed semiconductor substrate 21 is etched to a predetermined depth to form a trench. An oxide film 25 is formed on the entire structure to fill the trench.

도 2(b)를 참조하면, 산화막(25)을 연마한 후 제 1 폴리실리콘막(23) 상부의 질화막(24)을 식각하여 소자 분리막을 형성한다.Referring to FIG. 2B, after the oxide layer 25 is polished, the nitride layer 24 on the first polysilicon layer 23 is etched to form an isolation layer.

도 2(c)를 참조하면, NF3플라즈마 처리를 실시한 후 3단계 클리닝 공정을 실시하여 제 1 폴리실리콘막(23) 상부에 형성되는 자연 산화막을 제거한다. 3단클리닝 공정은 H2SO4및 H2O2의 혼합 용액을 이용하여 1차 클리닝 공정을 실시하고 NH4OH, H2O2및 H2O의 혼합 용액을 이용하여 2차 클리닝 공정을 실시한 후 BOE 용액을 이용하여 3차 클리닝 공정을 실시한다.Referring to FIG. 2 (c), after the NF 3 plasma treatment, a three-stage cleaning process is performed to remove the natural oxide layer formed on the first polysilicon layer 23. In the three-stage cleaning process, the first cleaning process is performed using a mixed solution of H 2 SO 4 and H 2 O 2 , and the second cleaning process is performed using a mixed solution of NH 4 OH, H 2 O 2, and H 2 O. After the 3rd cleaning process is performed using BOE solution.

도 2(d)를 참조하면, 전체 구조 상부에 제 2 폴리실리콘막(26)을 형성한 후 제 2 폴리실리콘막(26) 및 제 1 폴리실리콘막(23)을 패터닝하여 플로팅 게이트를 형성한다.Referring to FIG. 2 (d), after forming the second polysilicon layer 26 on the entire structure, the second polysilicon layer 26 and the first polysilicon layer 23 are patterned to form a floating gate. .

상술한 바와 같이 본 발명에 의하면 소자 분리막을 형성한 후 NF3플라즈마 처리와 다단계 클리닝 공정으로 제 1 폴리실리콘막과 제 2 폴리실리콘막 계면에 성장되는 자연 산화막을 제거함으로써 소자의 전기적 특성을 향상시킬 수 있다.As described above, according to the present invention, after the device isolation layer is formed, the electrical characteristics of the device may be improved by removing the natural oxide film grown at the interface between the first polysilicon film and the second polysilicon film by NF 3 plasma treatment and a multi-step cleaning process. Can be.

Claims (3)

반도체 기판 상부에 터널 산화막 및 제 1 폴리실리콘막을 형성하는 단계;Forming a tunnel oxide film and a first polysilicon film on the semiconductor substrate; 상기 제 1 폴리실리콘막 및 상기 터널 산화막의 소정 영역을 식각한 후 노출된 상기 반도체 기판을 소정 깊이로 식각하여 트렌치를 형성하는 단계;Etching a predetermined region of the first polysilicon layer and the tunnel oxide layer and then etching the exposed semiconductor substrate to a predetermined depth to form a trench; 상기 트렌치가 매립되도록 전체 구조 상부에 산화막을 형성한 후 상기 산화막을 연마하여 소자 분리막을 형성하는 단계;Forming an isolation layer on the entire structure to fill the trench, and then polishing the oxide to form an isolation layer; NF3플라즈마 처리를 실시한 후 클리닝 공정을 실시하여 상기 제 1 폴리실리콘막 상부에 성장되는 자연 산화막을 제거하는 단계; 및Performing a cleaning process after performing NF 3 plasma treatment to remove the native oxide film grown on the first polysilicon film; And 전체 구조 상부에 제 2 폴리실리콘막을 형성한 후 상기 제 2 및 제 1 폴리실리콘막을 패터닝하여 플로팅 게이트를 형성하는 단계를 포함하여 이루어진 것을 특징으로 하는 플래쉬 메모리 소자의 플로팅 게이트 형성 방법.And forming a floating gate by patterning the second and first polysilicon layers after forming a second polysilicon layer over the entire structure. 제 1 항에 있어서, 상기 클리닝 공정은 다단계로 실시하는 것을 특징으로 하는 플래쉬 메모리 소자의 플로팅 게이트 형성 방법.The method of claim 1, wherein the cleaning process is performed in a multi-step process. 제 1 항 또는 제 2 항에 있어서, 상기 클리닝 공정은 H2SO4및 H2O2의 혼합용액을 이용하여 1차 클리닝 공정을 실시하고 NH4OH, H2O2및 H2O의 혼합 용액을 이용하여 2차 클리닝 공정을 실시한 후 BOE 용액을 이용하여 3차 클리닝 공정을 실시하는 것을 특징으로 하는 플래쉬 메모리 소자의 플로팅 게이트 형성 방법.The method of claim 1 or 2, wherein the cleaning process is a first cleaning process using a mixed solution of H 2 SO 4 and H 2 O 2 and the mixture of NH 4 OH, H 2 O 2 and H 2 O And performing a third cleaning process using a BOE solution after performing a second cleaning process using a solution.
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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN107507761A (en) * 2017-08-31 2017-12-22 长江存储科技有限责任公司 A kind of polysilicon deposition method and polysilicon deposition equipment

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN107507761A (en) * 2017-08-31 2017-12-22 长江存储科技有限责任公司 A kind of polysilicon deposition method and polysilicon deposition equipment

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