KR102717096B1 - Integrated circuit and computer-implemented method for manufacturing the same - Google Patents

Abstract

A computer-implemented method of manufacturing an integrated circuit according to the technical idea of the present disclosure comprises: arranging standard cells defining an integrated circuit; pre-routing at least one net of a timing critical path among timing paths in the arranged standard cells to an airgap layer; routing nets of non-critical paths among the timing paths; and manufacturing the integrated circuit based on a layout generated according to the pre-routing and routing.

Description

Integrated circuit and computer-implemented method for manufacturing the same

The technical idea of the present disclosure relates to an integrated circuit, and more particularly, to an integrated circuit including an air-gap layer and a computer-implemented method for manufacturing the integrated circuit.

As semiconductor process technology advances, process miniaturization is accelerated, and accordingly, the gap between conductive patterns is reduced, which may increase parasitic capacitance. In order to reduce this parasitic capacitance, air gap technology that places air gap patterns between conductive patterns is being actively studied. Since air has a small dielectric constant, parasitic capacitance can be reduced by the air gap pattern, and thus, the operating speed of the semiconductor chip can be improved.

The technical idea of the present disclosure provides an integrated circuit capable of improving the operating speed of a chip at low cost and a computer-implemented method for manufacturing the integrated circuit.

A computer-implemented method of manufacturing an integrated circuit, performed at least in part by a processor, according to the technical idea of the present disclosure, comprises the steps of: placing standard cells defining the integrated circuit; pre-routing at least one net of a timing critical path among timing paths within the placed standard cells to an airgap layer; routing nets of non-critical paths among the timing paths; and manufacturing the integrated circuit based on the pre-routing and the layout generated according to the routing.

In addition, an integrated circuit according to the technical idea of the present disclosure includes a first air gap layer having a first conductive pattern, and a first air gap pattern adjacent to the first conductive pattern and extending in a first direction, a first via disposed on the first conductive pattern and electrically connected to the first conductive pattern, a second conductive pattern electrically connected to the first via, and a second air gap layer having a second air gap pattern adjacent to the second conductive pattern and extending in a second direction substantially perpendicular to the first direction.

According to the technical idea of the present disclosure, by pre-routing at least one selected net of timing-critical paths among timing paths in arranged standard cells to an air gap layer and routing nets of non-critical paths among timing paths, a high-performance integrated circuit can be implemented at low cost. Accordingly, the parasitic capacitance between conductive patterns constituting the selected net is reduced, so that the overall timing delay of the timing-critical path can be reduced. Accordingly, the timing-critical path can satisfy timing constraints, and the operating speed of the integrated circuit and a chip including the same can be greatly improved.

FIG. 1 is a flowchart illustrating a method for manufacturing an integrated circuit according to one embodiment of the present disclosure.
FIG. 2 is a cross-sectional view illustrating an integrated circuit including an airgap layer according to one embodiment of the present disclosure.
FIGS. 3 and 4 illustrate integrated circuit design systems according to some embodiments of the present disclosure.
FIG. 5 is a flowchart illustrating a design method of an integrated circuit according to one embodiment of the present disclosure.
FIG. 6 is a flowchart illustrating a design method of an integrated circuit according to one embodiment of the present disclosure.
FIG. 7 is a graph showing the results of timing analysis according to one embodiment of the present disclosure.
FIG. 8 illustrates a wiring structure routed using an air gap layer according to one embodiment of the present disclosure.
FIGS. 9A to 9C are perspective views each showing timing critical path nets routed to an airgap layer according to one embodiment of the present disclosure.
FIG. 10 illustrates a routing structure using a general layer according to one embodiment of the present disclosure.
FIG. 11a is a plan view showing an integrated circuit routed by applying an air gap pattern according to one embodiment of the present disclosure, and FIG. 11b is a perspective view showing the integrated circuit of FIG. 11a.
FIG. 12a is a plan view showing an integrated circuit routed by applying an air gap pattern according to one embodiment of the present disclosure, and FIG. 12b is a perspective view showing the integrated circuit of FIG. 12a.
FIG. 13a is a plan view showing an integrated circuit routed by applying an air gap pattern according to one embodiment of the present disclosure, and FIG. 13b is a perspective view showing the integrated circuit of FIG. 13a.
FIG. 14a is a plan view showing an integrated circuit routed by applying an air gap pattern according to one embodiment of the present disclosure, FIG. 14b is a perspective view showing the integrated circuit of FIG. 14a, and FIG. 14c shows an integrated circuit according to a comparative example for FIG. 14a.
FIG. 15a is a plan view showing an integrated circuit routed by applying an air gap pattern according to one embodiment of the present disclosure, and FIG. 15b is a perspective view showing the integrated circuit of FIG. 15a.
FIG. 16 is a layout of a standard cell included in an integrated circuit according to one embodiment of the present disclosure.
FIG. 17 is a block diagram illustrating a storage medium according to one embodiment of the present disclosure.

Hereinafter, embodiments of the present disclosure will be described in detail with reference to the attached drawings. The same reference numerals are used for the same components in the drawings, and redundant descriptions thereof are omitted.

FIG. 1 is a flowchart illustrating a method for manufacturing an integrated circuit according to one embodiment of the present disclosure.

Referring to FIG. 1, a method for manufacturing an integrated circuit according to the present embodiment can be divided into a design of an integrated circuit (S10) and a manufacturing process of an integrated circuit (S20). The design of the integrated circuit (S10) includes steps S110 to S130 and is a step of designing a layout for an integrated circuit, which can be performed using a tool for designing an integrated circuit. At this time, the tool for designing the integrated circuit can be a program including a plurality of instructions executed by a processor. Accordingly, the design of the integrated circuit (S10) can be referred to as a computer implemented method for designing an integrated circuit. Meanwhile, the manufacturing process of the integrated circuit (S20) is a step of manufacturing a semiconductor device according to the integrated circuit based on the designed layout, which can be performed in a semiconductor process module.

An integrated circuit may be defined as a plurality of cells, and specifically, may be designed using a cell library including characteristic information of a plurality of cells. The cell library may define a name, a dimension, a gate width, a pin, a delay characteristic, a leakage current, a threshold voltage, a function, and the like of a cell. In embodiments of the present disclosure, the cell library may be a standard cell library. The standard cell library may include information such as layout information and timing information of a plurality of standard cells, and may be stored in a computer-readable storage medium.

In step S110, standard cells defining an integrated circuit are placed. For example, step S110 may be performed by a processor using a placement and routing (hereinafter, 'P&R') tool. First, input data defining an integrated circuit is received. Here, the input data may be data generated by synthesis using a standard cell library from data defined in an abstract form for a behavior of the integrated circuit, for example, in an RTL (Register Transfer Level). For example, the input data may be a bitstream or netlist generated by synthesizing an integrated circuit defined as an HDL (Hardware Description Language) such as VHDL (VHSIC Hardware Description Language) and Verilog. Next, a storage medium storing the standard cell library is accessed, and standard cells selected from among a plurality of standard cells stored in the standard cell library according to the input data are placed.

In step S120, pre-routing is performed on selected nets from the placed standard cells to an air-gap layer. In step S130, unselected nets are routed from the placed standard cells. In this specification, the air-gap layer refers to a layer including an air-gap or an air-gap pattern. Specifically, at least one net among a plurality of nets included in the placed standard cells may be selected, and the selected at least one net may be assigned to the air-gap layer. In the present embodiment, at least one net may correspond to one net of a timing critical path.

In this specification, a net represents an equipotential in an equivalent circuit diagram of an integrated circuit. One net may correspond to one interconnection in the layout of the integrated circuit, and one interconnection may correspond to a wiring structure including a plurality of wiring layers and vias that are electrically connected to each other. Each wiring layer may include a plurality of conductive patterns, and the conductive patterns formed in the wiring layers at different levels may be electrically connected to each other through vias made of a conductive material. The wiring layer may be described as including a metal as the conductive material, and may be referred to as a metal layer. However, in some embodiments of the present disclosure, the wiring layers may include a conductive material other than a metal.

In one embodiment, the net may include a first conductive pattern included in a first wiring layer, a second conductive pattern included in a second wiring layer, and a via electrically connected between the first conductive pattern and the second conductive pattern, wherein the first wiring layer and the second wiring layer may be arranged at different levels. However, the present invention is not limited thereto, and in some embodiments, the net may include conductive patterns included in the same wiring layer. Furthermore, in some embodiments, the net may include a plurality of first conductive patterns included in the first wiring layer and a plurality of second conductive patterns included in the second wiring layer.

According to the present embodiment, by arranging an air gap pattern adjacent to a challenge pattern constituting a selected net, the selected net can be pre-routed to an air gap layer. In the present embodiment, the air gap layer can be implemented as a bi-directional air gap layer. Specifically, the air gap pattern included in the air gap layer can extend in a first direction or in a second direction substantially perpendicular to the first direction. Hereinafter, the air gap layer will be described in detail with reference to FIG. 2.

FIG. 2 is a cross-sectional view illustrating an integrated circuit (IC) including an airgap layer according to one embodiment of the present disclosure.

Referring to FIG. 2, the integrated circuit (IC) may include first to third wiring layers (M1, M2, M3), first and second insulating layers (ILD1, ILD2), and first and second barrier layers (BM1, BM2). For example, the integrated circuit (IC) may be designed according to step S10 of FIG. 1, and manufactured according to step S20.

A first wiring layer (M1) extends in the X direction, a first barrier layer (BM1) may include a plurality of barrier layers disposed on the first wiring layer (M1), and a first insulating layer (ILD1) may be disposed on the first barrier layer (BM1). A second wiring layer (M2) is disposed on the first insulating layer (ILD1) and extends in the Y direction, a second barrier layer (BM2) may include a plurality of barrier layers disposed on the second wiring layer (M2), and a second insulating layer (ILD2) may be disposed on the second barrier layer (BM2). The first and second insulating layers (ILD1, ILD2) may be referred to as an interlayer dielectric. A third wiring layer (M3) is disposed on the second insulating layer (ILD2) and extends in the X direction.

In one embodiment, the second wiring layer (M2) may be allocated as an air gap layer (AGL) including an air gap pattern (AGP), and the first and third wiring layers (M1, M3) may be allocated as general layers not including the air gap pattern (AGP). In one embodiment, the second wiring layer (M2) may be free-routed to the air gap layer (AGL), and the first and third wiring layers (M1, M3) may be routed as general layers. In this way, the first to third wiring layers (M1, M2, M3) may be routed using a two-step wiring technique.

According to the present embodiment, the second wiring layer (M2) may include conductive patterns (CPT) extending in the Y direction and air gap patterns (AGP) between the conductive patterns (CPT). At this time, the air gap pattern (AGP) may be generated by replacing the IMD (Inter Metal Dielectric) material between the conductive patterns (CPT) with air. Since air has a low dielectric constant of 1, the air gap pattern (AGP) may reduce the parasitic capacitance between the conductive patterns (CPT), thereby improving the operating speed of a chip including an integrated circuit (IC). However, since process costs such as mask costs increase in order to generate the air gap pattern (AGP), if all of the first to third wiring layers (M1, M2, M3) included in the integrated circuit (IC) are implemented as air gap layers, the manufacturing cost of the chip significantly increases.

According to the present embodiment, instead of implementing all layers included in an integrated circuit (IC), that is, the first to third wiring layers (M1, M2, M3), as air gap layers, only some layers corresponding to a net of a timing critical path, for example, the second wiring layer (M2), can be implemented as air gap layers. Accordingly, the performance improvement of the integrated circuit (IC) can be maximized at low cost, and specifically, the operating speed of a chip in which the integrated circuit (IC) is implemented can be improved to the same level as that of an integrated circuit in which all layers are implemented as air gap layers.

Referring back to FIG. 1, after step S130, output data defining an integrated circuit may be provided to a semiconductor process module. Here, the output data may have a format including all layout information of standard cells, that is, pattern information in all layers, for example, a GDS (Graphic Design System) II format. Alternatively, the output data may have a format including external information of a standard cell, such as a pin of the standard cell, for example, a LEF format or a Milkyway format.

As described above, according to the present embodiment, routing can be performed by applying a two-step routing technique to the placed standard cells. In other words, routing for the placed standard cells can include a first routing step such as S120 and a second routing step such as S130. Specifically, at least one net of timing critical paths among timing paths in the placed standard cells can be assigned to an air gap layer, and the remaining nets can be assigned to general layers. Therefore, a high-performance integrated circuit can be manufactured using a small number of air gap layers.

The design of the integrated circuit (S10) may include the steps S110 to S130 described above. However, the present invention is not limited thereto, and may further include various steps according to a general integrated circuit design method, such as generation of a standard cell library, modification of the standard cell library, verification of a layout, etc. In addition, steps S110 to S130 may correspond to a back-end design process in a design process of the integrated circuit, and a front-end design process may be performed before step S110. The front-end design process may include determination of design specifications, behavioral level modeling and verification, RTL design, functional verification, logic synthesis, gate-level verification (or pre-layout simulation), etc.

In step S140, a mask is generated based on the layout. Specifically, OPC (Optical Proximity Correction) can be performed based on the layout first, and OPC refers to a process of changing the layout by reflecting an error due to the optical proximity effect. Then, a mask can be manufactured according to the changed layout based on the OPC performance result. At this time, the mask can be manufactured using a layout reflecting OPC, for example, GDS reflecting OPC.

In step S150, an integrated circuit is manufactured using a mask. Specifically, various semiconductor processes are performed on a semiconductor substrate such as a wafer using the mask to form a semiconductor device in which an integrated circuit is implemented. For example, the process using the mask may mean a patterning process through a lithography process. Through this patterning process, a desired pattern can be formed on a semiconductor substrate or a material layer. Meanwhile, the semiconductor process may include a deposition process, an etching process, an ion process, a cleaning process, etc. In addition, the semiconductor process may include a packaging process for mounting a semiconductor element on a PCB and sealing it with a sealant, or may include a test process for testing the semiconductor element or the package.

FIG. 3 illustrates an integrated circuit design system (10) according to one embodiment of the present disclosure.

Referring to FIG. 3, the integrated circuit design system (10) may include a processor (11), a working memory (13), an input/output device (15), a storage device (17), and a bus (19). The integrated circuit design system (10) may perform the integrated circuit design step (S10) of FIG. 1. In the present embodiment, the integrated circuit design system (10) may be implemented as an integrated device, and thus, may be referred to as an integrated circuit design device. The integrated circuit design system (10) may be provided as a dedicated device for designing an integrated circuit of a semiconductor device, but may also be a computer for driving various simulation tools or design tools.

The processor (11) may be configured to execute instructions for performing at least one of various operations for designing an integrated circuit. The processor (11) may communicate with a working memory (13), an input/output device (15), and a storage device (17) via a bus (19). The processor (11) may execute a design operation of an integrated circuit by driving a P&R module (13a) and a timing analysis module (13b) loaded into the working memory (13).

The working memory (13) can store the P&R module (13a) and the timing analysis module (13b). The P&R module (13a) and the timing analysis module (13b) can be loaded from the storage device (17) to the working memory (13). The working memory (130) can be a volatile memory such as SRAM (Static Random Access Memory) or DRAM (Dynamic Random Access Memory), or a nonvolatile memory such as PRAM, MRAM, ReRAM, FRAM, NOR flash memory, etc.

The P&R module (13a) may be a program including a plurality of commands for performing, for example, a placement operation according to step S110 of FIG. 1 and a wiring operation according to steps S120 and S130. The timing analysis module (13b) may perform timing analysis on all timing paths within the placed standard cells to determine whether timing constraints are satisfied. For example, the timing analysis module (13b) may be a Static Timing Analysis (STA) tool.

The input/output device (15) can control user input and output from user interface devices. For example, the input/output device (15) can be equipped with input devices such as a keyboard, mouse, touchpad, etc., and can receive input data defining an integrated circuit. For example, the input/output device (15) can be equipped with output devices such as a display, speaker, etc., and can display layout results, wiring results, or timing analysis results.

The storage device (17) can store various data related to the P&R module (13a) and the timing analysis module (13b). The storage device (17) can include a memory card (MMC, eMMC, SD, MicroSD, etc.), a solid state drive, a hard disk drive, etc.

FIG. 4 illustrates an integrated circuit design system (20) according to one embodiment of the present disclosure.

Referring to FIG. 4, the integrated circuit design system (20) may include a user device (21), an integrated circuit design platform (22), and a storage device (23). The integrated circuit design system (20) may perform the integrated circuit design step (S10) of FIG. 1. In the present embodiment, at least one of the user device (21), the integrated circuit design platform (22), and the storage device (23) may be a separate device, and the user device (21), the integrated circuit design platform (22), and the storage device (23) may be connected via wired or wireless communication or a network. In one embodiment, at least one of the user device (21), the integrated circuit design platform (22), and the storage device (23) may be positioned spaced apart from each other.

The user device (21) may include a processor (21a) and a user interface (UI) (21b). According to a user input input through the user interface (21a), the processor (21a) may drive an integrated circuit design platform (22). The integrated circuit design platform (22) is a set of computer-readable instructions for designing an integrated circuit and may include a P&R module (22a) and a timing analysis module (22b). The storage device (23) may include a cell library database (hereinafter, 'DB') (23a) and a layout DB (23b). The cell library DB (23a) may store information on cells required to generate a layout of an integrated circuit, and the layout DB (23b) may store information on a layout generated by the P&R module (22a), specifically, physical information on the layout.

FIG. 5 is a flowchart illustrating a design method (S10A) of an integrated circuit according to one embodiment of the present disclosure.

Referring to FIG. 5, the integrated circuit design method (S10A) according to the present embodiment may correspond to an implementation example of the integrated circuit design method (S10) of FIG. 1. The integrated circuit design method (S10A) according to the present embodiment may be performed, for example, by a processor (11) in the integrated circuit design system (10) of FIG. 3 or by a processor (21a) in the integrated circuit design system (20) of FIG. 4. Accordingly, the contents described above with reference to FIGS. 1 to 4 may also be applied to the present embodiment.

In step S210, a floor plan is performed. Here, the floor plan is a placement planning step, and refers to a task of roughly planning how to place/wire standard cells and macro cells. Specifically, the floor plan is a step of placing I/O pads, standard cells, RAMs, etc. in the entire chip.

In step S220, standard cells defining an integrated circuit are placed. Afterwards, post-placement optimization may be performed. In step S230, clock tree synthesis is performed. Here, clock tree synthesis refers to a task of automatically configuring a clock network and inserting a buffer at an appropriate location when generating a circuit layout. By placing standard cells and performing clock tree synthesis by steps S220 and S230, it can be considered that the placement of the standard cells is completed.

In step S240, air gap layers are selected. In one embodiment, a timing critical path may be selected from among a plurality of timing paths included in the placed standard cells, and the timing critical path may be assigned to an air gap layer. In step S250, nets on the timing critical path (hereinafter, 'timing critical path nets') are selected. In one embodiment, nets included in a portion of a range of the timing critical path may be selected as timing critical path nets.

In step S260, timing critical path nets are pre-routed with high priority given to air gap layers. In step S270, non-critical path nets among timing paths in the placed standard cells are routed. In this way, according to the present embodiment, the integrated circuit design method (S10A) can implement a high-performance integrated circuit using a small number of air gap layers by applying a two-step wiring technique.

FIG. 6 is a flowchart illustrating a design method (S10B) of an integrated circuit according to one embodiment of the present disclosure.

Referring to FIG. 6, the integrated circuit design method (S10B) according to the present embodiment may correspond to an implementation example of the integrated circuit design method (S10A) of FIG. 5. The integrated circuit design method (S10B) according to the present embodiment may be performed, for example, by a processor (11) in the integrated circuit design system (10) of FIG. 3 or by a processor (21a) in the integrated circuit design system (20) of FIG. 4. Accordingly, the contents described above with reference to FIGS. 1 to 4 may also be applied to the present embodiment.

In step S310, a plurality of standard cells defining an integrated circuit are placed. Specifically, step S310 may be performed using a P&R tool (e.g., 13a of FIG. 3 or 22a of FIG. 4). In one embodiment, step S310 may correspond to step S220 of FIG. 5. Furthermore, in one embodiment, step S310 may also correspond to steps S220 and S230 of FIG. 5.

In step S320, trial routing is performed on the deployed standard cells. Here, trial routing refers to routing for selecting a timing critical path. In step S330, timing analysis is performed. Specifically, timing analysis can be performed to select a timing critical path among a plurality of timing paths in the deployed standard cells, and timing analysis result analysis data can be provided.

Here, the timing path can be divided into a data path, a clock path, a clock gating path, and an asynchronous path, and each timing path has a start point and an end point. Specifically, the timing path can refer to combinational logic and interconnect between parts of the integrated circuit, such as between an input pad and an output pad, between an input pad and a data input of a flip-flop, between a data output of a flip-flop and a data input of another flip-flop, and between a data output of a flip-flop and an output pad. The delay through the timing path is an important parameter of the integrated circuit, because the operating speed of the integrated circuit can be determined by the delay through the timing path.

Here, a timing critical path may refer to a timing path in which the total timing delay from an input (i.e., a starting point) to an output (i.e., an ending point) exceeds timing constraints. In one embodiment, a timing critical path may refer to a timing path having a maximum delay. Hereinafter, timing analysis will be described in more detail with reference to FIG. 7.

FIG. 7 is a graph showing the results of timing analysis according to one embodiment of the present disclosure.

Referring to FIG. 7, the horizontal axis represents slack, and the vertical axis represents the number of timing paths. Here, the slack represents the difference between the required time and the actual arrival time according to the timing requirement, and can be measured using a timing analyzer or a timing analysis module (for example, 13b of FIG. 3 or 22b of FIG. 4). Specifically, positive slack represents that the timing requirement is satisfied and therefore there is no timing violation, whereas negative slack represents that the timing requirement is not satisfied and therefore a timing violation occurs. Therefore, timing paths corresponding to negative slack in FIG. 7 can correspond to a timing critical path (TCP).

Referring back to FIG. 6, in step S340, nets of the timing critical path are selected. Specifically, by applying the analysis data acquired in step S330 to the standard cells arranged in S310, i.e., in a state before the trial routing of step S320 is performed, at least one net among the plurality of nets included in the timing critical path can be selected. For example, nets corresponding to a specific range of the timing critical path can be selected.

In step S350, the selected nets are routed to the air gap layer. In one embodiment, the selected net may correspond to a first conductive pattern included in a first wiring layer, a via electrically connected to the first conductive pattern, and a second conductive pattern included in a second wiring layer and electrically connected to the via. In one embodiment, the air gap patterns are arranged on both sides of the first conductive pattern, and the air gap patterns are arranged on both sides of the second conductive pattern, thereby routing the selected nets to two air gap layers. Hereinafter, step S350 will be described in more detail with reference to FIGS. 8 and 9A to 9C.

FIG. 8 illustrates a wiring structure (81) routed using an air gap layer (AGL) according to one embodiment of the present disclosure.

Referring to FIG. 8, the wiring structure (81) corresponds to a timing critical path, and only the fifth and sixth wiring layers (M5, M6) corresponding to a part of the wiring structure (81) can be routed to the air gap layer (AGL). Here, the fifth and sixth wiring layers (M5, M6) can correspond to selected nets of the timing critical path. The first wiring layer (M1) can include first and second pins (P1, P2), and for example, the first and second pins (P1, P2) can correspond to input pins (or starting points) and output pins (or ending points) of the timing critical path, respectively.

A timing-critical path is a timing path among timing paths in placed standard cells that does not satisfy timing constraints. Therefore, parasitic capacitance between conductive patterns in a timing-critical path can have a significant impact on the performance of an integrated circuit and a chip including the same, specifically, on the operating speed. According to the present embodiment, a net included in a timing-critical path can be pre-routed to an air-gap layer, and specifically, an air-gap pattern can be placed on both sides of a wiring layer forming a net included in the timing-critical path.

According to the present embodiment, the selected net of the timing critical path can be pre-routed to the air gap layer, thereby reducing the parasitic capacitance between the conductive patterns constituting the selected net of the timing critical path. Accordingly, the overall timing delay of the timing critical path is reduced, so that the timing critical path can satisfy the timing constraint. Therefore, the operating speed of the integrated circuit and the chip including the same can be significantly improved.

FIGS. 9A to 9C are perspective views each showing timing critical path nets routed to an air gap layer according to one embodiment of the present disclosure. For example, the timing critical path nets illustrated in FIGS. 9A to 9C may correspond to the fifth and sixth wiring layers (M5, M6) of FIG. 8.

Referring to FIG. 9a, a timing critical path net (100) may be a net connecting a first connection point (CP1) and a second connection point (CP2). The timing critical path net (100) may include a fifth wiring layer (M5) electrically connected to the first connection point (CP1), a via (V5) disposed on the fifth wiring layer (M5) and electrically connected to the fifth wiring layer (M5), and a sixth wiring layer (M6) disposed on the via (V5) and electrically connected to the via (V5). At this time, the fifth wiring layer (M5) extends in the Y direction, the sixth wiring layer (M6) extends in the X direction, and the X direction and the Y direction may be substantially perpendicular to each other. For example, the fifth and sixth wiring layers (M5, M6) may correspond to the fifth and sixth wiring layers (M5, M6) of FIG. 8, respectively.

In the present embodiment, both the fifth and sixth wiring layers (M5, M6) may be implemented as air gap layers. Specifically, air gap patterns (AGP1, AGP1') may be arranged on both sides of the fifth wiring layer (M5), and air gap patterns (AGP2, AGP2') may be arranged on both sides of the sixth wiring layer (M6). However, the present invention is not limited thereto, and in some embodiments, an air gap pattern may be arranged only on one side of the fifth wiring layer (M5), and an IMD made of a general dielectric material may be arranged on the other side of the fifth wiring layer (M5). Similarly, an air gap pattern may be arranged only on one side of the sixth wiring layer (M6), and an IMD made of a general dielectric material may be arranged on the other side of the sixth wiring layer (M6).

In the present embodiment, the air gap patterns (AGP1, AGP1') may extend in the Y direction, and the air gap patterns (AGP2, AGP2') may extend in the X direction. According to the present embodiment, the critical path net (100) may be implemented with bidirectional air gap layers. Accordingly, both the fifth and sixth wiring layers (M5, M6), which are two consecutive wiring layers adjacent in the Z direction, may be implemented with air gap layers. In this way, by utilizing the bidirectional air gap layers, the air gap volume becomes a maximum of almost 100% regardless of the positions of the first and second connection points (CP1, CP2) of the critical path net (100), thereby maximizing the performance gain of the integrated circuit.

Referring to FIG. 9b, the timing critical path net (100a) is a modified example of FIG. 9a, and the timing critical path net (100a) may include a fifth wiring layer (M5), a via (V5), and a sixth wiring layer (M6). In the present embodiment, among the fifth and sixth wiring layers (M5, M6), only the fifth wiring layer (M5) may be implemented as an air gap layer. Specifically, air gap patterns (AGP1, AGP1') may be arranged on both sides of the fifth wiring layer (M5), and an IMD made of a general dielectric material may be arranged on both sides of the sixth wiring layer (M6). However, the present invention is not limited thereto, and in some embodiments, an air gap pattern may be arranged only on one side of the fifth wiring layer (M5), and an IMD made of a general dielectric material may be arranged on the other side of the fifth wiring layer (M5).

Referring to FIG. 9c, the timing critical path net (100b) is a modified example of FIG. 9a, and the timing critical path net (100b) may include a fifth wiring layer (M5), a via (V5), and a sixth wiring layer (M6). In the present embodiment, among the fifth and sixth wiring layers (M5, M6), only the sixth wiring layer (M6) may be implemented as an air gap layer. Specifically, air gap patterns (AGP2, AGP2') may be arranged on both sides of the sixth wiring layer (M6), and an IMD made of a general dielectric material may be arranged on both sides of the fifth wiring layer (M5). However, the present invention is not limited thereto, and in some embodiments, an air gap pattern may be arranged only on one side of the sixth wiring layer (M6), and an IMD made of a general dielectric material may be arranged on the other side of the sixth wiring layer (M6).

As described above with reference to FIGS. 9A to 9C, the free routing for the selected net can be performed in various ways. For example, the number of air gap layers and/or the number of air gap patterns can be variably determined depending on the size of the slack based on the timing analysis results. In addition, the number of air gap layers and/or the number of air gap patterns can be variably determined by further considering other constraints, such as power constraints or area constraints, in addition to timing constraints.

Referring back to FIG. 7, in step S360, unselected nets are routed. In one embodiment, the unselected nets may include nets included in non-critical paths among timing paths within standard cells. In one embodiment, the unselected nets may further include nets other than the nets selected in step S340 among the nets included in timing critical paths.

In one embodiment, the unselected net may correspond to a first conductive pattern included in a first wiring layer, a via electrically connected to the first conductive pattern, and a second conductive pattern included in a second wiring layer and electrically connected to the via, wherein the unselected net may be routed by arranging a general dielectric material instead of air gap patterns on both sides of each of the first and second conductive patterns. Step S360 will be described in more detail below with reference to FIG. 10.

FIG. 10 illustrates a wiring structure (101) routed using a general layer according to one embodiment of the present disclosure.

Referring to FIG. 10, the wiring structure (101) corresponds to a non-critical path, and the first to sixth wiring layers (M1 to M6) included in the wiring structure (101) can be routed as general layers. The first wiring layer (M1) can include first and second pins (P1, P2), and for example, the first and second pins (P1, P2) can correspond to an input pin (or starting point) and an output pin (or ending point) of the non-critical path, respectively.

A non-critical path is a timing path that satisfies timing constraints among timing paths in placed standard cells. Therefore, parasitic capacitance between conductive patterns in a non-critical path may not have a significant effect on the performance of an integrated circuit and a chip including the same, specifically, on the operating speed. Therefore, according to the present embodiment, nets included in a non-critical path may be routed to a general layer, and specifically, an IMD including a general dielectric material may be placed on both sides of a wiring layer forming the nets included in the non-critical path.

According to the present embodiment, by routing the nets of the non-critical path and the unselected nets of the timing-critical path to a general layer, the number of airgap layers required for manufacturing the integrated circuit can be reduced, thereby reducing the manufacturing cost of the integrated circuit. In addition, according to the present embodiment, by pre-routing the selected nets of the timing-critical path to the airgap layer, the operating speed of the integrated circuit and the chip including the same can be significantly improved.

Referring back to FIG. 7, at step S370, post-route optimization is performed. Post-route optimization fixes timing and design rule violations that exist after routing is completed. After post-route optimization, ECO routing is performed to reflect changes in the netlist to the layout, thereby generating the final layout.

FIG. 11a is a plan view showing an integrated circuit (200) routed by applying an air gap pattern according to one embodiment of the present disclosure, and FIG. 11b is a perspective view showing the integrated circuit (200) of FIG. 11a.

Referring to FIGS. 11A and 11B, the integrated circuit (200) may correspond to one net composed of first and second connection points (210, 215) and a conductive pattern (220). At this time, the first and second connection points (210, 215) may be arranged on the same layer, and the Y coordinates may be the same and the X coordinates may be different from each other. Specifically, the integrated circuit (200) may include a conductive pattern (220) between the first and second connection points (210, 215) and air gap patterns (230, 235) arranged on both sides of the conductive pattern (220).

In the present embodiment, the conductive pattern (220) may constitute a timing critical path, and thus, air gap patterns (230, 235) may be arranged on both sides of the conductive pattern (220). The conductive pattern (220) extends in the X direction, and thus, the air gap patterns (230, 235) may also extend in the X direction. For example, the conductive pattern (220) may correspond to the fifth or sixth wiring layer (M5 or M6) of FIG. 8.

FIG. 12a is a plan view showing an integrated circuit (300) routed by applying an air gap pattern according to one embodiment of the present disclosure, and FIG. 12b is a perspective view showing the integrated circuit (300) of FIG. 12a.

Referring to FIGS. 12A and 12B, the integrated circuit (300) may correspond to one net composed of first and second connection points (310, 315) and first and second conductive patterns (320, 350). At this time, the first and second connection points (310, 315) may be arranged in different layers, respectively, and the Y coordinate may be the same and the X coordinate may be different. Specifically, the integrated circuit (300) may include a first conductive pattern (320) connected to a first connection point (310), first and second vias (340, 345) on the first conductive pattern (320), a second conductive pattern (350) on the second via (345), first air gap patterns (330, 335) arranged on both sides of the first conductive pattern (320), and second air gap patterns (360, 365) arranged on both sides of the second conductive pattern (350).

In the present embodiment, the first and second conductive patterns (320, 350) may form a timing critical path, and accordingly, the first air gap patterns (330, 335) may be arranged on both sides of the first conductive pattern (320), and the second air gap patterns (360, 365) may be arranged on both sides of the second conductive pattern (350). The first conductive pattern (320) may extend in the X direction, and the first air gap patterns (330, 335) may also extend in the X direction. The second conductive pattern (350) may extend in the X direction, and the second air gap patterns (360, 365) may also extend in the X direction. For example, the first and second conductive patterns (320, 350) may correspond to the fifth and sixth wiring layers (M5, M6) of FIG. 8, respectively.

FIG. 13a is a plan view showing an integrated circuit (400) routed by applying an air gap pattern according to one embodiment of the present disclosure, and FIG. 13b is a perspective view showing the integrated circuit (400) of FIG. 13a.

Referring to FIGS. 13A and 13B, the integrated circuit (400) may correspond to one net composed of first and second connection points (410, 415) and a conductive pattern (420). At this time, the first and second connection points (410, 415) may be arranged on the same layer, and the X coordinates may be the same and the Y coordinates may be different from each other. Specifically, the integrated circuit (400) may include a conductive pattern (420) between the first and second connection points (410, 415) and air gap patterns (430, 435) arranged on both sides of the conductive pattern (420).

In the present embodiment, the conductive pattern (420) may constitute a timing critical path, and accordingly, air gap patterns (430, 435) may be arranged on both sides of the conductive pattern (420). The conductive pattern (420) may extend in the Y direction, and the air gap patterns (430, 435) may also extend in the Y direction. For example, the conductive pattern (420) may correspond to the fifth or sixth wiring layer (M5 or M6) of FIG. 8.

FIG. 14a is a plan view showing an integrated circuit (500) routed by applying an air gap pattern according to one embodiment of the present disclosure, FIG. 14b is a perspective view showing the integrated circuit (500) of FIG. 14a, and FIG. 14c shows an integrated circuit (500') according to a comparative example for FIG. 14a.

Referring to FIGS. 14A and 14B, the integrated circuit (500) may correspond to one net composed of first and second connection points (510, 515) and first and second conductive patterns (520, 550). At this time, the first and second connection points (510, 515) may be arranged in different layers, respectively, and the X coordinate may be the same and the Y coordinate may be different. Specifically, the integrated circuit (500) may include a first conductive pattern (520) connected to a first connection point (510), first and second vias (540, 545) on the first conductive pattern (520), a second conductive pattern (550) on the second via (545), first air gap patterns (530, 535) arranged on both sides of the first conductive pattern (520), and second air gap patterns (560, 565) arranged on both sides of the second conductive pattern (550).

In the present embodiment, the first and second conductive patterns (520, 550) may form a timing critical path, and accordingly, the first air gap patterns (530, 535) may be arranged on both sides of the first conductive pattern (520), and the second air gap patterns (560, 565) may be arranged on both sides of the second conductive pattern (550). The first conductive pattern (520) may extend in the Y direction, and the first air gap patterns (530, 535) may also extend in the Y direction. The second conductive pattern (550) may extend in the Y direction, and the second air gap patterns (560, 565) may also extend in the Y direction. For example, the first and second conductive patterns (520, 550) may correspond to the fifth and sixth wiring layers (M5, M6) of FIG. 8, respectively.

Referring to FIG. 14c, it is assumed that the integrated circuit (500') according to the comparative example is implemented to include only a unidirectional air gap layer. For example, if the integrated circuit (500') is implemented to include only an air gap layer including air gap patterns extending in the X direction, an air gap pattern extending in the Y direction cannot be inserted adjacent to the first and second conductive patterns (520, 550). At this time, since the parasitic capacitance between the conductive patterns constituting the net of the timing critical path cannot be reduced, it is difficult to improve the operating speed of the integrated circuit and the chip including the same. Meanwhile, if the extension direction of the first and second conductive patterns (520, 550) in the integrated circuit (500') is modified to the X direction in order to utilize the air gap patterns extending in the X direction, cost, area, and/or time consumption may increase.

FIG. 15a is a plan view showing an integrated circuit (600) routed by applying an air gap pattern according to one embodiment of the present disclosure, and FIG. 15b is a perspective view showing the integrated circuit (600) of FIG. 15a.

Referring to FIGS. 15A and 15B, the integrated circuit (600) may correspond to one net composed of first and second connection points (610, 615) and first and second conductive patterns (620, 650). At this time, the first and second connection points (610, 615) may be arranged in different layers, respectively, and the X-coordinate and the Y-coordinate may be different from each other. Specifically, the integrated circuit (600) may include a first conductive pattern (620) connected to a first connection point (610), a via (640) on the first conductive pattern (620), a second conductive pattern (650) on the via (640), first air gap patterns (630, 635) arranged on both sides of the first conductive pattern (620), and second air gap patterns (660, 665) arranged on both sides of the second conductive pattern (650).

In the present embodiment, the first and second conductive patterns (620, 650) may form a timing critical path, and accordingly, first air gap patterns (630, 635) may be arranged on both sides of the first conductive pattern (620), and second air gap patterns (660, 665) may be arranged on both sides of the second conductive pattern (650). The first conductive pattern (620) may extend in the Y direction, and the first air gap patterns (630, 635) may also extend in the Y direction. The second conductive pattern (650) may extend in the X direction, and the second air gap patterns (660, 665) may also extend in the X direction. For example, the first and second conductive patterns (620, 650) may correspond to the fifth and sixth wiring layers (M5, M6) of FIG. 8, respectively.

As such, according to the present embodiment, the first air gap patterns (630, 635) may be arranged to extend in the Y direction, and the second air gap patterns (660, 665) may be arranged to extend in the X direction. In other words, the first and second air gap patterns (630, 635, 660, 665) may be implemented as bidirectional air gap patterns. Accordingly, two consecutive layers adjacent in the Z direction may be implemented as air gap layers. On the other hand, when the air gap patterns are implemented as unidirectional air gap patterns, two adjacent layers cannot be implemented as air gap layers, and only the alternately arranged layers may be implemented as air gap layers.

FIG. 16 is a layout of a standard cell (700) included in an integrated circuit according to one embodiment of the present disclosure.

Referring to FIG. 16, a standard cell (700) is defined by a cell boundary (CB) and may include a plurality of fins (FN), first and second active regions (AR1, AR2), a plurality of gate lines (GLa, GLb, GLc; GL), a plurality of first metal lines (M1a, M1b, M1c; M1) and a second metal line (M2). In addition, the standard cell (700) may further include first air gap patterns (AGP1a, AGP1b) and second air gap patterns (AGP2a, AGP2b). For example, the first metal line (M1a), the second via (V1) on the first metal line (M1b) and the second metal line (M2) may form a timing critical path net.

A cell boundary (CB) is an outline that defines a standard cell (700), and a placement and routing tool (e.g., 13a in FIG. 3 or 22a in FIG. 4) can recognize a standard cell (700) using the cell boundary (CB). The cell boundary (CB) consists of four boundary lines.

A plurality of fins (FN) may extend in the X direction and be arranged parallel to each other along the Y direction perpendicular to the X direction. The first active region (AR1) and the second active region (AR2) may be arranged parallel to each other and may have different conductivity types. Specifically, in the present embodiment, three fins (FN) may be arranged in each of the first and second active regions (AR1, AR2). However, the present invention is not limited thereto, and the number of fins (FN) arranged in each of the first and second active regions (AR1, AR2) may be variously changed.

At this time, the plurality of fins (FN) arranged in the first and second active regions (AR1, AR2) may be referred to as active fins. In FIG. 16, only active fins are illustrated, but the present invention is not limited thereto, and the standard cell (700) may further include dummy fins arranged in an area between the cell boundary (CB) and the first active region (AR1), the first and second active regions (AR1, AR2), or the area between the second active region (AR2) and the cell boundary (CB).

A plurality of gate lines (GL) may extend in the Y direction and may be arranged parallel to each other along the X direction. At this time, the gate lines (GL) may be composed of any material having electrical conductivity, and may include, for example, polysilicon, a metal, a metal alloy, etc. In FIG. 16, the standard cell (700) is illustrated as including three gate lines (GL), but this is only one embodiment, and the standard cell (700) may include four or more gate lines (GL) extending in the Y direction and arranged parallel to each other along the X direction.

The first vias (V0) are respectively arranged on the plurality of gate lines (GLa, GLb, GLc) to electrically connect the plurality of gate lines (GLa, GLb, GLc) and the plurality of first metal lines (M1a, M1b, M1c), respectively. At this time, the first vias (V0) may be composed of any material having electrical conductivity, and may include, for example, polysilicon, a metal, a metal alloy, etc.

A plurality of first metal lines (M1) may form a layer arranged on top of a plurality of gate lines (GL). For example, the first metal line (M1a) may correspond to the first conductive pattern (620) of FIG. 15b. At this time, the first metal lines (M1) may be composed of any material having electrical conductivity, and may include, for example, polysilicon, a metal, a metal alloy, etc.

The first metal lines (M1) may extend in the Y direction and may be arranged parallel to each other along the X direction. However, the present invention is not limited thereto, and in some embodiments, some of the first metal lines (M1) may be implemented in an L shape in which a portion of the first metal lines extends in the Y direction and another portion extends in the X direction. Although the standard cell (700) is illustrated in FIG. 16 as including three first metal lines (M1), this is only one embodiment, and the standard cell (700) may include four or more first metal lines (M1).

The second vias (V1) are respectively arranged on the plurality of first metal lines (M1a, M1c) to electrically connect the plurality of first metal lines (M1a, M1c) and the second metal line (M2). For example, the second via (V1) on the first metal line (M1a) may correspond to the via (640) of FIG. 15b. At this time, the second vias (V1) may be composed of any material having electrical conductivity, and may include, for example, polysilicon, a metal, a metal alloy, etc.

The second metal line (M2) may form a layer arranged on top of a plurality of first metal lines (M1). For example, the second metal line (M2) may correspond to the second conductive pattern (650) of FIG. 15B. At this time, the second metal line (M2) may be composed of any material having electrical conductivity, and may include, for example, polysilicon, a metal, a metal alloy, etc.

The second metal line (M2) may extend in the X direction. However, the present invention is not limited thereto, and in some embodiments, the second metal line (M2) may be implemented in an L shape in which one part extends in the X direction and the other part extends in the Y direction. Although the standard cell (700) is illustrated in FIG. 16 as including one second metal line (M2), this is only one embodiment, and the standard cell (700) may include two or more second metal lines (M2).

According to the present embodiment, first air gap patterns (AGP1a, AGP1b) may be arranged between a plurality of first metal lines (M1a to M1c). At this time, the first air gap patterns (AGP1a, AGP1b) may be formed to extend in the Y direction along the extension direction of the first metal lines (M1a to M1c). Accordingly, the plurality of first metal lines (M1a to M1c) and the first air gap patterns (AGP1a, AGP1b) may form a first air gap layer, and thereby, parasitic capacitance between the plurality of first metal lines (Ma1 to M1c) may be reduced.

In addition, according to the present embodiment, second air gap patterns (AGP2a, AGP2b) may be arranged on both sides of the second metal line (M2). At this time, the second air gap patterns (AGP2a, AGP2b) may be formed to extend in the X direction along the extension direction of the second metal line (M2). Accordingly, the second metal line (M2) and the second air gap patterns (AGP2a, AGP2b) may form a second air gap layer, thereby reducing parasitic capacitance between the second metal line (M2) and an adjacent metal line.

As described above with reference to FIGS. 1 to 16, according to embodiments of the present disclosure, in a step of designing a layout of an integrated circuit, a timing critical path may be selected from among timing paths in arranged standard cells, and at least one net may be selected from among nets of the selected timing critical paths. Subsequently, the at least one selected net may be pre-routed to an airgap layer, and the nets of non-critical paths and unselected nets of the timing critical paths may be routed to a general layer. Accordingly, a high-performance integrated circuit may be implemented at a low cost by using a small number of airgap layers.

FIG. 17 is a block diagram illustrating a storage medium (1000) according to one embodiment of the present disclosure.

Referring to FIG. 17, the storage medium (1000) can store a cell library (1100), layout data (1200), a placement and routing program (1300), and a timing analysis program (1400). The storage medium (1000) is a computer-readable storage medium, and can include any storage medium that can be read by a computer while being used to provide instructions and/or data to the computer. For example, the computer-readable storage medium (1000) can include magnetic or optical media such as a disk, a tape, a CD-ROM, a DVD-ROM, a CD-R, a CD-RW, a DVD-R, a DVD-RW, and the like, volatile or nonvolatile memory such as a RAM, a ROM, a flash memory, a nonvolatile memory accessible via a USB interface, and microelectromechanical systems (MEMS). The computer-readable storage medium can be inserted into the computer, integrated into the computer, or coupled to the computer via a communication medium such as a network and/or a wireless link.

The cell library (1100) may be a standard cell library and may include information about standard cells, which are units that constitute an integrated circuit. In one embodiment, the information about the standard cells may include layout information required for layout generation. In one embodiment, the information about the standard cells may include timing information required for layout verification or simulation.

Layout data (1200) may include physical information about a layout generated through placement and routing operations. In one embodiment, layout data (1200) may include width values and space values of the challenge patterns, and the number and size of air gap patterns arranged between the challenge patterns.

The placement and routing program (1300) may include a plurality of instructions to perform a method of generating a layout of an integrated circuit using a standard cell library according to exemplary embodiments of the present invention. The placement and routing program (1300) may be used to perform, for example, steps S110 and S130 of FIG. 1, steps S210, S260, and S270 of FIG. 5, or steps S310, S320, S350, and S360 of FIG. 6.

The timing analysis program (1400) may be, for example, a Static Timing Analysis (STA) program. STA is a simulation method for calculating the expected timing of a digital circuit, and may perform timing analysis on all timing paths of placed standard cells and output the timing analysis results. The STA program (1400) may be used to perform, for example, step S120 of FIG. 1, steps S240 and S250 of FIG. 5, or step S330 of FIG. 6.

In some embodiments, the storage medium (1000) may further store an analysis program, and the analysis program may include a plurality of commands that perform a method of analyzing an integrated circuit based on input data defining the integrated circuit. In some embodiments, the storage medium (1000) may further store a data structure, and the data structure may include a storage space for managing data generated in a process of using a standard cell library included in the standard cell library (1100), extracting specific information from a standard cell library included in the standard cell library (1100), or analyzing a characteristic of the integrated circuit by the analysis program.

As described above, exemplary embodiments have been disclosed in the drawings and the specification. Although specific terms have been used in the specification to describe the embodiments, these have been used only for the purpose of explaining the technical idea of the present disclosure and have not been used to limit the meaning or the scope of the present disclosure described in the claims. Therefore, those skilled in the art will understand that various modifications and equivalent other embodiments are possible therefrom. Accordingly, the true technical protection scope of the present disclosure should be determined by the technical idea of the appended claims.

10, 20: Integrated Circuit Design System
100, 100a, 100b: Timing Critical Pass Net
IC, 200, 300, 400, 500, 600: Integrated Circuits
700: Standard Cell

Claims (10)

A computer implemented method of manufacturing an integrated circuit, the method being performed at least in part by a processor,
A step of arranging standard cells defining the above integrated circuit;
A step of pre-routing at least one net of a timing critical path among the timing paths within the placed standard cells to an air-gap layer;
A step of routing nets of non-critical paths among the above timing paths; and
A method comprising the steps of manufacturing the integrated circuit based on the above pre-routing and the layout generated according to the above routing. In the first paragraph,
A method characterized in that the above routing step routes nets other than at least one net among a plurality of nets of the timing critical path and nets of the non-critical path. In the first paragraph,
wherein said at least one net comprises a first challenge pattern, a via on said first challenge pattern, and a second challenge pattern on said via,
The above air gap layer,
A first layer comprising the first challenge pattern and at least one first air gap pattern adjacent to the first challenge pattern; and
A method characterized by comprising at least one of a second layer including the second challenge pattern and at least one second air gap pattern adjacent to the second challenge pattern. In the third paragraph,
The above first challenge pattern and the above first air gap patterns extend along the first direction,
A method characterized in that the second challenge pattern and the second air gap patterns extend along a second direction substantially perpendicular to the first direction. In the third paragraph,
A method characterized in that the first and second challenge patterns and the first and second air gap patterns extend along the same direction. In the first paragraph,
A method characterized in that the above air gap layer is implemented as bidirectional air gap layers. In the first paragraph,
A method characterized in that, prior to the above-mentioned pre-routing step, it further comprises a step of selecting a timing critical path among the timing paths by performing timing analysis on the placed standard cells. In Article 7,
The step of selecting the above timing critical path is,
A step of performing trial routing on the above-described arranged standard cells;
A step of performing timing analysis on the standard cells on which the trial routing has been performed;
A step of selecting the timing critical path among the timing paths according to the result of the timing analysis; and
A method characterized by comprising a step of selecting at least one net in the timing critical path. In Article 7,
A method characterized by further comprising, after the step of placing, and before the step of selecting, a step of performing clock tree synthesis on the plurality of placed cells. delete

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