KR102426781B1 - Semiconductor device and light emitting module having thereof - Google Patents

Abstract

The light emitting device disclosed in the embodiment includes a semiconductor layer based on gallium oxide; a metal electrode on the semiconductor layer; and an ohmic contact layer disposed in the semiconductor layer and in contact with the metal electrode, wherein the ohmic contact layer includes an oxidizing composition having an element constituting the metal electrode.

Description

A semiconductor device and a light emitting module having the same

The embodiment relates to a gallium oxide-based semiconductor device.

The embodiment relates to a light emitting module having a gallium oxide-based semiconductor device.

As one of the light emitting devices, a light emitting diode (LED: Light Emitting Diode) is widely used. Light emitting diodes use the properties of compound semiconductors to convert electrical signals into light forms such as infrared, visible, and ultraviolet. As the light efficiency of the light emitting device increases, the light emitting device is applied to various fields including display devices, vehicle lamps, and various lighting devices.

On the other hand, transparent electrodes are being used in various fields such as LEDs, optical devices, power devices, solar cells, medical UV sterilizers, and fishery industry, and their application fields and their demand are gradually increasing. In particular, transparent electrodes are widely used in the LED field, and the current transparent electrode technology applied to LEDs can be applied to some areas (365 nm to 400 nm) of the visible light region (400 nm-800 nm) and the ultraviolet region (10 nm-400 nm). ITO (Indium Tin Oxide)-based technology is the mainstay. Recently, although the demand for UV LEDs that generate light in the ultraviolet region is rapidly increasing, transparent electrodes exhibiting high conductivity and high transmittance in the ultraviolet region have not been developed so far, so it is difficult to commercialize the ultraviolet LED. For example, in the case of a UV LED having an ITO transparent electrode, which is currently most used, most of the light in the short-wavelength ultraviolet region (10 nm to 320 nm) generated in the active layer is absorbed by the ITO, and the light is transmitted through the ITO and extracted to the outside. This is only about 1%. To solve this problem, a metal electrode pad was directly formed without forming a transparent electrode on the semiconductor layer. Since it is concentrated on the electrode pad and not supplied to the entire active layer, there is a problem in that the amount of light generated from the active layer is remarkably reduced.

The embodiment provides a semiconductor device in which an ohmic contact layer is disposed between a gallium oxide-based semiconductor layer and a metal electrode.

The embodiment provides a semiconductor device capable of reducing contact resistance between a gallium oxide-based semiconductor layer and a metal electrode.

The embodiment provides a semiconductor device including a gallium oxide-based semiconductor layer and a transparent electrode having the metal electrode between the metal electrode.

The embodiment provides a method of manufacturing a semiconductor device in which a gallium oxide-based semiconductor layer and a metal electrode are formed, and then a transparent electrode having the metal electrode is formed by heat treatment.

Provided is a light emitting module having a semiconductor device according to an embodiment.

A semiconductor device according to an embodiment includes a gallium oxide-based semiconductor layer; a metal electrode on the semiconductor layer; and an ohmic contact layer disposed in the semiconductor layer and in contact with the metal electrode, wherein the ohmic contact layer includes an oxidizing composition having an element constituting the metal electrode.

The ohmic contact resistance of the semiconductor device having the gallium oxide-based semiconductor layer according to the embodiment may be lowered.

The embodiment may lower the ohmic contact resistance of a light emitting device having a gallium oxide-based semiconductor layer.

The embodiment may prevent deterioration of the film quality of the gallium oxide-based semiconductor layer of the semiconductor device.

It is possible to improve the reliability of the semiconductor device or the light emitting device and the light emitting module having the same according to the embodiment.

1 is a side cross-sectional view showing a semiconductor device having a gallium oxide-based semiconductor layer according to a first embodiment.
FIG. 2 is a view showing a detailed configuration diagram of the metal electrode of FIG. 1 .
3 and 4 are diagrams illustrating examples of patterns of the metal electrode of FIG. 1 .
FIG. 5 is a view for explaining a manufacturing process of the semiconductor device of FIG. 1 .
6 is a side cross-sectional view illustrating a semiconductor device according to a second embodiment.
7 is a modified example of the semiconductor device of FIG. 6 .
8 is a diagram illustrating an MESFET as an example of a gallium oxide-based semiconductor device according to an embodiment.
9 is a voltage/current graph according to a heat treatment process of a semiconductor device according to an embodiment.
10 and 11 are views comparing X-ray diffraction spectroscopy (XRD) analysis results before and after heat treatment of a semiconductor device according to an embodiment.
12 is a diagram illustrating a package including the semiconductor device of FIG. 6 according to an embodiment.

In the description of an embodiment, each layer (film), region, pattern or structure is “on” or “under” the substrate, each layer (film), region, pad or pattern. In the case of being described as being formed on, "on" and "under" include both "directly" or "indirectly" formed through another layer. do. In addition, the criteria for the upper / upper or lower / lower of each layer will be described with reference to the drawings.

Hereinafter, light emitting devices according to embodiments will be described in detail with reference to the accompanying drawings.

1 is a side cross-sectional view showing a semiconductor device having a gallium oxide-based semiconductor layer according to a first embodiment, FIG. 2 is a view showing a detailed configuration diagram of the metal electrode of FIG. 1, FIGS. 3 and 4 are FIG. 1 It is a diagram showing an example of a pattern of a metal electrode.

1 to 4 , the semiconductor device includes a substrate 11 , a gallium oxide-based semiconductor layer 13 on the substrate 11 , a metal electrode 17 on the semiconductor layer 13 , and the semiconductor An ohmic contact layer 15 is included between the layer 13 and the metal electrode 17 .

The substrate 11 may be, for example, a light-transmitting, conductive, or insulating substrate. For example, the substrate 11 is sapphire (Al ₂ O ₃ ), SiC, Si, GaAs, GaN, ZnO, GaP, InP, Ge, and Ga ₂ O ₃ may include at least one of A plurality of protrusions (not shown) may be formed on the upper surface and/or lower surface of the substrate 11, and each of the plurality of protrusions has a side cross-section, including at least one of a hemispherical shape, a polygonal shape, and an elliptical shape, It may be arranged in a stripe form or a matrix form. The protrusion may improve light extraction efficiency. A plurality of compound semiconductor layers may be disposed on the substrate 11 . The substrate 11 may include the same gallium oxide semiconductor as the gallium oxide-based semiconductor layer 13 , for example, β-Ga ₂ O ₃ .

The gallium oxide-based semiconductor layer 13 is disposed on the substrate 11 and includes β-Ga ₂ O ₃ , and a dopant may be added thereto. The gallium oxide-based semiconductor layer 13 may include at least one of an n-type dopant and a p-type dopant, and may include a single-layer or multi-layer structure. The gallium oxide-based semiconductor layer 13 may be an n-type semiconductor layer when an n-type dopant is added, and may be a p-type semiconductor layer when a p-type dopant is added. The multilayered gallium oxide-based semiconductor layer 13 may be stacked with a group II to group VI compound semiconductor layer, and may include an n-type semiconductor layer, an active layer, and a p-type semiconductor layer. At least one or two of the n-type semiconductor layer, the active layer, and the p-type semiconductor layer may be selected from GaN, AlN, AlGaN, InGaN, InN, InAlGaN, AlInN, AlGaAs, GaP, GaAs, GaAsP, or AlGaInP. The semiconductor layer 13 may be implemented as any one of an np junction structure, a pn junction structure, an npn junction structure, and a pnp junction structure.

The gallium oxide-based semiconductor layer 13 according to the embodiment may be a conductive semiconductor layer or a conductive substrate. When the gallium oxide-based semiconductor layer 13 is a conductive substrate, the substrate 11 may be removed. This gallium oxide-based semiconductor layer 13 has a wide band gap of 4.6 to 4.7 eV or more, is a direct transition semiconductor material, has high thermal conductivity, is chemically stable, and exhibits transparency of 80% or more in the ultraviolet to visible ray region. will have However, the gallium oxide-based semiconductor layer 13 having a wide band gap has difficulty in forming an ohmic contact with the metal electrode 17, and when a transparent electrode such as ITO is used, the light efficiency is lowered in the ultraviolet region. there is a problem. In addition, as a method of lowering the resistance for the ohmic contact, an ion implantation method may be used. However, the process cost is high, the process is complicated, and the quality of the resulting film may be deteriorated due to defects.

In the embodiment, in order to solve the above problem, the ohmic contact layer 15 may be formed by diffusing an element used as the metal electrode 17 on the surface of the gallium oxide-based semiconductor layer 13 . The ohmic contact layer 15 may be formed of an oxidizing composition of an element and oxygen constituting the metal electrode 17, and the elements constituting the metal electrode 17 include tin (Sn), titanium (Ti), chromium ( Cr) and indium (In) may be included. The ohmic contact layer 15 may include at least one of SnO _x (0<x≤2), TiO, CrO, and InO.

The gallium oxide-based semiconductor layer 13 may include an n-type dopant, for example, at least one of tin (Sn), titanium (Ti), chromium (Cr), and indium (In). In addition, the metal electrode 17 may include at least one of tin (Sn), titanium (Ti), chromium (Cr), and indium (In), for example, an n-type dopant added to the semiconductor layer 13 and It may contain the same metal. Here, the concentration of the n-type dopant in the semiconductor layer 13 may be in the range of 1x10 ¹⁷ to ^{9x10 18} cm ^-3 , for example, 2x10 ^{18 to} 9x10 ¹⁸ cm -3. When the concentration of the n-type dopant is lower than the range, conductivity properties may be deteriorated, and when the concentration of the n-type dopant is higher than the range, defects may be further generated by the dopant.

In the ohmic contact layer 15 , an element of the metal electrode 17 is diffused into the semiconductor layer 13 having an n-type dopant, so that an electron density may be increased. Accordingly, the contact resistance of the ohmic contact layer 15 may be lowered, for example, in the range of 5 × 10 ^-6 to 1 × 10 ^-4 Ω·cm ² . In addition, the ohmic contact layer 15 may prevent a decrease in optical efficiency in the ultraviolet region.

The metal electrode 17 and the ohmic contact layer 15 may be disposed to overlap each other in a vertical direction, and may have one or a plurality of female patterns, and/or a curved pattern. As shown in FIG. 3 , when the metal electrode 17 is formed in a form in which, for example, a plurality of arm patterns P0 , P1 , P2 , P3 are connected, or is formed in a matrix-shaped pattern P4 as shown in FIG. 4 , the The ohmic contact layer 15 may be formed in the same pattern as that of the metal electrode 17 .

The ohmic contact layer 15 may have a larger area than a lower surface area of the metal electrode 17 . This may give an area difference from the metal electrode 17 by removing the metal electrode 17 on the ohmic contact layer 15 by partial etching. When the ohmic contact layer 15 has a larger surface area, light extraction efficiency may be improved. A top surface of the ohmic contact layer 15 may be disposed on the same horizontal plane as the top surface of the semiconductor layer 13 . Since the ohmic contact layer 15 is disposed in the semiconductor layer 13 without protruding above the upper surface of the semiconductor layer 13 , it is possible to prevent an increase in resistance due to a separate component.

As shown in FIG. 2 , the metal electrode 17 includes a plurality of layer structures, for example, a first layer 17A in contact with the ohmic contact layer 15 , and a second layer on the first layer 17A. (17B), a third layer 17C may be included on the second layer 17B. The first layer 17A may include at least one of tin (Sn), titanium (Ti), chromium (Cr), and indium (In), and may be the same metal element as a dopant in the semiconductor layer 13 . The second layer 17B is a barrier metal for preventing diffusion at the interface between the first layer 17A and the third layer 17C, and includes at least one of Ni, Rh, Pd, Ir, Ru, Mg, and Zn. can be formed. The third layer 17C is a bonding metal, to which a wire may be bonded, and may include at least one of Au, Ag, Al, and Cu. The first layer 17A includes a range of 15 nm to 25 nm, for example, a range of 18 nm to 22 nm, the second layer 17B includes a range of 15 nm to 25 nm, for example, a range of 18 nm to 22 nm, and the third layer 17C may include a range of 80 nm to 120 nm, for example, a range of 90 nm to 110 nm, and when the thickness of the first layer 17A is thinner than the thickness range, heat treatment affects the second layer 17B. If it is thicker than the above thickness, electrical properties may be reduced.

In the embodiment, the ohmic contact layer 15 is described as an example of an oxidation composition using an n-type dopant, but may be implemented as an oxidation composition using a p-type dopant, but is not limited thereto.

Referring to FIG. 5 , in the manufacturing process of a semiconductor device, a gallium oxide-based semiconductor layer 13 is grown on a substrate 11 , and the growth method at this time is an electron beam evaporator, PVD (physical vapor deposition), or CVD. (chemical vapor deposition), plasma laser deposition (PLD), dual-type thermal evaporator sputtering (sputtering), may be grown by MOCVD (metal organic chemical vapor deposition). Alternatively, the gallium oxide-based semiconductor layer 13 may form a β-Ga2O3 bulk-based single crystal layer by, for example, a CZ method (Czochralski method) or a FZ (Floating Zone Technique) method, but is not limited thereto. .

An n-type dopant may be added to the gallium oxide-based semiconductor layer 13 , and the n-type dopant includes at least one of tin (Sn), titanium (Ti), chromium (Cr), and indium (In). can do.

A metal electrode 17 is deposited on the gallium oxide-based semiconductor layer 13 , and the metal electrode 17 may be stacked in a multi-layer structure 17A, 17B, and 17C as shown in FIG. 2 . For example, the metal electrode 17 may be patterned by a photolithography process, and may be deposited using an E-beam deposition method. Among the multilayer structures of the metal electrode 17, the first layer (17A in FIG. 2) in contact with the gallium oxide-based semiconductor layer 13 is tin (Sn), titanium (Ti), chromium (Cr), indium ( In) may be formed of at least one of.

Thereafter, heat treatment may be performed to form an ohmic contact layer 15 between the gallium oxide-based semiconductor layer 13 and the metal electrode 17 . In the ohmic contact layer 15 , the element of the metal electrode 17 is diffused in the gallium oxide semiconductor layer 13 , and a region in contact with the metal electrode 17 forms the metal electrode 17 . It can be formed from a composition of elements and oxygen. The heat treatment process may be performed for a predetermined time by supplying a predetermined temperature, for example, a temperature of 500 degrees or more, a predetermined pressure, for example, a pressure of 8.0 torr or more, and an atmospheric gas, for example, argon (Ar) using a furnace. By this heat treatment process, the metal electrode 17, for example, Sn is diffused in the gallium oxide-based semiconductor layer 13 having an n-type dopant (eg Sn), and Sn and gallium oxide react to form a thin ohmic contact layer ( 15) can be formed. The ohmic contact layer 15 may reduce the contact resistance between the metal electrode 17 and the gallium oxide-based semiconductor layer 13 . In addition, by forming the ohmic contact layer 15 by diffusion of ions by heat, it is possible to suppress the occurrence of defects in the lattice of the gallium oxide semiconductor layer 13 .

9 is a graph illustrating a bias voltage-current relationship according to an annealing method of a rapid thermal process (RTP) and annealing of a furnace, and it can be seen that the bias voltage and current are improved after annealing of the furnace.

10 is an X-ray diffraction analysis (XRD) analysis result before heat treatment of a semiconductor device, and FIG. 11 shows an XRD analysis result after heat treatment of a semiconductor device. 11 is different from FIG. 11 , it can be seen that SnO ₂ (111) or SnO (213) appears after heat treatment. The ohmic contact layer 15 may be used as a transparent electrode and may provide high transmittance in the ultraviolet region.

6 is a view showing an example of a light emitting device as a semiconductor device having a gallium oxide-based semiconductor layer according to the embodiment.

Referring to FIG. 6 , a light emitting device, which is a semiconductor device, includes a first conductive semiconductor layer 41 , an active layer 50 disposed on the first conductive semiconductor layer 41 , and an active layer 50 on the active layer 50 . It may include an electron blocking layer 71 disposed on the electron blocking layer 71 , and a second conductivity type semiconductor layer 75 disposed on the electron blocking layer 71 .

The light emitting device may include one or more or both of the buffer layer 31 and the substrate 21 under the first conductivity type semiconductor layer 41 . The light emitting device includes a first cladding layer 43 between the first conductive semiconductor layer 41 and the active layer 50 and a second cladding layer between the active layer 50 and the second conductive semiconductor layer 75 . (not shown) may include at least one or all of.

The substrate 21 may be, for example, a light-transmitting, conductive, or insulating substrate. For example, the substrate 21 is sapphire (Al ₂ O ₃ ), SiC, Si, GaAs, GaN, ZnO, GaP, InP, Ge, and Ga ₂ O ₃ may include at least one of A plurality of protrusions (not shown) may be formed on the upper and / or lower surfaces of the substrate 21, and each of the plurality of protrusions has a side cross-section, including at least one of a hemispherical shape, a polygonal shape, and an elliptical shape, It may be arranged in a stripe form or a matrix form. The protrusion may improve light extraction efficiency. A plurality of compound semiconductor layers may be disposed on the substrate 21 , and equipment for growing the plurality of compound semiconductor layers is an electron beam evaporator, physical vapor deposition (PVD), chemical vapor deposition (CVD), or plasma laser deposition (PLD). , a dual-type thermal evaporator may be formed by sputtering, metal organic chemical vapor deposition (MOCVD), or the like, but is not limited thereto.

The buffer layer 31 may be disposed between the substrate 21 and the first conductivity type semiconductor layer 41 . The buffer layer 31 may be formed of at least one layer using a group II to group VI compound semiconductor. The buffer layer 31 includes a semiconductor layer using a group III-V compound semiconductor, for example, In _x Al _y Ga _{1 -x- y} N (0≤x≤1, 0≤y≤1, 0≤x) It can be implemented with a semiconductor material having a composition formula of +y≤1). The buffer layer 31 may include, for example, at least one of GaN, AlN, AlGaN, InGaN, InN, InAlGaN, AlInN, AlGaAs, GaP, GaAs, GaAsP, AlGaInP, ZnO, Ga ₂ O ₃ materials such as a single layer or It may be formed in multiple layers. The buffer layer 31 may include a super lattice structure in which different semiconductor layers are alternately disposed. The buffer layer 31 may be formed to alleviate a difference in lattice constant between the substrate 21 and the nitride-based semiconductor layer, and may be defined as a defect control layer. The lattice constant of the buffer layer 31 may have a value between the lattice constant between the substrate 21 and the nitride-based semiconductor layer. The buffer layer 31 may include an undoped semiconductor layer, and the undoped semiconductor layer may have lower electrical conductivity than the first conductivity type semiconductor layer 41 . The undoped semiconductor layer has a first conductivity type characteristic even if it is not intentionally doped with a conductivity type dopant. The buffer layer 31 may be formed as a single layer or multiple layers.

The first conductive semiconductor layer 41 may be disposed between at least one of the substrate 21 and the buffer layer 31 and the active layer 50 . The first conductivity type semiconductor layer 41 may be implemented as at least one of group III-V and group II-VI compound semiconductors doped with a first conductivity type dopant. The first conductivity type semiconductor layer 41 is, for example, a semiconductor having a composition formula of In _x Al _y Ga _{1 -x- y} N (0≤x≤1, 0≤y≤1, 0≤x+y≤1) It may be formed of a material. The first conductive semiconductor layer 41 includes, for example, at least one of GaN, AlN, AlGaN, InGaN, InN, InAlGaN, AlInN, AlGaAs, GaP, GaAs, GaAsP, AlGaInP, ZnO, Ga ₂ O ₃ , can do. The first conductivity-type semiconductor layer 41 may be an n-type semiconductor layer doped with an n-type dopant such as Si, Ge, Sn, Se, Te, Sn, Ti, Cr, or In. The first conductive semiconductor layer 41 may be disposed as a single layer or a multilayer. The first conductive semiconductor layer 41 may have a superlattice structure in which at least two different layers are alternately disposed. The first conductive semiconductor layer 41 may be an electrode contact layer.

The first clad layer 43 may include at least one of a group II-VI group and a group III-V compound semiconductor. The first clad layer 43 may be an n-type semiconductor layer having a dopant of a first conductivity type, for example, an n-type dopant. The first clad layer 43 may include at least one of GaN, AlN, AlGaN, InGaN, InN, InAlGaN, AlInN, AlGaAs, GaP, GaAs, GaAsP, and AlGaInP, and an n-type semiconductor doped with an n-type dopant. can be layered. The first clad layer 43 may be formed as a single layer or a multilayer.

The active layer 50 may be formed of at least one of a single well, a single quantum well, a multi well, a multi quantum well (MQW) structure, a quantum wire (Quantum-Wire) structure, or a quantum dot structure. can In the active layer 50, electrons (or holes) injected through the first conductivity type semiconductor layer 41 and holes (or electrons) injected through the second conductivity type semiconductor layer 75 meet each other, and the This is a layer that emits light due to a difference in the band gap of an energy band according to a material forming the active layer 50 . The active layer 50 may be implemented with a compound semiconductor. The active layer 50 may be implemented, for example, by at least one of group II-VI and group III-V compound semiconductors.

When the active layer 50 is implemented in a multi-well structure, the active layer 50 includes a plurality of well layers and a plurality of barrier layers alternately arranged, and the well layer/barrier layer pair is formed in 2 to 30 cycles. can be The period of the well/barrier layer may be, for example, InGaN/GaN, GaN/AlGaN, AlGaN/AlGaN, InGaN/AlGaN, InGaN/InGaN, AlGaAs/GaAs, InGaAs/GaAs, InGaP/GaP, AlInGaP/InGaP, or and at least one of the InP/GaAs pairs. The well layer may be formed of, for example, a semiconductor material having a composition formula of In _x Al _y Ga _{1 -x- y} N (0<x≤1, 0≤y≤1, 0≤x+y<1). The barrier layer may be formed of, for example, a semiconductor material having a composition formula of In _x Al _y Ga _{1 -x- y} N (0≤x≤1, 0≤y≤1, 0≤x+y<1). The active layer 50 may emit at least one peak wavelength among ultraviolet, blue, green, and red wavelengths. For example, the active layer 50 may provide a different peak wavelength of each light emitting chip according to the composition of indium or aluminum.

The electron blocking layer 71 is disposed on the active layer 50 . The electron blocking layer 71 may include an AlGaN-based semiconductor. The electron blocking layer 71 may be a p-type semiconductor layer having a second conductivity-type dopant, for example, a p-type dopant. The electron blocking layer 71 may include at least one of GaN, AlN, AlGaN, InGaN, InN, InAlGaN, AlInN, AlGaAs, GaP, GaAs, GaAsP, or AlGaInP, and Mg, Zn, Ca, Sr, Ba It may include a p-type dopant such as

A second conductive semiconductor layer 75 may be disposed on the electron blocking layer 71 . The second conductivity type semiconductor layer 75 is, for example, a semiconductor having a composition formula of In _x Al _y Ga _{1 -x- y} N (0≤x≤1, 0≤y≤1, 0≤x+y≤1). It may be formed of a material. The second conductive semiconductor layer 75 may include, for example, at least one of GaN, AlN, AlGaN, InGaN, InN, InAlGaN, AlInN, AlGaAs, GaP, GaAs, GaAsP, or AlGaInP, and a p-type dopant. may be a doped p-type semiconductor layer. The second conductive semiconductor layer 75 may be disposed as a single layer or a multilayer. The second conductive semiconductor layer 75 may have a superlattice structure in which at least two different layers are alternately disposed. The second conductive semiconductor layer 75 may be an electrode contact layer.

A gallium oxide-based semiconductor layer 93 may be disposed between the second conductive semiconductor layer 75 and the second electrode 95 . The gallium oxide-based semiconductor layer 93 may be implemented as an n-type semiconductor layer to which the n-type dopant disclosed in the embodiment is added. The n-type dopant added to the gallium oxide-based semiconductor layer may include, for example, at least one of tin (Sn), titanium (Ti), chromium (Cr), and indium (In).

The light emitting structure may include a first conductive semiconductor layer 41 to a second conductive semiconductor layer 75 . As another example, in the light emitting structure, the first conductivity type semiconductor layer 41 and the first clad layer 43 are p-type semiconductor layers, and the second clad layer 73 and the second conductivity type semiconductor layer 75 are n It may be implemented as a type semiconductor layer. Such a light emitting structure may be implemented as any one of an n-p junction structure and a p-n junction structure. A gallium oxide-based semiconductor layer 93 may be stacked on the light emitting structure as an n-type semiconductor layer or a p-type semiconductor layer.

The light emitting device includes a first electrode 91 and a second electrode 95 . A first electrode 91 may be electrically connected to the first conductive semiconductor layer 41 , and a second electrode 95 may be electrically connected to the gallium oxide-based semiconductor layer 93 . The first electrode 91 may be disposed on the first conductivity type semiconductor layer 41 , and the second electrode 95 may be disposed on the gallium oxide-based semiconductor layer 93 . The first electrode 91 and the second electrode 95 may further have a current diffusion pattern having an arm structure or a finger structure.

A first ohmic contact layer 15A may be disposed between the first electrode 91 and the first conductive semiconductor layer 41, and the first ohmic contact layer 15A is an ohmic contact layer disclosed in the embodiment. In the case where the first conductive semiconductor layer 41 is a gallium oxide-based semiconductor, the first conductive semiconductor layer 41 is formed by diffusion of an element constituting the first electrode 91 according to the embodiment. can be formed. Accordingly, the first ohmic contact layer 15A may lower the contact resistance between the first conductive semiconductor layer 41 and the first electrode 91 . The first ohmic contact layer 15A may not be formed, but is not limited thereto. Also, when the substrate 21 and the buffer layer 31 are gallium oxide-based semiconductors, the first electrode 91 and the first ohmic contact layer 15A may be removed.

A second ohmic contact layer 15B may be formed between the second electrode 95 and the gallium oxide-based semiconductor layer 93 , and the second ohmic contact layer 15B is an ohmic contact layer disclosed in the embodiment. can be layered. As another example, when the second conductivity type semiconductor layer 75 is a gallium oxide-based semiconductor, the second conductivity type semiconductor layer 75 is transferred to the second conductivity type semiconductor layer 75 by diffusion of an element constituting the second electrode 95 . An ohmic contact layer 15B may be formed. Accordingly, the second ohmic contact layer 15B may lower the contact resistance between the gallium oxide-based semiconductor layer 93 and the second electrode 95 . The first electrode 91 and the second electrode 95 are formed in the same structure as in FIG. 3, or Sn, Ti, Cr, Ru, Rh, Ir, Mg, Zn, Al, In, Ta, Pd, Co, It may be selected from at least one of Ni, Si, Ge, Ag and Au, or an optional alloy thereof.

An insulating layer 81 may be disposed on the surfaces of the semiconductor layers 41 , 43 , 50 , 71 , and 75 . The insulating layer 81 may be disposed on the upper surface of the second conductive semiconductor layer 75 and on the side surfaces of the semiconductor layers 41 , 43 , 50 , 71 and 75 , and the first and second electrodes 91 and 95 . ) can be selectively contacted. The insulating layer 81 includes an insulating material or insulating resin formed of at least one of oxide, nitride, fluoride, and sulfide having at least one of Al, Cr, Si, Ti, Zn, and Zr. The insulating layer 81 may be selectively formed from, for example, SiO ₂ , Si ₃ N ₄ , Al ₂ O ₃ , and TiO ₂ . The insulating layer 81 may be formed as a single layer or multiple layers or may be removed.

7 is a view showing an example of a vertical light emitting chip using the light emitting device of FIG. In the description of FIG. 7 , the same parts as those of the configuration shown in FIG. 6 will be referred to the description of the embodiment disclosed above.

Referring to FIG. 7 , the light emitting device includes a first electrode 91 on the first conductive semiconductor layer 41 and a plurality of conductive layers 96 , 97 , 98 and 99 under the second conductive semiconductor layer 75 . and a second electrode having

The second electrode is disposed under the second conductive semiconductor layer 75 , and includes a contact layer 96 , a reflective layer 97 , a bonding layer 98 , and a support member 99 . The contact layer 96 is in contact with a semiconductor layer, for example, the second conductive semiconductor layer 75 . The contact layer 96 may include at least one of Sn, Ti, Cr, and In.

Here, a gallium oxide-based semiconductor layer 93 is disposed between the contact layer 96 and the second conductive semiconductor layer 75 , and a second ohmic contact layer is disposed on the gallium oxide-based semiconductor layer 93 . (15D) may be disposed. The second ohmic contact layer 15D is formed on the gallium oxide-based semiconductor layer 93, or when the second conductive semiconductor layer 75 is a gallium oxide-based semiconductor, the layer 93 is removed and the first It may be formed on the second conductive semiconductor layer 75 . The second ohmic contact layer 15D may be formed in the gallium oxide-based semiconductor layer 93 , and may contain at least one of tin (Sn), titanium (Ti), chromium (Cr), and indium (In) and oxygen. composition may be included. The second ohmic contact layer 15D may not be formed.

A reflective layer 97 is disposed under the contact layer 96, and the reflective layer 97 is composed of Ag, Ni, Al, Rh, Pd, Ir, Ru, Mg, Zn, Pt, Au, Hf, and combinations thereof. It may be formed in a structure including at least one layer made of a material selected from the group. The reflective layer 97 may be in contact under the second conductivity type semiconductor layer 75 , but is not limited thereto. A bonding layer 98 is disposed under the reflective layer 97, and the bonding layer 98 may be used as a barrier metal or a bonding metal, and the material thereof is, for example, Ti, Au, Sn, Ni, Cr, at least one of Ga, In, Bi, Cu, Ag and Ta and an optional alloy.

A protective layer 83 and a current blocking layer 85 are disposed between the second conductive semiconductor layer 75 and the second electrode. The protective layer 83 is formed along the lower edge of the second conductive semiconductor layer 75 and may be formed in a ring shape, a loop shape, or a frame shape. The protective layer 83 may include a transparent conductive material or an insulating material, for example, at least one of SiO ₂ , SiO _x , SiO _x N _y , Si ₃ N ₄ , Al ₂ O ₃ , and TiO ₂ . The protective layer 83 may not be formed. The inner portion of the protective layer 83 is disposed under the second conductivity type semiconductor layer 75 , and the outer portion is disposed further outside the side surface of the light emitting structure. The current blocking layer 85 may be disposed between the second conductive semiconductor layer 75 and the contact layer 96 or the reflective layer 97 . The current blocking layer 85 includes an insulating material, for example, SiO ₂ , SiO _x , SiO _x N _y , Si ₃ N ₄ , Al ₂ O ₃ , TiO ₂ It may include at least one of As another example, the current blocking layer 85 may be formed of a metal for a Schottky contact.

The current blocking layer 85 is disposed to correspond to the first electrode 91 disposed on the light emitting structure in a thickness direction of the light emitting structure. The current blocking layer 85 may block the current supplied from the second electrode and spread it to another path. One or a plurality of the current blocking layers 85 may be disposed, and at least a portion or the entire region may overlap the first electrode 91 in a vertical direction.

A support member 99 is formed under the bonding layer 98 , and the support member 99 may be formed of a conductive member, and the material is copper (Cu-copper), gold (Au-gold), or nickel. It may be formed of a conductive material such as (Ni-nickel), molybdenum (Mo), copper-tungsten (Cu-W), or a carrier wafer (eg, Si, Ge, GaAs, ZnO, SiC, etc.). As another example, the support member 99 may be implemented as a conductive sheet.

Here, the substrate of FIG. 6 may be removed. The substrate may be removed by a physical method (eg, laser lift off) and/or a chemical method (eg, wet etching) to expose the first conductive semiconductor layer 41 . The first electrode 91 is formed on the first conductivity type semiconductor layer 41 by performing isolation etching in the direction in which the substrate is removed. A light extraction structure (not shown) such as roughness may be formed on the upper surface of the first conductive semiconductor layer 41 . An insulating layer (not shown) may be further disposed on the surface of the semiconductor layer, but is not limited thereto. Accordingly, a light emitting chip having a vertical electrode structure including the first electrode 91 on the light emitting structure and the support member 99 below may be manufactured.

When the first conductive semiconductor layer 41 is a gallium oxide-based semiconductor, the first ohmic contact layer 15C according to the embodiment is disposed between the first electrode 91 and the first conductive semiconductor layer 41 . ) can be placed. The ohmic contact layer may include a composition of oxygen and at least one of tin (Sn), titanium (Ti), chromium (Cr), and indium (In).

The gallium oxide-based semiconductor device according to the embodiment is a device having a stacked structure of a gallium oxide-based semiconductor layer/ohmic contact layer/electrode. schottky) can be applied to devices such as diodes. The junction-type field effect transistor (JFET), a Schottky barrier field effect transistor (MESFET) using a Schottky contact of a metal-semiconductor structure, a MIS field effect transistor (MISFET or MOSFET) having a metal-insulator-semiconductor structure, such as It can be applied to devices.

8 is an example of a FET having a gallium oxide-based semiconductor layer, for example, an MESFET according to an embodiment.

Referring to FIG. 8 , the FET semiconductor device includes a substrate 211 , a semiconductor layer 213 on the substrate 211 , a gate electrode 215 on the semiconductor layer 213 , and a source electrode. 217 and a drain electrode 219 may be formed. The substrate 211 may be a gallium oxide-based semiconductor, and may be doped with a p-type dopant.

The semiconductor layer 213 may be formed of the gallium oxide-based semiconductor disclosed in the embodiment, and an n-type dopant may be added thereto. The ohmic contact layers 221 , 223 , and 225 described in the embodiment may be formed on the semiconductor layer 213 under the gate electrode 215 , the source electrode 217 , and the drain electrode 219 . The ohmic contact layers 221 , 223 , and 225 may lower the contact resistance between the respective electrodes 215 , 217 and 219 and the semiconductor layer 213 .

<Light emitting device package>

12 is a view illustrating a light emitting device package including the light emitting device of FIG. 6 .

12 , the light emitting device package includes a support member 110 , a reflective member 111 having a cavity 112 on the support member 110 , an upper portion of the support member 110 and within the cavity 112 . The light emitting device 101 according to the embodiment includes a transparent window 115 on the cavity 112 .

The support member 110 is a resin-based printed circuit board (PCB), silicon-based such as silicon or silicon carbide (SiC), ceramic-based such as aluminum nitride (AlN), polyphthalic It may be formed of at least one of a resin series such as amide (polyphthalamide: PPA), liquid crystal polymer, and a metal core PCB (MCPCB) having a metal layer at the bottom, but is not limited to these materials.

The support member 110 includes a first metal layer 131 , a second metal layer 133 , a first connection member 138 , a second connection member 139 , a first electrode layer 135 , and a second electrode layer 137 . includes The first metal layer 131 and the second metal layer 132 are disposed on the bottom of the support member 110 to be spaced apart from each other. The first electrode layer 135 and the second electrode layer 137 are disposed on the upper surface of the support member 110 to be spaced apart from each other. The first connection member 138 may be disposed inside or on the first side surface of the support member 110 , and connects the first metal layer 131 and the first electrode layer 135 to each other. The second connection member 139 may be disposed inside or on the second side of the support member 110 , and connects the second metal layer 133 and the second electrode layer 137 to each other.

The first metal layer 131 , the second metal layer 133 , the first electrode layer 135 , and the second electrode layer 137 are made of a metal material, for example, titanium (Ti), copper (Cu), nickel (Ni). , may be formed of at least one of gold (Au), chromium (Cr), tantalum (Ta), platinum (Pt), tin (Sn), silver (Ag), phosphorus (P), or a selective alloy thereof, It may be formed of a single metal layer or a multi-layered metal layer.

The first connection member 138 and the second connection member 139 include at least one of a via, a via hole, and a through hole.

The reflective member 111 is disposed around the cavity 112 on the support member 110 , and may reflect the ultraviolet light emitted from the light emitting device 101 .

The reflective member 111 is a resin-based printed circuit board (PCB), silicon-based such as silicon or silicon carbide (SiC), ceramic-based such as AlN (aluminum nitride; AlN), polyphthalamide It may be formed of at least one of a resin series such as (polyphthalamide: PPA) and a liquid crystal polymer, but is not limited to these materials. The support member 110 and the reflective member 111 may include a ceramic-based material, and the ceramic-based material has a higher heat dissipation efficiency than a resin material.

The light emitting device 101 may be disposed on the second electrode layer 137 or on the support member 110 , and may be electrically connected to the first electrode layer 135 and the second electrode layer 137 . do. The light emitting device 101 may be connected with a wire 121 . As another example, the light emitting device 101 may be bonded in a flip chip method.

The light emitting device 101 may emit an ultraviolet wavelength or, when a phosphor layer is disposed on the light emitting device 101 , may emit light of a different wavelength.

The transparent window 115 is disposed on the cavity 112 and emits a peak wavelength emitted from the light emitting device 101 . The transparent window 115 may include a glass material, a ceramic material, or a light-transmitting resin material.

In addition, an optical lens or a phosphor layer may be further disposed on the cavity 112 , but the present invention is not limited thereto.

A semiconductor device, a light emitting device, or a light emitting device package according to an embodiment may be applied to a light unit. The light unit is an assembly including one or a plurality of light emitting devices or light emitting device packages, and may include an ultraviolet lamp.

A lens, a light guide plate, a prism sheet, a diffusion sheet, etc., which are optical members, may be disposed on the semiconductor device or the light emitting device according to the embodiment. The light unit may be implemented in a top view or side view type, and may be provided to display devices such as portable terminals and notebook computers, or may be variously applied to lighting devices and indicating devices. Another embodiment may be implemented as a lighting device including the light emitting device described in the above-described embodiments. For example, the lighting device may include a lamp, a street lamp, an electric billboard, and a headlamp.

Features, structures, effects, etc. described in the above embodiments are included in at least one embodiment of the present invention, and are not necessarily limited to only one embodiment. Furthermore, features, structures, effects, etc. illustrated in each embodiment can be combined or modified for other embodiments by a person skilled in the art to which the embodiments belong. Accordingly, the contents related to such combinations and modifications should be interpreted as being included in the scope of the present invention.

In addition, although the embodiment has been described above, it is only an example and does not limit the present invention, and those of ordinary skill in the art to which the present invention pertains are exemplified above in a range that does not depart from the essential characteristics of the present embodiment. It can be seen that various modifications and applications that have not been made are possible. For example, each component specifically shown in the embodiment may be implemented by modification. And the differences related to these modifications and applications should be construed as being included in the scope of the present invention defined in the appended claims.

11,21: substrate
13,93: gallium oxide-based semiconductor layer
15,15A,15B,15C,15D: Ohmic contact layer
17: metal electrode
17A: 1st floor
17B: 2nd floor
17C: 3rd floor
41: first conductive type semiconductor layer
43: first clad layer
50: active layer
71: electron blocking layer
75: second conductivity type semiconductor layer

Claims (12)

Gallium oxide-based semiconductor layer;
a metal electrode disposed on the semiconductor layer; and
and an ohmic contact layer disposed in the semiconductor layer and in contact with the metal electrode,
an upper surface of the ohmic contact layer is disposed on the same horizontal surface as an upper surface of the semiconductor layer;
The ohmic contact layer includes an oxidizing composition having an element constituting the metal electrode,
The gallium oxide-based semiconductor layer is a semiconductor device comprising β-Ga ₂ O ₃ . According to claim 1,
The metal electrode includes at least one of tin (Sn), titanium (Ti), chromium (Cr), and indium (In),
The ohmic contact layer includes a composition of oxygen and at least one of tin (Sn), titanium (Ti), chromium (Cr), and indium (In),
The ohmic contact layer is disposed to vertically overlap the metal electrode. 3. The method of claim 2,
The gallium oxide-based semiconductor layer is a semiconductor device comprising an n-type dopant. 4. The method of claim 2 or 3,
The metal electrode has one or a plurality of female patterns,
The gallium oxide-based semiconductor layer is a semiconductor device that emits at least one of ultraviolet light, blue, green, and red light. 4. The method according to any one of claims 1 to 3,
an insulating or conductive substrate under the gallium oxide-based semiconductor layer; and
A semiconductor device comprising a light emitting structure having a nitride semiconductor layer between the gallium oxide-based semiconductor layer and the substrate.
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