KR102190859B1 - Method of forming a p-type layer for a light emitting device - Google Patents

Abstract

In a method according to embodiments of the present invention, a semiconductor structure including a III-nitride light emitting layer disposed between a p-type region and an n-type region is grown. The p-type region is embedded within the semiconductor structure. The trench is formed in the semiconductor structure. The trench exposes the p-type region. After forming the trench, the semiconductor structure is annealed.

Description

Method of forming a P-type layer for a light emitting device {METHOD OF FORMING A P-TYPE LAYER FOR A LIGHT EMITTING DEVICE}

Cross-reference to related applications

This application claims priority to U.S. Provisional Patent Application No. 62/339,448, filed May 20, 2016, and European Patent Application No. 16179661.0, filed July 15, 2016. US Provisional Patent Application No. 62/339,448 and European Patent Application No. 16179661.0 are incorporated herein.

Including light emitting diodes (LEDs), resonant cavity light emitting diodes (RCLEDs), vertical cavity laser diodes (VCSELs), and edge emitting lasers. Semiconductor light emitting devices are currently available among the most efficient light sources. Material systems of current interest in the manufacture of high-brightness light-emitting devices capable of operating across the visible spectrum are group III-V semiconductors, in particular binary, 3, gallium, aluminum, indium, and nitrogen, also referred to as III-nitride materials. Circle, and quaternary alloys. Typically, III-nitride light-emitting devices are sapphire, silicon, or by metal-organic chemical vapor deposition (MOCVD), molecular beam epitaxy (MBE), or other epitaxial techniques. It is prepared by epitaxially growing a stack of semiconductor layers of different compositions and dopant concentrations on a carbide, III-nitride, or other suitable substrate. The stack can be, for example, one or more n-type layers doped with Si, often formed over a substrate, one or more light-emitting layers in the active region formed over the n-type layer or layers, and, for example, Mg formed over the active region. At least one p-type layer doped with. Electrical contacts are formed on the n- and p-type regions.

In commercial III-nitride LEDs, semiconductor structures are typically grown by MOCVD. The nitrogen source used during MOCVD is typically ammonia. When ammonia dissociates, hydrogen is produced. Hydrogen forms a complex with magnesium, and magnesium is used as a p-type dopant during the growth of p-type materials. The hydrogen complex deactivates the p-type property of magnesium, effectively reducing the dopant concentration of the p-type material and reducing the efficiency of the device. After the growth of the p-type material, the structure is annealed to destroy the hydrogen-magnesium complex by blocking the hydrogen.

1 illustrates a portion of a semiconductor structure including a buried p-type region and trenches for activating the p-type region.
2 illustrates a portion of the top surface of the structure illustrated in FIG. 1.
3 is a method of forming a device with a buried p-type region, according to some embodiments of the invention.
4 illustrates an LED with a p-type region grown before the n-type region, according to some embodiments of the invention.
5 illustrates an LED including a tunnel junction, in accordance with some embodiments of the invention.
6 illustrates a device comprising two LEDs separated by a tunnel junction, in accordance with some embodiments of the invention.
7 illustrates a portion of a partially grown semiconductor device, including segments of a mask material.
8 illustrates a portion of a semiconductor device with embedded trenches.
9 illustrates a portion of a semiconductor device including a trench in which metal contacts are disposed.

The requirement of annealing in an anhydrous atmosphere to activate the p-type layers in the III-nitride device limits the device design. It has been experimentally demonstrated that hydrogen cannot diffuse through n-type III-nitride materials, and that hydrogen does not readily diffuse laterally through the semiconductor material over distances corresponding to half the diameter of a typical device wafer. As a result, in order for the activation annealing to be effective, the p-type layers cannot be covered by any other layer. Without effective annealing, the device remains without a p-type layer, or with a p-type layer with an extremely low dopant concentration, making it useless. Thus, devices with buried p-type layers, such as devices with tunnel junctions or devices in which p-type layers are grown before n-type layers, will be formed by annealing after conventional processes including growth by MOCVD. Can't.

In embodiments of the invention, the device structure is grown with a buried p-type layer. Trenches are formed in the device structure exposing portions of the buried p-type layer. The structure is then annealed so that hydrogen can diffuse laterally into the trenches from the buried p-type layer, and hydrogen can escape around.

1 illustrates a portion of a semiconductor device structure. The structure of FIG. 1 is grown on a growth substrate 30, which can be, for example, a sapphire, SiC, Si, non-III-nitride material, GaN, a composite substrate, or any other suitable substrate. The optional III-nitride film 102 may be grown prior to the p-type region 100, but the III-nitride film 102 is not required. The III-nitride film 102 can be, for example, nucleation or buffer layers, smoothing layers, n-type layers, luminescent or active layers, undoped layers, which may be GaN or any other III-nitride material. Active regions, and/or any other suitable layers or materials.

The p-type region 100 comprises at least one binary, ternary, quaternary, or 5-membered III-nitride layer doped with a p-type dopant, such as Mg or any other suitable material. .

The III-nitride film 104 is grown after the p-type layer 100 such that the p-type layer 100 is embedded by the III-nitride film 104. The III-nitride film 104 may include n-type layers, p-type layers, active region of the device, emissive layers, undoped layers, and/or any other suitable layers or materials.

After or during growth, trenches 106 are formed in the semiconductor structure. The trenches 106 may extend through the entire thickness of the III-nitride film 104 such that the lower ends of the trenches 106 are in the p-type region 100, as illustrated in FIG. 1. Alternatively, the trenches 106 may be formed such that the lower ends of the trenches 106 are in the III-nitride film 102, the surface of the growth substrate 30, or extend into the growth substrate 30. 104) and the p-type region 100 may extend through the entire thicknesses of both.

The width 108 of the trenches 106 is, for example, at least 0.05 μm in some embodiments, 50 μm or less in some embodiments, at least 0.5 μm in some embodiments, and 15 μm in some embodiments. It can be below. In some embodiments, the trenches are kept as small as possible to avoid losing the light emitting area.

The trenches 106 are spaced such that all of the p-type region 100 is spaced a distance from the trench that is less than or equal to the maximum diffusion length of hydrogen during a later anneal. The maximum spacing 110 between the trenches 106 may be twice the average or maximum diffusion length of hydrogen during annealing. The spacing 110 may be determined by the conditions of the annealing, which may determine the maximum lateral diffusion length of hydrogen during annealing-different anneals may have different maximum lateral diffusion lengths. The maximum spacing 110 between closest neighboring trenches may be at least 1 μm in some embodiments, 500 μm or less in some embodiments, at least 5 μm in some embodiments, and 250 μm or less in some embodiments. have.

The semiconductor structure illustrated in FIG. 1 may be annealed after forming the trenches 106. During annealing, hydrogen is pushed from the p-type region 100 into the trenches 106, which can escape from the semiconductor structure around.

In some embodiments, after annealing, trenches 106 may be filled with insulating material 114. The insulating material 114 allows a metal contact to be formed on the surface with trenches, without accidentally causing a short. The insulating material 114 may be formed at any stage of processing after annealing-for example, the trenches 106 may be formed before or after removing the growth substrate, in embodiments where the growth substrate is removed, or In embodiments where etching is performed, it may be filled with insulating material 114 before or after etching to expose the buried layer.

In some embodiments, trenches 106 are used as vias on which metal contacts are formed to contact the p-type region in the device below the p-side, as illustrated in FIG. 9. In embodiments in which metal contacts 134 are formed in the trenches 106 in contact with the p-type region 100, a series of metals and insulators are formed in a trench (as illustrated in FIG. 9). It is deposited and patterned in direct contact only with the buried p-type region 100 or other desired layer (in the bottom of 132) and not in direct contact with the layers (III-nitride film 104). For example, the insulating material 130 may be disposed on the sidewalls of the trench between the contact metal 134 and semiconductor layers that do not directly contact the metal contact.

In some embodiments, trenches 106 are left exposed to air or ambient gas, or coated with a thin passivation layer (eg, SiO ₂ ) rather than being filled. Thus, in some embodiments, trenches 106 may be partially or completely filled with an insulating or passivating material.

2 is a plan view of a portion of the top surface 112 of the structure of FIG. 1. As illustrated in FIG. 2, in some embodiments, the trenches 106 are insulated from each other and may be surrounded by a portion of the semiconductor structure not interrupted by the trench. Thus, in some embodiments, all of the semiconductor material is electrically connected, and no electrically isolated islands of the semiconductor material are formed by the trenches 106. In some embodiments, some or all of the trenches may be connected to each other to form isolated islands of semiconductor material-for example, in some embodiments, the trenches 106 are later separated from the wafer of semiconductor material. You can define the boundaries of a single device. A single device formed on a wafer of devices includes some trenches connected to each other to define the boundaries of the device or an isolated island of semiconductor material within the device, and one or more others isolated from each other and formed within the isolated island of semiconductor material. You can have a trench.

3 illustrates a method of forming a device. In block 120, a III-nitride structure with a buried p-type region is grown on a growth substrate.

At block 122, trenches 106 are formed in the grown III-nitride structure. Trenches 106 are illustrated in FIGS. 1 and 2. The trenches 106 may be formed by any suitable technique, including, for example, dry etching, wet etching, or a combination of dry and wet etching. In some embodiments, the method of forming the trench can affect the diffusion of hydrogen from the exposed surface of the semiconductor material formed by etching the trench. For example, p-type GaN is known to be converted to n-type GaN during dry etching. If the thickness of the surface of the p-type converted to n-type is too large, the diffusion of hydrogen can be blocked so that hydrogen cannot accumulate and escape from the type-converted surface. Thus, in some embodiments, after dry etching to form the trenches 106, the surface of the trenches removes the n-type converted layer or increases the thickness of the n-type converted layer to a thickness at which hydrogen readily diffuses. It can be cleaned with a wet etch to reduce it.

In some embodiments, the semiconductor structure may be selectively grown to form trenches during growth, as illustrated in FIGS. 7 and 8. For example, as illustrated in FIG. 7, an optional III-nitride film 102 and p-type region 100 are grown over the substrate 30. A mask material 120 such as SiO ₂ may be disposed on the p-type region 100 and then patterned so that the mask material is left in the areas where the trenches are formed. The mask material is not limited to the position illustrated in FIG. 7. For example, in various embodiments, the mask material is a fully grown III-nitride film 102 on the surface of a partially grown III-nitride film 102, on a direct growth substrate, as illustrated. Is formed on the surface of the partially grown p-type region 100, or on the surface of the fully grown p-type region 100. As long as the mask material is in direct contact with at least a portion of the p-type region 100, the mask material is in any layer, on any surface (including directly on growth substrate 30), of any thickness of the device. It can be formed with and can extend through multiple layers.

A III-nitride film 104 is grown over the mask material 120. The growth eventually covers the mask material through lateral overgrowth, as illustrated in FIG. 8, so that the areas 122 between neighboring mask regions are filled with the III-nitride material. When the die is singulated after growth, wet etch or other suitable technique can be used to remove the mask material, creating a built-in trench 124 through which hydrogen can escape during activation annealing. During activation annealing, hydrogen escapes from the embedded trenches through the sides of the wafer, and the embedded trenches are exposed around it.

Returning to Figure 3, at block 124, the III-nitride structure with trenches activates the buried p-type region, for example by blocking hydrogen that has formed a complex with the p-type dopant in the p-type region. To make it, it is annealed.

4, 5, and 6 illustrate devices comprising a buried p-type region that can be activated by forming trenches and by annealing, as illustrated in FIGS. 1, 2, and 3 . 4 illustrates a device in which the p-type region is grown before the n-type region. 5 and 6 illustrate devices including tunnel junctions. Trenches are omitted from FIGS. 4, 5, and 6 for clarity. In particular, the devices illustrated in FIGS. 4, 5, and 6 may be, for example, approximately 1 mm on the side, which means tens or even hundreds of trenches may be formed in a single device. In any of the devices illustrated in FIGS. 4, 5, and 6, one or more of the trenches may be used as vias in which metal contacts to the buried layers of the device are placed, as described above.

In some embodiments, the p-type region of the III-nitride device is grown before the emissive layer and the n-type region.

In conventional III-nitride LEDs, an n-type region is first grown on a substrate, followed by light-emitting layers and a p-type semiconductor. The internal field of the III-nitride LED growing below the n-side increases with increasing forward bias. As a result, as the device bias (current) increases, the internal electric field increases, thereby reducing electron-hole overlap and thereby reducing the radiation efficiency. Growing the device in reverse order reverses the internal field, with the p-type region first grown on the substrate. In the III-nitride LED grown below the p-side, the internal field is opposite to the embedded polarization field. As a result, as the forward bias (current) increases, the radiating efficiency of such a device may increase.

4 illustrates an example of a device in which the p-type region is grown before the light emitting layer and the n-type region. Such semiconductor structures can be included in any suitable device; Embodiments of the invention are not limited to the vertical device illustrated. In embodiments where the original growth substrate is removed, such as, for example, a flip chip device, the structure 102 may be removed entirely to form electrical contacts in the p-type region, or the hole/trench may be a metal contact. May be etched through the structure 102 to expose a portion of the p-type region in which a may be formed. For example, in embodiments where the substrate remains, such as a lateral die device, one contact can be placed on the top surface of the semiconductor structure and the other contact is exposed by an etching exposing the p-type region. It can be placed on the surface.

The device illustrated in FIG. 4 includes a semiconductor structure 10 grown on a growth substrate (not shown). After the p-type region 12 is first grown, the active or light emitting region comprising at least one light emitting layer 14 is continued, followed by the n-type region 16.

P-type region 12 corresponds to buried p-type region 100 of FIG. 1; The active region 14 and the n-type region 16 correspond to the III-nitride film 104 of FIG. 1; The III-nitride film 102 of FIG. 1 may be a nucleating or buffer structure (not shown) or may be omitted.

Metal p-contact 18 is disposed on p-type region 12; The metallic n-contact 20 is disposed on the n-type region 16.

The semiconductor structure 10 includes a light emitting or active region sandwiched between an n-type region and a p-type region. The n-type region 16 is, for example, different compositions comprising n- or even p-type device layers designed for specific optical, material, or electrical properties desirable for the light-emitting region to emit light efficiently. And multiple layers of dopant concentration. The light-emitting layer 14 may be included in the light-emitting or active region. Examples of suitable light emitting regions include a single thick or thin light emitting layer, or a plurality of quantum well light emitting regions comprising a plurality of thin or thick light emitting layers separated by barrier layers. The p-type region 12 includes preparation layers such as buffer layers or nucleation layers, and/or layers designed to facilitate removal of the growth substrate, which may be p-type, n-type, or intentionally undoped, And multiple layers of different composition, thickness, and dopant concentration, including intentionally undoped layers, or n-type layers.

After growth, the semiconductor structure can be processed with any suitable device.

In some embodiments, the III-nitride device includes a tunnel junction. A tunnel junction (TJ) is a structure that allows electrons to tunnel from the valence band of the p-type layer to the conduction band of the n-type layer in reverse bias. When electrons are tunneled, holes remain behind the p-type layer, so carriers are generated in both layers. Thus, in an electronic device such as a diode, when only a small leakage current flows in the reverse bias, a large current can be carried across the tunnel junction in the reverse bias. Tunnel junctions typically have a specific alignment of conduction and valence bands in the p/n tunnel junction, which has been achieved in other material systems (e.g., p++/n++ junctions in (Al)GaAs material systems) using very high doping. need. III-nitride materials have an inherent polarization that creates an electric field at heterointerfaces between different alloy compositions. This polarization field can be used to achieve the required band alignment for tunneling.

5 and 6 illustrate two devices including tunnel junctions.

In the device of Figure 5, a tunnel junction is placed between a p-type region and a metal contact that injects current into the p-type region. The contact can be formed on the n-type layer, which can have much better sheet resistance and thus better current spreading compared to p-type layers. In the device illustrated in Fig. 5, the n-type layers convert holes from the p-type region to electrons in the n-type contact layer through a tunnel junction, thereby forming the contact layer for both the positive and negative terminals of the LED. Are used as fields.

The device of FIG. 5 includes an n-type region 32 that is grown on a growth substrate, a light emitting layer 34 that may then be disposed in the light emitting region, and a p-type region 36. The n-type region 32, the light emitting layer 34, and the p-type region 36 are detailed in the text accompanying FIG. 4. The tunnel junction 38 is formed over the p-type region 36.

In some embodiments, the tunnel junction 38 is also referred to as a p++ layer, a highly doped p-type layer in direct contact with the p-type region 36, and also referred to as an n++ layer, directly with the p++ layer. It comprises a highly doped n-type layer in contact. (In some embodiments, the p++ layer of the tunnel junction 38 can serve as a p-type region in the device, so a separate p-type region is not required.) In some embodiments, the tunnel junction 38 ) Comprises a layer of a composition different from the p++ layer and the n++ layer and the p++ layer sandwiched between the p++ layer and the n++ layer. In some embodiments, tunnel junction 38 includes an InGaN layer sandwiched between a p++ layer and an n++ layer. In some embodiments, tunnel junction 38 includes an AlN layer sandwiched between a p++ layer and an n++ layer. The tunnel junction 38 is in direct contact with the n-type layer 40 described below.

The p++ layer may be, for example, InGaN or GaN doped with an acceptor such as Mg or Zn to a concentration of about 10 ¹⁸ cm ^-3 to about 5×10 ²⁰ cm ^-3 . In some embodiments, the p++ layer is doped to a concentration of about 2×10 ²⁰ cm ^-3 to about 4×10 ²⁰ cm ^-3 . The n++ layer may be, for example, InGaN or GaN doped with an acceptor such as Si or Ge to a concentration of about 10 ¹⁸ cm ^-3 to about 5×10 ²⁰ cm ^-3 . In some embodiments, the n++ layer is doped to a concentration of about 7×10 ¹⁹ cm ^-3 to about 9×10 ¹⁹ cm ^-3 . The tunnel junction 38 is usually very thin, for example the tunnel junction 38 can have a total thickness ranging from about 2 nm to about 100 nm, and each of the p++ and n++ layers has a range of about 1 nm. It can have a thickness ranging from about 50 nm. In some embodiments, each of the p++ layer and the n++ layer can have a thickness ranging from about 25 nm to about 35 nm. The p++ layer and the n++ layer may not necessarily be of the same thickness. In one embodiment, the p++ layer is 15 nm of Mg-doped InGaN and the n++ layer is 30 nm of Si-doped GaN. The p++ layer and the n++ layer may have a sloped dopant concentration. For example, a portion of the p++ layer adjacent to the basic p-type region 36 may have a dopant concentration that slopes from the dopant concentration of the basic p-type region in the p++ layer to a desired dopant concentration. Similarly, the n++ layer may have a dopant concentration that slopes from a maximum adjacent to the p++ layer to a minimum adjacent to the n-type layer 40 formed over the tunnel junction 38. The tunnel junction 38 is made thin enough and sufficiently doped so that the tunnel junction 38 displays a low series of voltage drops when the conduction current is in reverse bias mode. In some embodiments, the voltage drop across tunnel junction 38 is between about 0.1V and about 1V.

Embodiments including an InGaN or AlN or other suitable layer between the p++ layer and the n++ layer may enhance the polarization field in the III-nitrides to help align the bands for tunneling. This polarization effect can reduce the doping requirement and reduce the tunneling distance required in the n++ and p++ layers (potentially allowing higher current flow). The composition of the layer between the p++ layer and the n++ layer may be different from the composition of the p++ layer and the n++ layer, and/or selected to cause realignment due to polarization charges present between other materials in the III-nitride material system. Can be.

Examples of suitable tunnel junctions are described in US8039352 B2, which patent is incorporated herein by reference.

An n-type contact layer 40 is formed over the tunnel junction 38, in direct contact with the n++ layer.

In the device of FIG. 5, the p-type region 36 and the p++ layer of the tunnel junction 38 correspond to the p-type region 100 of FIG. 1; The n++ layer and the n-type contact layer 40 of the tunnel junction 38 correspond to the III-nitride film 104 of FIG. 1; The n-type region 32 and the active region 34 correspond to the III-nitride film 102 of FIG. 1.

The first and second metal contacts 44 and 42 are formed on the n-type contact layer 40 and the n-type region 32, respectively. The mesa may be etched to form a flip chip device, as illustrated in FIG. 5, or any other suitable device structure may be used. The first and second metal contacts 44 and 42 may be the same material, such as aluminum, but this is not required; Any suitable contact metal or metals may be used.

In the device of Figure 6, a number of LEDs are grown on top of one another and connected in series through a tunnel junction. In the device of Figure 6, multiple LEDs are created within the footprint of a single LED, which can dramatically increase the optical flux generated per unit area. In addition, by driving the LEDs connected by the tunnel junction with a lower drive current, each LED can operate at its peak efficiency. In a single LED, this will cause a drop in the light output, but by having two or more LEDs connected in series in a given chip area, the light output can be maintained with a dramatic improvement in efficiency. Thus, the tunnel junction device illustrated in FIG. 6 can be used in applications requiring high efficiency and/or applications requiring high flux per unit area.

The device of Fig. 6 comprises an n-type region 32 grown on a growth substrate, followed by a light emitting layer 34, which may be disposed in the light emitting region, and a p-type region 36 (as described above. Likewise, the p++ layer of the tunnel junction can function as a p-type region 36, so a separate p-type region is not required). The n-type region 32, the light emitting layer 34, and the p-type region 36 are detailed in the text accompanying FIG. 4. The tunnel junction 38 is formed over the p-type region 36, as described above. A second device structure including a second n-type region 46, a second light emitting layer 48, and a second p-type region 50 is formed over the tunnel junction 38. The tunnel junction 38 is oriented such that the p++ layer directly contacts the p-type region 36 of the first LED and the n++ layer directly contacts the n-type region 46 of the second LED.

In the device of FIG. 6, the p-type region 36 and the p++ layer of the tunnel junction 38 correspond to the p-type region 100 of FIG. 1; The n++ layer, the n-type layer 46, the active region 48, and the p-type region 50 of the tunnel junction 38 correspond to the III-nitride film 104 of FIG. 1 (the trenches are p- Upon direct contact with the type region 50, the trenches will also activate the p-type region 50, through the p-type region 50, and if it is the last grown layer, it will also be activated by conventional annealing. Can); The n-type region 32 and the active region 34 correspond to the III-nitride film 102 of FIG. 1.

First and second metal contacts 54 and 52 are formed on the n-type region 32 of the first LED and the p-type region 50 of the second LED, respectively. The mesa may be etched to form a flip chip device, as illustrated in FIG. 6, or any other suitable device structure may be used. In some embodiments, the additional tunnel junction and the n-type layer are applied to the p-type of the second LED to form a second metal contact 52 on the n-type layer, as illustrated in the device of FIG. 5. It may be formed over the region 50.

Although two active regions are illustrated in FIG. 6, any number of active regions are the two illustrated if the p-type region adjacent to each active region is separated from the n-type region adjacent to the next active region by a tunnel junction. It may be included between metal contacts. Since the device of Fig. 6 has only two contacts, both light emitting layers emit light simultaneously and cannot be activated individually and separately. In other embodiments, individual LEDs in the stack can be activated separately by forming additional contacts. In some embodiments, the device may have sufficient junctions such that the device can operate at a typical line voltage such as 110 volts, 220 volts, or the like, for example.

The two light emitting layers can be made of the same composition, so that they emit the same color light, or can be made of different compositions, so that they emit light of different colors (ie, different peak wavelengths). For example, a three active area device with two contacts can be fabricated such that a first active area emits red light, a second active area emits blue light, and a third active area emits green light. have. When activated, the device can produce white light. Since active regions are stacked to appear to emit light from the same area, such devices avoid problems with color mixing present in devices combining red, blue, and green light from adjacent active regions rather than stacked ones. can do. In devices with active regions that emit light of different wavelengths, the active region generating light of the shortest wavelength can be located closest to the surface from which the light is extracted from the LED, typically a sapphire, SiC, or GaN growth substrate. The placement of the shortest wavelength active region close to the output surface can minimize losses due to absorption in the quantum wells of the other active regions and are more sensitive by locating longer wavelength active regions closer to the heat sink formed by the contacts. Thermal shock can be reduced on long wavelength quantum wells. Quantum well layers can also be made thin enough so that the absorption of light in the quantum well layers is low. The color of the mixed light emitted from the device can be controlled by selecting the number of active regions that emit light of each color. For example, the human eye is very sensitive to green photons and not to red and blue photons. To generate balanced white light, a stacked active area device can have a single green active area and multiple blue and red active areas.

The devices of FIGS. 4, 5, and 6 are formed by growing a III-nitride semiconductor structure on a growth substrate 30 as is known in the art. The growth substrate is often sapphire, but may be any suitable substrate such as, for example, SiC, Si, GaN, or a composite substrate (eg, such as GaN on a sapphire template). The surface of the growth substrate on which the III-nitride semiconductor structure is grown can be patterned, roughened, or textured prior to growth, which can improve light extraction from the device. The surface of the growth substrate opposite to the growth surface (i.e., the surface from which a large number of light is extracted from the flip chip configuration) can be patterned, roughened or textured before or after growth, which can improve light extraction from the device. have.

Metal contacts often include a number of conductive layers, such as a reflective metal and a guard metal that can prevent or reduce electron transfer of the reflective metal. The reflective metal is often silver, but any suitable material or materials can be used. The metal contacts are electrically insulated from each other by a gap that can be filled with a dielectric such as silicon or an oxide of any other suitable material. Multiple vias may be formed exposing portions of the n-type region 32; The metal contacts are not limited to the arrangements illustrated in FIGS. 4, 5, and 6. Metal contacts can be redistributed to form bond pads with a dielectric/metal stack, as in the art.

In order to make electrical connections to the LED, one or more interconnects are formed on or are electrically connected to the two metal contacts illustrated. The interconnects may be, for example, solder, stud bumps, gold layers, or any other suitable structure.

The substrate 30 can be thinned or completely removed. In some embodiments, the surface of the substrate 30 exposed by the thinning is patterned, textured, or roughened to improve light extraction.

Any of the devices described herein can be combined with a wavelength converting structure. The wavelength converting structure can include one or more wavelength converting materials. The wavelength converting structure may be connected directly to the LED, placed in close proximity to the LED but not directly connected to the LED, or may be spaced apart from the LED. The wavelength converting structure can be any suitable structure. The wavelength conversion structure can be formed individually from the LED, or can be formed in situ with the LED.

Examples of wavelength converting structures that are individually formed from an LED are ceramic wavelength converting structures that can be formed by sintering or any other suitable process, rolled, cast, or otherwise formed into a sheet, and then individual wavelength converted. Wavelength converting materials such as powder phosphors disposed in a transparent material such as silicon or glass that are singulated into structures, and a transparent material such as silicon formed from a flexible sheet that may be laminated or otherwise disposed over an LED And wavelength converting materials such as powdered phosphors disposed on.

Examples of wavelength converting structures formed in situ include wavelength converting materials such as powder phosphors mixed and dispensed with a transparent material such as silicon, screen printed, stenciled, molded, or otherwise disposed over an LED; And wavelength converting materials coated on the LED by electrophoretic, vapor phase, or any other suitable type of deposition.

Multiple types of wavelength converting structures can be used in a single device. As only one example, the ceramic wavelength converting member may be combined with the molded wavelength converting member, with the same or different wavelength converting materials present in the ceramic and molded members.

The wavelength conversion structure is, for example, conventional phosphors, organic phosphors, quantum dots, organic semiconductors, II-VI or III-V semiconductors, II-VI or III-V semiconductor quantum dots or nanocrystals, dye Materials, polymers, or other materials that emit light.

The wavelength converting material absorbs the light emitted by the LED and emits one or more different wavelengths of light. The unconverted light emitted by the LED is often part of the final spectrum extracted from the structure, but it is not required. Examples of common combinations include a blue emitting LED in combination with a yellow emission wavelength converting material, a blue emitting LED in combination with green and red emission wavelength converting materials, a UV emitting LED in combination with blue and yellow emission wavelength converting materials, and blue, green. , And a UV emitting LED in combination with red emitting wavelength converting materials. Wavelength converting materials that emit different colors of light can be added to adjust the spectrum of light extracted from the structure.

The embodiments described herein can be included with any suitable light emitting device. Embodiments of the invention are not limited to the specific structures illustrated.

Some features of some embodiments may be omitted or implemented in other embodiments. The device elements and method elements described herein are interchangeable and may be used or omitted in any of the examples or embodiments described herein.

In the examples and embodiments described above, the semiconductor light emitting device is a III-nitride LED that emits blue or UV light, but semiconductor light emitting devices other than LEDs, such as laser diodes, are within the scope of the invention. In addition, the principles described herein include semiconductor light emission or other material systems manufactured from other material systems such as other III-V materials, III-phosphide, III-arsenide, II-VI materials, ZnO, or Si-based materials. It may be applicable to other devices.

Having described the invention in detail, those skilled in the art will understand that, given the present disclosure, modifications may be made to the invention without departing from the spirit of the creative concepts described herein. Accordingly, it is not intended that the scope of the invention be limited to the specific embodiments illustrated and described.

Claims (15)

As a method for selectively growing a semiconductor structure,
Forming a plurality of sections of mask material on the surface;
Growing the semiconductor structure around a plurality of sections of the mask material to form at least one trench, the mask material remaining in the at least one trench; And
Annealing the semiconductor structure
How to include. The method of claim 1, wherein the semiconductor structure comprises at least one p-type region and at least one n-type region. 3. The method of claim 2, wherein the semiconductor structure further comprises at least one III-nitride emissive layer. The method of claim 1, wherein the mask material comprises an insulating material. The method of claim 1,
Prior to annealing the semiconductor structure, removing the plurality of sections of the mask material to expose a surface of the at least one trench. The method of claim 5,
After the step of annealing the semiconductor structure, the method further comprising filling the at least one trench with an insulating material. The method of claim 1,
Further comprising disposing a metal in the at least one trench, wherein the metal is in direct contact with a first portion of the semiconductor structure in the trench, and the mask material is a second portion of the semiconductor structure in the at least one trench. The method of being disposed between the part and the metal. The method of claim 1, wherein there are a plurality of trenches, and for each of the plurality of trenches there is a nearest neighbor trench. 9. The method of claim 8, wherein each of the plurality of trenches is surrounded by a portion of the semiconductor structure that is uninterrupted by each of the plurality of trenches. 9. The method of claim 8, wherein the closest neighboring trenches are spaced less than twice the maximum length of diffusion of hydrogen during annealing the semiconductor structure. The method of claim 1, wherein the semiconductor structure comprises a tunnel junction. 3. The method of claim 2, wherein the at least one trench comprises at least one embedded trench and the at least one embedded trench exposes at least a portion of the p-type region to the surrounding environment. 13. The method of claim 12, wherein the at least one trench is a lateral embedded trench. The method of claim 12, wherein the at least one trench is surrounded by at least one portion of the p-type region or the n-type region not interrupted by the at least one embedded trench. 13. The method of claim 12, further comprising growing tunnel junctions on the p-type region.

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