KR101879328B1 - Double split monotonic successive approximation register analog to digital converter - Google Patents

Abstract

The present invention relates to a dual-split monotonic successive approximation register analog to digital converter which comprises: a sample hold unit receiving a first input signal (V_ip) and a second input signal (V_in) as input signals in response to switching control by a successive approximation register (SAR) control logic to perform sample operation and hold operation; a capacitor array generating a first output signal and a second output signal as output voltage values, respectively in response to the first input signal and the second input signal during the period of the sample hold, wherein the capacitor array is formed in a two-tier structure for determining a high-order bit or a low-order bit by using two bridge capacitors (C_B1, C_B2); switches (S7, LSB_SW) interworking with the sample hold unit to determine the high-order bit or the low-order bit; a comparison unit comparing the size of the first output signal with that of the second output signal to output a digital value according to the result of the comparison; and a successive approximation register control logic outputting the final digital code value as a result signal in response to the digital value. According to the present invention, a combination of a dual-split form and a monotonic form is expected to have effects such as the decreased number of capacitors, enhanced energy efficiency, a realizable size of a capacitor, enhanced accuracy and the like.

Description

[0001] The present invention relates to a double split monotonic successive approximation register analog to digital converter

The present invention relates to an analog-to-digital converter, and more particularly to a dual-ended forged successive approximation analog-to-digital converter that combines separate techniques to reduce the number of capacitors in an energy efficient conventional forged consecutive analog-to-digital converter.

A conventional monotonic successive approximation register analog to digital converter (MSAR ADC) requires a number of capacitors of 2 ^N-1 per bit (N). Therefore, it requires 512 capacitors for 10 bits, and the design area increases greatly as 1 bit increases. However, it has the advantage of being more energy efficient than conventional successive approximation analog-to-digital converters.

Meanwhile, a conventional split-successive analog-to-digital converter (Split SAR ADC) is capable of high-resolution analog-to-digital conversion with a small number of capacitors through a bridge capacitance. However, since it is difficult to precisely control the size (capacitance size) of the bridge capacitor, there is a problem that the error in the lower bit area becomes larger. For example, in a 10-bit, discrete successive approximation analog-to-digital converter, setting the basic capacitor size to 100 fF results in a bridge capacitor ... fF, which is impossible to accurately implement in the present process. Therefore, the accuracy of the low-order bits is determined according to the process error range of the bridge capacitor, and a correction circuit must be added to improve the accuracy at the low-order bits.

Korean Patent Laid-Open Publication No. 2013-0045803 (Publication date 2013.05.06.), "Multi-bit successive approximation analog-to-digital conversion"

SUMMARY OF THE INVENTION It is therefore an object of the present invention to solve the problem of a separate type technique by combining a separate type technique in which the sizes of two additional bridge capacitors are implemented in a natural number, To-analog converters for analog to digital conversion.

According to an aspect of the present invention, there is provided a dual detached forged successive approximation analog-to-digital converter including a first approximation register (SAR) control logic for controlling a first input signal (V _ip ) A sample hold unit that receives the input signal V _in and performs a sample operation and a hold operation; And generates a first output signal and a second output signal, which are output voltage values corresponding to the first input signal and the second input signal, respectively, during the sample hold time, using two bridge capacitors (C _B1 , C _B2 ) A capacitor array in which a capacitor array for determining an upper bit or a lower bit is formed in a two-stage structure; A switch (S7, LSB_SW) interlocked with the sample hold section to determine the upper bit or the lower bit; A comparator for comparing the magnitudes of the first output signal and the second output signal and outputting a digital value according to a comparison result; And successive approximation register control logic for outputting the final digital code value as a result signal corresponding to the digital value.

At this time, the capacitor array includes an upper capacitor array and a lower capacitor array determined by the bridge capacitors (C _B1 , C _B2 ) and the switches (S7, LSB_SW). Each of the upper capacitor arrays and the lower capacitor arrays includes a first capacitor portion for determining upper bits, a second capacitor portion for determining a lower bit, and a second capacitor portion for determining an upper half of the intermediate capacitor connected in parallel between the first capacitor portion and the second capacitor portion. (MID). Each of the first capacitor portion and the second capacitor portion includes a plurality of capacitors connected in parallel, and the plurality of capacitors have one end connected to a reference voltage or a bottom switch grounded, and the other end connected to a comparator. Wherein the ratio of the first capacitor unit to the second capacitor unit is N: N, N: N-1, N: N-2, , And N: 1. Each of the bridge capacitors (C _B1 , C _B2 ) and the first capacitor portion and the second capacitor portion has a drain relation.

The switch S7 is connected at one end to the bridge capacitors C _B1 and C _B2 and the intermediate capacitor MID and is connected to the reference or ground at the upper bit and is opened at the lower bit, The switch LSB_SW has one end connected to the second capacitor, the other end connected to the reference or ground at the upper bit, and opened at the lower bit.

As described above, according to the present invention, the size of the added two bridge capacitors can be solved by solving the problem of the separate type technique, and at the same time, The total number of capacitors can be reduced, so that the energy efficiency can be improved and the design area can be reduced.

In addition, the size of the capacitor can be accurately implemented in the current process, and the accuracy can be improved without the need for an additional correction circuit.

That is, the present invention can reduce the number of capacitors, improve the energy efficiency, realize the capacitor size, and improve the accuracy by combining the dual separation type and the forging.

1 is a circuit diagram of a conventional forged successive approximation analog-to-digital converter.
2 is a waveform diagram illustrating the operation of a conventional monotonic successive approximation analog-to-digital converter.
3 is a circuit diagram of a conventional detachable successive approximation analog-to-digital converter.
4 is a circuit diagram of a dual detachable forged successive approximation analog-to-digital converter according to an embodiment of the present invention.
5 is a circuit diagram of a higher bit of the present invention.
6 is a waveform diagram of an upper bit operation of the present invention.
7 is a lower bit circuit diagram of the present invention.
FIGS. 8 to 11 are conceptual diagrams illustrating a process of changing a lower bit capacitor value and a voltage change of the present invention.
12 is a diagram for explaining the lower bit operation of the present invention.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT Hereinafter, the present invention will be described in detail with reference to preferred embodiments of the present invention and the accompanying drawings, wherein like reference numerals refer to like elements.

As described above, in the conventional forged successive approximation analog-to-digital converter, the number of capacitors increases with a bit increase, and the design area increases. On the other hand, in the separate-type successive approximation analog-to-digital converter, the size of the bridge capacitor can not be accurately implemented by the current process technology, and there is a problem that an error occurs in the lower bits according to the process error of the bridge capacitor.

In the present invention, by combining the double split method and the monotonic method, the values of the two bridge capacitors are made to be natural numbers, the energy efficiency is improved, and at the same time, the number of capacitors is reduced. That is, the present invention combines a double-split technique that can reduce the number of capacitors for a conventional energy-efficient forged consecutive analog-to-digital converter. By implementing the size of the two added bridge capacitors in a natural number, the problem of the separate type technique is solved and at the same time, the number of the whole capacitors of the forged consecutive analog-to-digital converter is also reduced. As a result, the energy efficiency can be improved and the design area can be reduced. In addition, the capacitor size can be accurately implemented in the current process, and the accuracy can be improved without the need for an additional correction circuit.

First, after explaining the existing technology, a description will be made of a dual-separated forged successive approximation analog-digital converter of the present invention.

1 is a circuit diagram of a conventional forged successive approximation analog-to-digital converter.

Referring to FIG. 1, a conventional forged successive approximation analog-to-digital converter is illustrated with 10 bits.

Conventional forged successive approximation analog digital converters consist of a comparator, a capacitor, and a sampling hold switch (SH). The bottom switches (D _p0 to D _p8 , D _n0 to D _n8 ) formed at one end of the capacitor are connected to V _REF or GND (ground). The capacitors have 256 (2 ^N-2 ) capacitors at the non-inverting terminal (+) and inverting terminal (-) of the comparator, respectively, and a total of 512 (2 ^N-1 ) capacitors of 10 bits are required. If you increase 1 bit here, that is, make 11 bits, a total of 1024 capacitors will be needed.

2 is a waveform diagram illustrating the operation of a conventional monotonic successive approximation analog-to-digital converter.

Referring to FIG. 2, bottom switches (D _p0 to D _p8 , D _n0 to D _n8 ) formed at one end of the capacitor during the sampling hold (SH) time are all connected to V _REF and inverted The terminals (-) are charged with V _{IN_P} and V _{IN_N} , respectively. After the noninverting terminal (+) and inverting terminal (-) of the comparator are charged, the comparator compares the two values and stores the result ('1') in D9. Since the voltage of the non-inverting terminal (+) of the comparator is larger than the voltage of the inverting terminal (-), the D _p8 switch is connected to GND and the voltage of the non-inverting terminal (+) of the comparator is V _REF / 2 . And the comparator compares the two values. As a result, D8 stores '1' because the voltage of the non-inverting terminal (+) of the comparator is larger than the voltage of the inverting terminal (-). The D _p7 switch is then connected to GND and the voltage at the non-inverting terminal (+) of the comparator is reduced by V _REF / 2 ² and the comparator compares the two values. Next, since the voltage of the non-inverting terminal (+) of the comparator is greater than the voltage of the inverting terminal (-), a value of '0' is stored in D ₇ , the D _n6 switch is connected to GND, -) is reduced by V _REF / 2 ³ . Calculate up to D0 in the same way. In this way, the voltage of the non-inverting terminal (+) or inverting terminal (-) of the comparator moves in one direction decreasing. This analog-to-digital converter is called a forged successive approximation analog-to-digital converter.

3 is a circuit diagram of a conventional detachable successive approximation analog-to-digital converter.

Referring to FIG. 3, a conventional discrete successive approximation analog-to-digital converter is illustrated with 10 bits.

In the conventional separable successive approximation analog-to-digital converter, 5 bits of the MSB and 5 bits of the LSB are separated into a bridge capacitance, and 5 bits (LSB) (D0-D4) and 5 bits (D5-D9) of the upper bits (MSB). At this time, the most important thing is the size (capacity size) of the bridge capacitor that separates the two regions. As shown in FIG. 1, the size of the total capacitors in the lower bit region viewed from the upper bit region should be 1C. When the size of the bridge capacitor is C _B ,

가 된다. 따라서 공정으로 정확히 구현하기가 불가능하며, 브릿지 커패시터의 공정오차에 따라 하위비트에서의 오차가 발생하게 된다.And,

. Therefore, it is impossible to accurately implement the process, and an error occurs in the lower bit according to the process error of the bridge capacitor.

4 is a circuit diagram of a dual detachable forged successive approximation analog-to-digital converter according to an embodiment of the present invention.

FIG. 4 shows only one side of a double split monotonic successive approximation register analog to digital converter connected to one terminal (non-inverting terminal or inverting terminal) of the comparator, Is connected to the other terminal. The circuit diagram of Fig. 4 shows a circuit diagram connected to the inverting terminal of the comparator.

Referring to FIG. 4, the dual-ended forged successive approximation analog-to-digital converter of the present invention includes a first approximation register (SAR) control logic, a first input signal V _ip A sample hold section (SH switch) SH for receiving a second input signal V _in and performing a sample operation and a hold operation, and a sample hold section A capacitor having a two-stage structure in which a capacitor array for generating a first output signal and a second output signal, which are output voltage values, and for determining an upper bit or a lower bit using two bridge capacitors C _B1 and C _B2 , A switch (S7, LSB_SW) interlocked with the sample hold section to determine the upper bit or the lower bit; and a comparator for comparing the magnitude of the first output signal with the magnitude of the second output signal, Comparison to output And a SAR control logic for outputting the final digital code value as a result signal corresponding to the digital value.

At this time, the capacitor array CA includes an upper capacitor array and a lower capacitor array determined by the bridge capacitors C _B1 , C _B2 and the switches S7, LSB_SW.

Each of the upper capacitor array and the lower capacitor array includes a first capacitor portion for determining the upper bit, a second capacitor portion for determining the lower bit, and an intermediate capacitor connected in parallel between the first capacitor portion and the second capacitor portion. (MID). In this case, each of the first capacitor portion and the second capacitor portion includes a plurality of capacitors connected in parallel, and the plurality of capacitors have one end connected to a reference voltage or a ground switch to be grounded, and the other end connected to a comparator (Comp).

For example, the first capacitor unit (upper bit) may be composed of six capacitors, and the second capacitor unit (lower bit) may be composed of three capacitors. At this time, the bridge capacitor C _B1 is 2 ³ C and the bridge capacitor C _B2 is 2 ² C. That is, the capacitance values of the bridge capacitors C _B1 and C _B2 are natural numbers. On the other hand, the ratio of the first capacitor unit to the second capacitor unit is N: N, N: N-1, N: N-2, , And N: 1 can be selected. At this time, each of the bridge capacitors (C _B1 , C _B2 ) and the first capacitor portion and the second capacitor portion has a drain relation. Therefore, the capacitance of the bridge capacitors C _B1 and C _B2 can be any one of natural numbers.

On the other hand, a switch (S7) is the one end is connected to the bridge capacitor (C _B1, C _B2) and an intermediate capacitor (MID), to be connected to the other end to a reference or ground on the high-order bit, is opened (OPEN) on the low-order bit, The switch LSB_SW is connected at one end to the second capacitor, and the other bit is connected to the reference or ground at the upper bit and is opened at the lower bit.

In the double separated forging successive approximation analog-to-digital converter of the present invention configured as described above, a portion for determining upper bits and a portion for determining lower bits are divided through two bridge capacitors (C _B1 and C _B2 ) and switches (S7 and LSB_SW) . When the S7 and LSB_SW switches are closed, they become successive approximate analog-to-digital converters that determine the upper bits. When the S7 and LSB_SW switches are opened, they become successive approximate analog-to-digital converters that determine the lower bits.

Hereinafter, the operation of the above-configured double separated forged successive approximation analog-to-digital converter will be described.

5 is a circuit diagram of a higher bit of the present invention.

Referring to FIG. 5, when the S7 switch and the LSB_SW switch in FIG. 4 are connected (closed) to V _REF or GND, a circuit diagram of the upper bit is obtained. The result is as shown in Fig. 5, which is a circuit diagram for determining the upper bits of the double detached forged successive approximation analog-to-digital converter.

6 is a waveform diagram of an upper bit operation of the present invention.

Referring to FIG. 6, when the SH switch is initially closed, <S _4p : S _9p > = <000000> and <S _4n : S _9n > = <000000> are all connected to V _REF . Then, the input voltages V _{IN_n} and V _{IN_p} are sampled on the capacitor top plate C_top. When the input voltage is sampled on the capacitor, only the SH switch is opened. Thereafter, the voltage of the non-inverting terminal (+) of the comparator (Comp) is compared with the voltage of the inverting terminal (-). Since the voltage of the non-inverting terminal (+) of the comparator (Comp) is larger than the voltage of the inverting terminal (-), <D _9p > = <1> The voltage decreases by V _REF / 2. <D _9n> = doeseo as connected to the V _REF <0>, inverting terminal of the comparator (Comp) (-) voltage is maintained. Then, since the voltage of the non-inverting terminal (+) of the comparator (Comp) is larger than the voltage of the inverting terminal (-), <D _8p > = <1> is connected to GND, (+) Voltage decreases by V _REF / 2 ² . <D _8n> = doeseo as connected to the V _REF <0>, inverting terminal of the comparator (Comp) (-) voltage is maintained. Next, since the voltage of the inverting terminal (-) of the comparator (Comp) is larger than the voltage of the non-inverting terminal (+), <D _7n > = <1> is connected to GND, -) decreases by V _REF / 2 ³ . _<7p D> = doeseo as connected to the V _REF <0>, the voltage of the comparator (Comp) a non-inverting terminal (+) of is maintained. In this way, the remaining bits are also determined. As a result, <D _4p : D _p9 > = <110010> and <D _4n : D _n9 > = <001101>. When the upper 6 bits are determined, both S _7n and S _7p are connected to OPEN.

7 is a lower bit circuit diagram of the present invention.

Referring to Fig. 7, when both the S7 switch and the SH switch are opened in Fig. 4, a circuit diagram of lower bits is obtained. The switches D ₉ , D ₈ , D ₇ , D ₆ , D ₅ , and D ₄ of the upper bits are connected to GND as a result of FIG. And the lower ₃ bits are determined according to the switch connection of the remaining D ₁ to D ₃ .

FIGS. 8 to 11 are conceptual diagrams illustrating a process of changing a lower bit capacitor value and a voltage change of the present invention.

과 같이 1/8 만큼 감소되어 넘어간다. 도 9에서는 MSB 커패시터와 C_B1의 커패시터 총합을 보여준다.

가 되고, 중간커패시터(MID)에서 커패시터 5C와 7C가 병렬연결이 된다. 도 10은 LSB에서 중간커패시터(MID)로 전압이 넘어가는 것을 설명하고 있다. 도 10은 앞서 도 9에서 5C와 7C가 12C로 합쳐진 회로도이다. 중간커패시터(MID)에 해당하는 커패시터의 총합은 12C이며 C_B2는 4C이다. 따라서 LSB에서 중간커패시터(MID)로 넘어가는 전압은

과 같이 1/4 만큼 감소되어 넘어간다. 도 11은 LSB의 전압변화를 설명하고 있다. 앞서 도 10의 4C와 12C가 직렬 연결되어 있으므로,

가 된다. D₂의 전압이

만큼 변할 경우 LSB의 상판의 전압은

가 된다. 따라서 D₁, D₂ 각각

,

만큼의 전압이 변하게 된다.Referring to FIGS. 8 to 11, the sum of the capacitors corresponding to MSB in FIG. 8 is 56C and C _B1 is 8C. Therefore, the voltage across the intermediate capacitor (MID)

As shown in FIG. 9 shows the sum of the capacitors of MSB and C _B1 .

And the capacitors 5C and 7C are connected in parallel in the intermediate capacitor MID. Figure 10 illustrates that the voltage goes from the LSB to the intermediate capacitor (MID). 10 is a circuit diagram in which 5C and 7C are combined to 12C in FIG. The sum of the capacitors corresponding to the intermediate capacitors (MID) is 12C and C _B2 is 4C. Therefore, the voltage across the LSB to the intermediate capacitor (MID)

As shown in FIG. 11 illustrates the voltage change of the LSB. Since 4C and 12C of Fig. 10 are connected in series,

. The voltage of D ₂

The voltage of the top plate of the LSB is

. Therefore, D ₁ and D ₂

,

Voltage is changed.

12 is a diagram for explaining the lower bit operation of the present invention.

만큼 변하게 된다. 그 후 브릿지 커패시터(C_B1, C_B2)에 의해서 전압이

,

만큼 감소하게 된다. 그 결과 LSB에서

만큼의 전압 변화가 MSB에서는

가 만들어지면서 하위비트 D₃가 결정된다. 그 후 D₂, D₁은 커패시터 값이 1/2 만큼 감소하기 때문에, 각각

,

이 만들어 진다. 따라서 하위비트 3비트가 결정된다. Referring to FIG. 12, when explaining the upper bits in FIG. 6, 7 bits of upper bits are determined up to V _REF / 2 ⁶ . Therefore, in the lower bit, if the determination is made from V _REF / 2 ⁷ to V _REF / 2 ⁹ , the lower 3 bits are determined. When the value of the lower bit D _{3 changes} from '1' to '0', the voltage changes by _{ΔV, and} the voltage of C _LSB becomes

. Then, the bridge capacitors (C _B1 , C _B2 )

,

. As a result,

In the MSB

And the lower bit D ₃ is determined. Since D ₂ and D ₁ then decrease the capacitor value by 1/2,

,

. Therefore, the lower 3 bits are determined.

The description of the disclosed embodiments is provided to enable any person skilled in the art to make or use the present invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without departing from the scope of the invention. Thus, the present invention is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features presented herein.

SH: Sample hold section (SH switch)
CA: capacitor array
Comp: Comparator

Claims (7)

A sample hold unit for receiving a first input signal V _ip and a second input signal V _{in as} input signals in response to a switching control by a consecutive approximation register (SAR) control logic and performing a sample operation and a hold operation; And generates a first output signal and a second output signal, which are output voltage values corresponding to the first input signal and the second input signal, respectively, during the sample hold time, using two bridge capacitors (C _B1 , C _B2 ) A capacitor array in which a capacitor array for determining an upper bit or a lower bit is formed in a two-stage structure; A switch (S7, LSB_SW) interlocked with the sample hold section to determine the upper bit or the lower bit; A comparator for comparing the magnitudes of the first output signal and the second output signal and outputting a digital value according to a comparison result; And successive approximation register control logic for outputting the final digital code value as a result signal corresponding to the digital value,
The capacitor array includes an upper capacitor array and a lower capacitor array determined by the bridge capacitors (C _B1 , C _B2 ) and the switches (S7, LSB_SW)
Each of the upper capacitor arrays and the lower capacitor arrays includes a first capacitor portion for determining upper bits, a second capacitor portion for determining a lower bit, and a second capacitor portion for determining an upper half of the intermediate capacitor connected in parallel between the first capacitor portion and the second capacitor portion. (MID)
The switch S7 is connected at one end to the bridge capacitors C _B1 and C _B2 and the intermediate capacitor MID and is connected to the reference or ground at the upper bit and opened at the lower bit,
The switch LSB_SW is connected at one end to the second capacitor unit, the other end connected to the reference or ground at the upper bit, and opened at the lower bit.
delete delete The method according to claim 1,
Wherein each of the first capacitor portion and the second capacitor portion includes a plurality of capacitors connected in parallel and the plurality of capacitors are connected to a reference switch or ground switch to which one end is connected and the other end is connected to a comparator, Digital converter.
5. The method of claim 4,
Wherein the ratio of the first capacitor unit to the second capacitor unit is N: N, N: N-1, N: N-2, , N: 1, respectively.
The method according to claim 1,
Wherein the bridge capacitors (C _B1 , C _B2 ) and the first capacitor portion and the second capacitor portion each have a drain relationship. delete

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