KR101392160B1 - Liquid crystal display device - Google Patents

Abstract

The present invention relates to a liquid crystal display device. A liquid crystal display device according to the present invention includes a first substrate having a display region, a second substrate facing the first substrate, and a liquid crystal layer disposed between the first substrate and the second substrate, 1 substrate includes: a gate main line positioned within the display area; A gate pad located outside the display region; And a resistance portion electrically connected to the gate main line and the gate pad and made of a material having a higher resistance than the gate main line. Thereby, a luminance unevenness due to a difference in gate signal delay is reduced, is provided.

Description

[0001] LIQUID CRYSTAL DISPLAY DEVICE [0002]

1 is a layout diagram of a first substrate in a liquid crystal display device according to a first embodiment of the present invention,

Fig. 2 is an enlarged view of a portion A in Fig. 1,

3 is a cross-sectional view taken along the line III-III in Fig. 2,

4 is a graph showing the transmittance according to the pixel voltage in the liquid crystal display according to the first embodiment of the present invention,

5 is an equivalent circuit diagram of a pixel in the liquid crystal display device according to the first embodiment of the present invention,

6A to 6C are diagrams for explaining luminance unevenness due to gate signal delay,

7 is an enlarged view of a portion B in Fig. 1,

8 is a cross-sectional view taken along line VIII-VIII of FIG. 7,

FIG. 9 is a view for explaining improvement in luminance unevenness in the liquid crystal display device according to the first embodiment of the present invention,

10 is a diagram showing the relationship between the gate signal delay and the luminance,

11 is a diagram showing a change in parasitic capacitance and luminance,

12 is a view showing a gate signal delay according to the resistance value of the resistance portion,

13 is a diagram showing a pixel voltage according to a resistance value of a resistance portion,

FIG. 14 is a view for explaining a liquid crystal display according to a second embodiment of the present invention, and FIG.

Fig. 15 is a sectional view taken along the line XV-XV in Fig. 14,

16 is an equivalent circuit diagram of a pixel in a liquid crystal display device according to the third embodiment of the present invention,

17 shows the principle of improving the visibility in the liquid crystal display device according to the third embodiment of the present invention

18 is a layout diagram of a liquid crystal display device according to the third embodiment of the present invention,

19 is a layout diagram of a liquid crystal display device according to a fourth embodiment of the present invention.

Description of Reference Numerals of Major Parts of the Drawings [

121: gate line 122: gate electrode

123: fan-out portion 124: gate pad

131: gate insulating film 151: protective film

161: pixel electrode 166: pixel electrode cut-out pattern

163: Resistor part 200: Second substrate

251: common electrode 252: common electrode incision pattern

300: Sealant

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display, and more particularly, to a liquid crystal display having improved luminance uniformity by reducing gate signal delay.

A liquid crystal display device includes a first substrate on which a thin film transistor is formed, a second substrate opposed to the first substrate, and a liquid crystal layer interposed between the first substrate and the second substrate.

A gate line and a data line provided on a thin film transistor substrate intersect each other to form pixels, and each pixel is connected to a thin film transistor. When a gate signal (gate on voltage Von) is applied to the gate line and the thin film transistor is turned on, the data voltage Vd applied through the data line is charged in the pixel.

The alignment state of the liquid crystal layer is determined according to the electric field formed between the pixel voltage Vp charged in the pixel and the common voltage Vcom formed at the common electrode of the second substrate. The data voltage Vd is applied with a different polarity for each frame.

The data voltage Vd applied to the pixel is lowered by the parasitic capacitance Cp between the gate electrode and the source electrode (drain electrode) to form the pixel voltage Vp. The voltage difference between the data voltage Vd and the pixel voltage Vp is referred to as a kickback voltage Vkb.

The gate line receives a gate signal through a gate pad connected to the end. A gate signal having a small delay is applied to the pixel adjacent to the gate pad and a gate signal having a large delay due to the resistance of the gate line is applied to the pixel distant from the gate pad.

However, the size of the kickback voltage varies depending on the degree of delay of the gate signal, and the pixel voltage varies due to the change of the kickback voltage, resulting in a problem that the brightness of the screen becomes uneven.

SUMMARY OF THE INVENTION Accordingly, it is an object of the present invention to provide a liquid crystal display device in which luminance unevenness due to gate signal delay difference is reduced.

It is an object of the present invention to provide a liquid crystal display device including a first substrate having a display region, a second substrate facing the first substrate, and a liquid crystal layer positioned between the first substrate and the second substrate The first substrate includes: a gate main line positioned in the display area; A gate pad located outside the display region; And a resistance portion electrically connected to the gate main line and the gate pad and made of a material having a higher resistance than the gate main line.

The first substrate includes a thin film transistor connected to the gate main line; And a pixel electrode electrically connected to the thin film transistor.

It is preferable that the resistance portion is formed of the same material as the pixel electrode.

The resistor may include indium tin oxide (ITO) or indium zinc oxide (IZO).

The resistive part preferably has a smaller resistance value as the distance between the gate main line and the gate pad is larger.

And a fan-out unit positioned between the gate pad and the resistor unit.

The gate main line, the gate pad, and the fan-out portion are preferably formed in the same layer.

And a sealant that is formed on the fan-out portion and couples the first substrate and the second substrate.

And a fan-out unit positioned between the gate pad and the resistor unit.

The gate pad, the fan-out portion, and the resistor portion may be formed of the same layer.

It is preferable that at least a part of the resistance portion is formed in a zigzag shape.

Preferably, the liquid crystal layer is in a vertical alignment (VA) mode.

It is preferable that the pixel electrode includes a pixel electrode cut-out pattern, and the second substrate includes a common electrode on which a common electrode cut-out pattern is formed.

The pixel electrode may include a first pixel electrode and a second pixel electrode that are separated from each other, and a different pixel voltage may be applied to the first pixel electrode and the second pixel electrode.

The thin film transistor includes a drain electrode, and the drain electrode includes a first drain electrode for applying a data voltage directly to the first pixel electrode, and a second drain electrode for forming a coupling capacitance with the second pixel electrode desirable.

The thin film transistor may include a first thin film transistor connected to the first pixel electrode and a second thin film transistor connected to the second pixel electrode.

It is preferable that the total resistance of the resistance portion is 10% to 50% of the total resistance of the gate main line.

It is preferable that the change of the gate signal delay of the gate main line is made within 100%.

It is an object of the present invention to provide a liquid crystal display device including a first substrate having a display region, a second substrate facing the first substrate, and a liquid crystal layer positioned between the first substrate and the second substrate Wherein the first substrate includes: a gate main line positioned within the display area; A gate pad located outside the display region; A resistor part electrically connected to the gate main line and the gate pad and made of a material having a higher resistance than the gate main line; A thin film transistor connected to the gate main line; And a pixel electrode electrically connected to the thin film transistor and made of the same material as the resistance portion, wherein the liquid crystal layer is in a VA mode.

The above object of the present invention can be achieved by a display device comprising a substrate having a display area and a non-display area, a gate main line positioned in the display area, A gate pad located outside the display region; A resistor part electrically connected to the gate line and the gate pad and made of a material having a higher resistance than the gate line; A thin film transistor connected to the gate main line; And a thin film transistor array substrate including a pixel electrode electrically connected to the thin film transistor and made of the same material as the resistance portion.

BRIEF DESCRIPTION OF THE DRAWINGS The invention will now be described in more detail with reference to the accompanying drawings, in which: FIG. Hereinafter, the fact that a certain film (layer) is formed (positioned) on another film (layer) means that not only when both films (layer) are in contact but also when another film And the case where it exists.

A liquid crystal display according to the present invention will be described with reference to FIGS. 1 to 3. FIG.

The liquid crystal display device 1 includes a first substrate 100 on which a thin film transistor T is formed, a second substrate 200 opposed to the first substrate 100, And a sealant 400 for bonding the liquid crystal layer 300 and both substrates 100 and 200 to each other.

The first substrate 100 is divided into a display region and a non-display region surrounding the display region. The gate line 121 of the display area is connected to the gate pad 124 through the fan-out part 123 of the non-display area.

First, the first substrate 100 will be described.

Gate wirings are formed on the first insulating substrate 111. The gate wiring may be a single metal layer or multiple layers. The gate wiring line includes a gate main line 121 located in the display region and extending in the horizontal direction, a gate electrode 122 connected to the gate main line 121, a fan-out portion extending from the gate main line 121 to the non- A gate pad 124 connected to the end of the pixel portion 123 and the fan-out portion 123, and a sustain electrode line 125 extending parallel to the gate line 121.

The gate pad 124 is connected to a gate driver (not shown) and receives a gate signal. The width of the gate pad 124 is larger than that of the gate main line 121.

On the first insulating substrate 111, a gate insulating film 131 made of silicon nitride (SiNx) covers the gate wiring.

A semiconductor layer 132 made of a semiconductor such as amorphous silicon is formed on the gate insulating layer 131 of the gate electrode 122. An n + An ohmic contact layer 133 made of a material such as hydrogenated amorphous silicon is formed. In the channel portion between the source electrode 142 and the drain electrode 143, the ohmic contact layer 133 is removed.

Data wirings are formed on the ohmic contact layer 133 and the gate insulating film 131. The data lines may also be a single layer or multiple layers of metal layers. The data line includes a data line 141 formed in the vertical direction and intersecting the gate line 121 to form a pixel, a source electrode 142 extending from the branch of the data line 141 to the upper portion of the ohmic contact layer 133 A drain electrode 143 separated from the source electrode 142 and formed on the ohmic contact layer 133 on the opposite side of the source electrode 142, a drain electrode 143 formed on the data electrode 141, And a data pad 145 connected to the end of the fan-out portion 144 and the fan-out portion 144.

The data pad 145 is connected to a data driver (not shown) and receives a data driving signal. The data pad 145 has a width larger than that of the data main line 141.

A protective film 151 is formed on the data line and the semiconductor layer 132 not covered with the data line. A contact hole 152 for exposing the drain electrode 143 is formed in the protection film 151. [ 7 and 8, contact holes 153, 154 and 155 are further formed in the passivation layer 151, and the gate insulating layer 131 is also removed therefrom.

A pixel electrode 161 is formed on the protective film 151. The pixel electrode 161 is typically made of a transparent conductive material such as ITO (indium tin oxide) or IZO (indium zinc oxide). The pixel electrode 161 is connected to the drain electrode 143 through the contact hole 152. A pixel electrode cutout pattern 166 is formed on the pixel electrode 161. [

The pixel electrode cutout pattern 166 of the pixel electrode 161 divides the liquid crystal layer 300 into a plurality of regions together with a common electrode cutout pattern 252 to be described later.

Next, the second substrate 200 will be described.

A black matrix 221 is formed on the second insulating substrate 211. The black matrix 221 generally separates the red, green, and blue filters and serves to block direct light irradiation to the thin film transistors located on the first substrate 100. The black matrix 221 is usually made of a photosensitive organic material to which a black pigment is added. As the black pigment, carbon black, titanium oxide, or the like is used.

The color filter 231 is formed by repeating red, green, and blue filters with the black matrix 221 as a boundary. The color filter 231 irradiates light from the backlight unit (not shown) and imparts hue to light passing through the liquid crystal layer 300. The color filter 231 is usually made of a photosensitive organic material.

An overcoat layer 241 is formed on the upper portion of the black matrix 221 on which the color filter 231 and the color filter 231 are not covered. The overcoat layer 241 serves to protect the color filter 231 while flattening the color filter 231. The overcoat layer 241 may be a photosensitive acrylic resin.

A common electrode 251 is formed on the overcoat layer 241. The common electrode 251 is made of a transparent conductive material such as ITO (indium tin oxide) or IZO (indium zinc oxide). The common electrode 251 applies a voltage directly to the liquid crystal layer 300 together with the pixel electrode 161 of the thin film transistor substrate.

A common electrode cutout pattern 252 is formed in the common electrode 251. The common electrode cutout pattern 252 serves to divide the liquid crystal layer 300 into a plurality of regions together with the pixel electrode cutout pattern 166 of the pixel electrode 161. The pixel electrode cut-out pattern 166 and the common electrode cut-out pattern 252 are not limited to the embodiment and may be formed in various shapes. In another embodiment, protrusions may be provided instead of the cut-out patterns 166 and 252 to divide the liquid crystal layer 300 into a plurality of regions.

A liquid crystal layer 300 is positioned between the first substrate 100 and the second substrate 200. The liquid crystal layer 300 is a VA (Vertically Aligned) mode, and the longitudinal direction of the liquid crystal molecules is vertical when no voltage is applied. When the voltage is applied, the liquid crystal molecules lie in the vertical direction with respect to the electric field because the dielectric anisotropy is negative.

If the cutting patterns 166 and 252 are not formed, the liquid crystal molecules are disorderly arranged in various directions because the lying azimuth is not determined, and a disclination line is generated at a boundary surface having a different alignment direction. Cutting patterns 166 and 252 create a fringe field when a voltage is applied to the liquid crystal layer 300 to determine the azimuth angle of the liquid crystal alignment. In addition, the liquid crystal layer 300 is divided into multiple regions according to the disposition of the dissection patterns 166 and 252.

The liquid crystal display device 1 according to the first embodiment is a normally black mode, and the transmittance according to the pixel voltage is shown in Fig. The change in the transmittance at the low gradation shown in part C of FIG. 4 is about three times as rapid as that of the TN (twisted nematic) liquid crystal.

In the liquid crystal display 1 described above, the gate main line 121 receives a gate signal through the gate pad 124 connected to the end. A gate signal having a small delay is applied to the thin film transistor T adjacent to the gate pad 124 by the resistance of the gate main line 121, that is, the thin film transistor T on the left side. On the other hand, a gate signal with a large delay is applied to the thin film transistor T, that is, the thin film transistor T on the right side, which is distant from the gate pad 123.

The change of the screen brightness according to the difference of the gate signal delay will be described with reference to Figs. 5 to 6C.

The kickback voltage Vkb is expressed by Equation 1 as follows.

Equation 1

Vkb = (Von-Voff) * Cp / (Clc + Cst + Cp)

3 and 5, Cp denotes parasitic capacitance (Cgs) between the gate electrode and the source electrode, parasitic capacitance (Cgd) between the gate electrode and the drain electrode, Clc denotes the liquid crystal capacitance, Cst denotes the storage capacitance, , And Voff represents a gate-off voltage.

If the delay of the gate signal is large, the gate-on voltage is poor and the kickback voltage becomes small. The kickback voltage becomes larger when the negative pixel voltage is applied than when the positive pixel voltage is applied.

6A and 6B show a kickback voltage for a pixel on the left side of the display area with a small delay of the gate signal and a pixel on the right side of the display area where the delay of the gate signal is large.

In the case of the left pixel shown in FIG. 6A, the kickback voltage is 1 V when the positive pixel voltage is applied, and the kickback voltage is 1.2 V when the negative pixel voltage is applied. In the case of the right pixel shown in Fig. 8B, the kickback voltage is 0.8 V both when the positive pixel voltage is applied and when the negative pixel voltage is applied.

Accordingly, the root mean square pixel voltage at which the left pixel finally remains in the pixel is larger, and the portion corresponding to the left pixel is recognized as brighter at the screen.

Referring to FIG. 6C, the gate signal delay is smaller and the kickback voltage Vkb becomes larger toward the gate pad 124. On the other hand, the gate signal delay becomes larger and the kickback voltage Vkb becomes smaller as the distance from the gate pad 124 increases. Therefore, the pixel of the left side is larger than the pixel of the right side (average root mean square).

As described above, there is a problem that the luminance of the left and right sides of the screen is changed and the horizontal line is recognized accordingly. Such a problem becomes more serious in a large-sized liquid crystal display device in which the gate main line 121 is long and gate signal delay is large.

In the first embodiment of the present invention, the problem caused by the gate delay difference is solved by forming the resistor portion 163 between the gate main line 121 and the gate pad 124. [

The resistance portion 163 will be described with reference to Figs.

The resistor portion 163 is located between the fan-out portion 123 and the gate main line 121 in the non-display area. The resistance portion 163 is formed of the same layer as the pixel electrode 161 and includes a first portion 163a connected to the fan-out portion 123, a second portion 163b connected to the gate main line 121, And a third portion 163c positioned between the first portion 163a and the second portion 163b

The first portion 163a contacts the fan-out portion 123 through the contact hole 154 and the second portion 163b contacts the gate main line 21 through the contact hole 155. [

The gate pad 124 exposed by the contact hole 153 is covered with a contact member 162 made of the same layer as the pixel electrode 161.

The resistance portion 163 is made of ITO, IZO or the like, and these materials have a larger resistance than the metal material constituting the gate main line 121. The gate signal is already delayed by the resistance portion 163 having a large resistance as shown in Fig. 9 before entering the display region.

Therefore, the delay variation width of the gate signal and the variation width of the kickback voltage (Vkb) decrease. The luminance difference between the right and left of the display area also decreases.

The total resistance of the gate main line 121 is generally 4000? To 7000?, And the total resistance of the resistance portion 163 may be 10% to 50% of the total resistance of the gate main line 121. [ The resistance value of the resistance portion 163 can be changed by adjusting the thickness, width, and length of the resistance portion 163.

It is preferable that the resistance value of the resistance portion 163 is determined such that the gate delay variation changes within 100%, that is, the gate delay value of the rightmost pixel of the display region is within two times the gate delay value of the leftmost pixel of the display region Do.

On the other hand, the distance between the gate main line 121 and the gate pad 124 varies, which causes a problem that the resistance between the gate main line 121 and the gate pad 124 is varied to change the brightness.

The length of the third portion 163c of the resistor portion 163 is inversely proportional to the distance between the gate line 121 and the gate pad 124. [ Thus, unevenness in luminance due to the difference in distance between the gate main line 121 and the gate pad 124 is reduced.

The sealant 400 is positioned on the fan-out portion 123 and the resistor portion 163 is located in the sealant 400. [ There is no problem that the resistance portion 163 is corroded because the resistance portion 163 is not exposed to the outside.

In the manufacturing process, a static electricity introduced from the outside may damage the thin film transistor T or the like. According to the first embodiment, the static electricity introduced through the gate pad 124 is partially eliminated in the resistance portion 163 having a high resistance, and the problem caused by the static electricity is reduced.

In another embodiment, the resistance portion 163 may be made of another material having a higher resistance than the gate main line 121, apart from the pixel electrode 161. [ In another embodiment, the resistive portion 163 is all the same in shape, and the difference in distance between the gate main line 121 and the gate pad 124 can be solved by changing the shape of the fan-out portion 123.

Hereinafter, the reason why the gate signal delay is adjusted to control the luminance unevenness will be described.

10 shows the luminance deviation rate according to the gate signal delay value in the display area. The luminance deviation rate (luminance at the left side of the display area - luminance at the center part of the display area) / luminance at the center part of the display area * 100.

Referring to FIG. 10, when the gate signal delay value increases by about 43% (3.67 μs at 2.55 μs), the luminance deviation rate increases by about 64% (30.6% to 50.3%).

FIG. 11 shows the luminance deviation rate according to Cp / (Clc + Cst + Cp) proportional to the kickback voltage. 11, when the Cp / (Clc + Cst + Cp) is increased by 24% (0.037 to 0.046), the luminance deviation rate increases by about 26.4% (35.6% to 45%).

It can be seen from FIG. 10 and FIG. 11 that it is effective to adjust the gate signal delay value in order to improve the luminance unevenness.

The gate signal delay and the pixel voltage are changed by the resistance in the non-display area, that is, the resistance from the gate pad to the gate main line, which will be described with reference to FIGS. 12 and 13. FIG.

In FIGS. 12 and 13, the resistance in the non-display region has four values of 1/6 k ?, 1/3 k ?, 1/2 k ?, and 2/3 k ?. The data indicated by 0 k? Is the case where there is no resistance portion and the gate main line and the gate pad are formed integrally.

12, it can be seen that the gate signal delay value increases as the resistance of the non-display region increases. On the other hand, as the non-display area resistance increases, the right gate signal delay value / left gate signal delay value decreases.

That is, in the case of 0 kΩ, the right gate signal delay value / left gate signal delay value is 6.53 (4.18 / 0.64), whereas in case of 2/3 kΩ, the right gate signal delay value / left gate signal delay value is 1.77 (8.12 / 4.57).

As shown in FIG. 13, as the non-display area resistance increases, the pixel voltage decreases as a whole. On the other hand, the larger the resistance of the resistor, the lower the left pixel voltage / the right pixel voltage. That is, in the case of 0 kΩ, the left pixel voltage / the right pixel voltage is 1.028 (3.3 / 3.21), whereas in the case of 2/3 kΩ, the left pixel voltage / right pixel voltage is 1.012 (3.19 / 3.15).

It can be seen from FIG. 12 and FIG. 13 that by increasing the non-display area resistance, the difference between the gate signal delay and the pixel display voltage in the left display area and the right display area can be reduced. However, when the non-display area resistance becomes large, the gate signal transfer becomes difficult. Therefore, the non-display area resistance should be determined in consideration of the total resistance of the gate main line 121 and the like.

The second embodiment will be described below with reference to Figs. 14 and 15. Fig.

According to the second embodiment, the gate pad 164 and the fan-out portion 165 are integrally formed with the resistor portion 163 and made of ITO or IZO. The resistance portion 163 is connected to the gate main line 121 through the contact hole 156. [ In the second embodiment, the gate pad 164 and the fan-out portion 165 also function as the resistor 163 of the first embodiment.

The resistance portion 163 is provided in inverse proportion to the distance between the gate line 121 and the gate pad 164 as in the first embodiment. Thus, unevenness in luminance due to the difference in distance between the gate main line 121 and the gate pad 164 is reduced

In another embodiment, without the resistor 163, only the fan-out portion 165 can be made of ITO or IZO to delay the gate signal.

The third embodiment will be described with reference to Figs. 16 to 18. Fig.

16, two liquid crystal capacitors C _LC1 and C _LC2 are connected to the thin film transistor T. In FIG. The first liquid crystal capacitance C _{LC1 is} formed between the first pixel electrode PE1 and the common electrode CE and the first pixel electrode PE1 is directly connected to the thin film transistor T. The second liquid crystal capacitance C _{LC2 is} formed between the second pixel electrode PE2 and the common electrode CE and the second pixel electrode PE2 is indirectly connected to the thin film transistor T through the coupling capacitance C _CP . .

Here, the first pixel electrode PE1 and the second pixel electrode PE2 are separated from each other.

According to the third embodiment, visibility is improved, which will be described with reference to FIG.

The data signal is normally applied to the first pixel electrode PE1 through the thin film transistor T. [ On the other hand, the second pixel electrode PE2 does not receive a data signal directly from the thin film transistor T, and the coupling capacitance C _CP generated by the insulating film between the second pixel electrode PE2 and the thin film transistor T The signal is applied by the induced voltage.

Therefore, a weaker signal is applied to the second pixel electrode PE2 than the first pixel electrode PE1, and the brightness of the pixel region corresponding to the first pixel electrode PE1 and the brightness of the pixel electrode PE2 corresponding to the second pixel electrode PE2 The luminance of the pixel region becomes different. The voltage applied to the second pixel electrode PE2 is 50% to 90% of the voltage applied to the first pixel electrode PE1.

In this manner, a plurality of regions having different gamma curves exist in one pixel. This improves the lateral visibility by compensating the luminance and the color of the front and the side.

Referring to FIG. 18, the pixel electrode 161 includes a first pixel electrode 161a and a second pixel electrode 161b separated from each other by a pixel electrode isolation pattern 167. The second pixel electrode 161b is a trapezoid, and three surfaces are surrounded by the first pixel electrode 161a. A pixel electrode cutout pattern 166 is formed on the first pixel electrode 161a and the second pixel electrode 161b in parallel with the pixel electrode cutout pattern 167, respectively.

The drain electrode 143 is connected to the first pixel electrode 161a and includes a first drain electrode 143a that applies an electric signal directly to the first pixel electrode 161a and a second drain electrode 143b that extends below the second pixel electrode 161b And a second drain electrode 143b. The second drain electrode 143b forms a coupling capacitance Ccp together with the second pixel electrode 161b.

The pixel electrode separation pattern 167 and the pixel electrode cutout pattern 166 divide the liquid crystal layer 300 into a plurality of regions together with the common electrode cutout pattern 252.

The sustain electrode lines 125 are formed along the periphery of the pixel electrodes 161 and the sustain electrode lines 125 at the upper and lower portions are connected to each other through the contact holes 157 and the bridge electrodes 168.

A fourth embodiment of the present invention will be described with reference to Fig.

The pixel electrode 161 is entirely formed in a rectangular shape and is elongated in the extending direction of the data line 141. The pixel electrode 161 has a vertically symmetrical shape.

The pixel electrode 161 includes a first pixel electrode 161a and a second pixel electrode 161b which are separated from each other by a pixel electrode isolation pattern 167. [ The first pixel electrode 161a is located at the center of the pixel and has a cantilever shape. The second pixel electrode 161b surrounds the first, the second, and the bottom of the first pixel electrode 161a. The second pixel electrode 161b is formed wider than the first pixel electrode 161a.

The thin film transistor T includes a first thin film transistor TFT1 connected to the first pixel electrode 161a and a second thin film transistor TFT2 connected to the second pixel electrode 161b.

The drain electrode 143 of each of the thin film transistors TFT1 and TFT2 overlaps the pixel electrode 161 to form a storage capacitor Cst and the storage capacitor is connected to the drain electrode 143 and the pixel electrode 161 It is proportional to the overlap area.

In the fourth embodiment, different pixel voltages can be applied to the pixel electrodes 161a and 161b by using the independent thin film transistors TFT1 and TFT2. The principle of improving the visibility in the fourth embodiment is the same as that in the third embodiment, and repeated explanation is omitted.

In the third and fourth embodiments described above, the structure of the non-display region follows the first embodiment or the second embodiment.

In the third and fourth embodiments, the pixel electrode 161 is divided so that the liquid crystal capacitance Clc and the storage capacitance Cst are small. As a result, the kickback voltage Vkb increases (see Equation 1), and the luminance difference becomes more problematic. Therefore, in the third and fourth embodiments, it is necessary to further equalize the gate signal delay using the resistor portion.

Although the embodiments of the present invention have been shown and described, those skilled in the art will appreciate that various modifications, additions and substitutions are possible, without departing from the scope or spirit of this invention. The scope of the present invention shall be determined by the appended claims and their equivalents.

INDUSTRIAL APPLICABILITY As described above, according to the present invention, a liquid crystal display device in which luminance unevenness due to a gate signal delay difference is reduced is provided.

Claims (20)

A liquid crystal display comprising a first substrate having a display region, a second substrate facing the first substrate, and a liquid crystal layer interposed between the first substrate and the second substrate, Wherein the first substrate comprises: A gate main line positioned within the display area; A gate pad located outside the display region; And a resistance portion electrically connected to the gate main line and the gate pad and made of a material having a higher resistance than the gate main line, The resistor portion includes a first portion connected to the gate pad, a second portion connected to the gate main line, and a third portion positioned between the first portion and the second portion, Wherein a length of the third portion is inversely proportional to a distance between the gate main line and the gate pad. The method according to claim 1, Wherein the first substrate comprises: A thin film transistor connected to the gate main line; And a pixel electrode electrically connected to the thin film transistor. 3. The method of claim 2, Wherein the resistance portion is formed of the same material as the pixel electrode. The method of claim 3, Wherein the resistance portion includes indium tin oxide (ITO) or indium zinc oxide (IZO). The method according to claim 1, Wherein a resistance value of the resistor unit is smaller as the distance between the gate main line and the gate pad is longer. The method according to claim 1, Further comprising a fan-out unit positioned between the gate pad and the resistor unit. The method according to claim 6, Wherein the gate main line, the gate pad, and the fan-out portion are formed in the same layer. The method according to claim 6, Further comprising a sealant formed on the fan-out unit and coupling the first substrate and the second substrate. delete The method according to claim 6, Wherein the gate pad, the fan-out portion, and the resistor portion are formed of the same layer. The method according to claim 1, And at least a part of the resistance portion is formed in a zigzag shape. 3. The method of claim 2, Wherein the liquid crystal layer is in a vertical alignment (VA) mode. 13. The method of claim 12, The pixel electrode is formed with a pixel electrode cut-out pattern, Wherein the second substrate includes a common electrode on which a common electrode cutout pattern is formed. 14. The method of claim 13, Wherein the pixel electrode includes a first pixel electrode and a second pixel electrode that are separated from each other and different pixel voltages are applied to the first pixel electrode and the second pixel electrode. 15. The method of claim 14, The thin film transistor includes a drain electrode, Wherein the drain electrode comprises a first drain electrode for applying a data voltage directly to the first pixel electrode, and a second drain electrode for forming a coupling capacitance with the second pixel electrode. 15. The method of claim 14, Wherein the thin film transistor includes a first thin film transistor connected to the first pixel electrode and a second thin film transistor connected to the second pixel electrode. The method according to claim 1, Wherein a total resistance of the resistance portion is 10% to 50% of a total resistance of the gate main line. The method according to claim 1, And the change of the gate signal delay of the gate main line is within 100%. A liquid crystal display comprising a first substrate having a display region, a second substrate facing the first substrate, and a liquid crystal layer interposed between the first substrate and the second substrate, Wherein the first substrate comprises: A gate main line positioned within the display area; A gate pad located outside the display region; A resistor part electrically connected to the gate main line and the gate pad and made of a material having a higher resistance than the gate main line; A thin film transistor connected to the gate main line; And a pixel electrode electrically connected to the thin film transistor and made of the same material as the resistance portion, The liquid crystal layer is in a VA mode, The resistor portion includes a first portion connected to the gate pad, a second portion connected to the gate main line, and a third portion positioned between the first portion and the second portion, Wherein a length of the third portion is inversely proportional to a distance between the gate main line and the gate pad. A substrate having a display area and a non-display area, A gate main line positioned within the display area; A gate pad located outside the display region; A resistor part electrically connected to the gate main line and the gate pad and made of a material having a higher resistance than the gate main line; A thin film transistor connected to the gate main line; And a pixel electrode electrically connected to the thin film transistor and made of the same material as the resistance portion, The resistor portion includes a first portion connected to the gate pad, a second portion connected to the gate main line, and a third portion positioned between the first portion and the second portion, Wherein a length of the third portion is inversely proportional to a distance between the gate main line and the gate pad.

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