KR101174776B1 - Thin Film Transistor Array Substrate And Method For Fabricating The Same - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a TFT array substrate and a method of manufacturing the same, in which a transparent semiconductor film is applied to a TFT to improve aperture ratio and to reduce a process time and a unit cost by forming a thin film transistor array substrate with three masks. A thin film transistor including a gate wiring and a data wiring defining a gate wiring, a thin film transistor formed at an intersection of the two wirings, and including a transparent semiconductor film, a pixel electrode integrally extending from a drain electrode of the thin film transistor, and a front surface including the thin film transistor. And a passivation layer formed at the gate, a gate pad electrode extending from the gate wiring, and a data pad electrode extending from the data wiring.

Low Mask, Transparent Semiconductor Film, ZnO

Description

TFT Film Substrate and Method for Manufacturing the Same {Thin Film Transistor Array Substrate And Method For Fabricating The Same}

1A to 1E are process cross-sectional views of a TFT array substrate according to the prior art.

2 is a plan view of a TFT array substrate according to a first embodiment of the present invention.

3 is a cross-sectional view of the TFT array substrate according to the first embodiment of the present invention.

4A to 4D are cross-sectional views of a TFT array substrate according to a first embodiment of the present invention.

5 is a plan view of a TFT array substrate according to a second embodiment of the present invention.

6 is a cross-sectional view of the TFT array substrate according to the second embodiment of the present invention.

7A to 7D are cross-sectional views of a TFT array substrate according to a second embodiment of the present invention.

* Explanation of symbols on the main parts of the drawings

101 metal layer 102 first transparent conductive film

103: transparent semiconductor film 104: second transparent conductive film

111: substrate 112: gate wiring

112a: gate electrode 113: gate insulating film

114: semiconductor layer 115: data wiring

115a: source electrode 115b: data electrode

116: protective film 117: pixel electrode

122: gate pad electrode 125: data pad electrode

132: storage electrode

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display device (LCD), and in particular, to improve the aperture ratio by applying a transparent semiconductor film to the TFT and to form a thin film transistor array substrate with three masks to reduce process time and process cost. An array substrate and a method of manufacturing the same.

Liquid crystal display devices have a high contrast ratio, are suitable for gray scale display and moving image display, and have low power consumption.

The liquid crystal display device forms various patterns such as a driving device or a wiring on a substrate to perform an operation, and photolithography is a common technique used to form a pattern.

In the photolithography technique, a photoresist, which is a material that is photosensitive with ultraviolet rays, is coated on a film layer on a substrate on which a pattern is to be formed, and the pattern formed on the exposure mask is exposed on the photoresist as it is, and developed. Leveraging the film layer and then stripping the photoresist is a series of complex processes.

The TFT array substrate for a liquid crystal display device according to the prior art generally uses 5 to 7 mask techniques to form a gate wiring layer, a gate insulating film, a semiconductor layer, a data wiring layer, a protective film, and a pixel electrode on the substrate. As the number of photo etching techniques used increases, the probability of process error increases.

In order to overcome such a problem, research on "low mask technology" has been actively conducted in order to increase productivity and secure process margin by reducing the number of photolithography processes to a minimum.

Hereinafter, a manufacturing method of a TFT array substrate according to the prior art will be described with reference to the accompanying drawings.

1A to 1E are process cross-sectional views of a TFT array substrate according to the prior art.

In order to form a TFT array substrate for a liquid crystal display device according to the prior art, first, as shown in FIG. 1A, on the substrate 11, copper (Cu), aluminum (Al), aluminum alloy (AlNd), molybdenum (Mo), After depositing a low-resistance metal material such as chromium (Cr), a plurality of gate wirings (not shown), gate electrodes 12a, and gate pads 22 are formed by applying photolithography using a first mask. .

The photo etching technique proceeds as follows.

That is, after depositing a low-resistance metal at a high temperature on a transparent glass substrate having excellent heat resistance and applying a photoresist thereon, a first mask provided with a pattern layer on the photoresist is positioned to provide light. Is irradiated selectively to form the same pattern on the photoresist as the pattern layer of the first mask.

Next, the photoresist is patterned by removing the photoresist of the lighted portion using a developer. The metal of the exposed portion is selectively etched from the patterned photoresist to obtain a desired pattern.

Next, as shown in FIG. 1B, an inorganic material such as silicon nitride (SiNx) or silicon oxide (SiOx) is deposited at a high temperature on the entire surface including the gate electrode 12a to form a gate insulating layer 13.

Subsequently, amorphous silicon is deposited on the gate insulating layer 13 and patterned by a photolithography technique using a second mask to form an island-shaped semiconductor on the gate insulating layer 13 to overlap the gate electrode 12a. Layer 14 is formed.

Subsequently, as illustrated in FIG. 1C, low resistances such as copper (Cu), aluminum (Al), aluminum alloy (AlNd), molybdenum (Mo), and chromium (Cr) are applied to the entire surface including the semiconductor layer 14. A metal material is deposited and patterned by photolithography using a third mask to form a data wiring layer.

The data wiring layer includes data wirings (not shown) defining unit pixel regions crossing the gate wirings, a source electrode 15a and a drain electrode 15b overlapping edges of the semiconductor layer 14, and pads. The data pad 25 of the sub area is included.

The gate electrode 12a, the gate insulating layer 13, the semiconductor layer 14, and the source / drain electrodes 15a and 15b stacked as described above may include a thin film transistor that controls on / off of a voltage applied to a unit pixel. Achieve.

Next, as shown in FIG. 1D, the protective layer 16 is formed by coating an organic insulating material such as BCB or an inorganic insulating material of SiNx on the entire surface including the drain electrode 15b. In addition, a portion of the passivation layer 16 may be removed by a photoetching technique using a fourth mask to expose the contact hole 71 exposing the drain electrode 15b and the first pad open region exposing the gate pad 22. A second pad open area 81b through which the data pad 25 is exposed may be formed.

Next, as illustrated in FIG. 1E, a transparent conductive material, such as indium tin oxide (ITO) or indium zinc oxide (IZO), is deposited on the entire surface including the passivation layer 16 and a photolithography technique using a fifth mask is applied. The TFT array substrate is completed by forming the pixel electrode 17 in the pixel region so as to be electrically connected to the drain electrode 15b. At the same time, the transparent conductive film 27 is formed simultaneously to cover the first and second pad open regions to prevent oxidation of the gate pad and the data pad.

The TFT array substrate for a liquid crystal display device according to the prior art uses at least five exposure masks in order to form a gate wiring layer, a semiconductor layer, a data wiring layer, a contact hole of a protective film, and a pixel electrode. The higher the number, the more complicated the process and the higher the process time and cost, the process efficiency is greatly reduced.

In order to solve the above problems, the TFT array which improves the aperture ratio by applying a transparent semiconductor film to the TFT and forms a thin film transistor array substrate using a total of three exposure masks to reduce the process time and process cost Its purpose is to provide a substrate and a method of manufacturing the same.

The TFT array substrate of the present invention for achieving the above object is a thin film transistor including a gate wiring and a data wiring vertically crossed to define a unit pixel, and a transparent semiconductor film formed at the intersection of the two wiring, and the thin film A pixel electrode integrally formed from the drain electrode of the transistor, a passivation layer formed on the front surface including the thin film transistor, a gate pad electrode extending from the gate wiring, and a data pad electrode extending from the data wiring. It is characterized in that the configuration.

Meanwhile, a method of manufacturing a TFT array substrate for achieving another object of the present invention includes stacking a metal layer and a first transparent conductive layer on a substrate, and forming a gate wiring, a gate electrode, and a gate pad electrode by photolithography using a first mask. Forming a gate insulating film on the entire surface including the gate electrode, laminating a transparent semiconductor layer and a second transparent conductive layer on the whole surface including the gate insulating film, and using a photolithography technique using a second mask. Forming a wiring, a source / drain electrode, a data pad electrode, and a pixel electrode; forming a protective film on the entire surface including the data wire; and forming a gate insulating film and a protective film on the gate pad electrode and the data pad electrode. It comprises the step of exposing to the outside by removing by a photo-etching technique using a mask .

That is, the TFT array substrate for a liquid crystal display device according to the present invention forms a transparent TFT using a transparent semiconductor film such as AZO and ZnO, and completes the pattern on the substrate using a total of three masks, thereby reducing manufacturing costs by reducing the number of times of use of the mask. Savings and reducing process time.

Hereinafter, the manufacturing method of the TFT array substrate according to an embodiment of the present invention through the accompanying drawings.

First embodiment

2 is a plan view of a TFT array substrate according to a first embodiment of the present invention, FIG. 3 is a cross-sectional view of a TFT array substrate according to a first embodiment of the present invention, and FIGS. 4A to 4D are a first embodiment of the present invention. The process cross section of the TFT array substrate by an example is shown.

As illustrated in FIGS. 2 and 3, a TFT array substrate for a liquid crystal display according to the present invention includes an active region in which a pixel electrode 117 and a thin film transistor TFT are formed, and a gate pad GP and 122. And a pad portion region in which data pads DP and 125 are formed, respectively.

In detail, the active region includes a gate wiring 112 and a data wiring 115 that vertically cross each other to define a unit pixel, and a gate electrode 112a, a gate insulating film 113, and a semiconductor layer at intersections of the two wirings. 114, a thin film transistor TFT in which source / drain electrodes 115a and 115b are sequentially stacked, a protective film 116 formed on the front surface including the thin film transistor, and integrally extend from the drain electrode 115b. The pixel electrode 117 formed on the entire surface of the unit pixel and the storage electrode 132 parallel to the gate line 112 are formed.

In this case, the pixel electrode 117 overlaps the gate insulating layer 113 and the passivation layer 116 on the storage electrode 132 to form a storage capacitor.

In addition, a gate pad 122 extending from the gate line 112 to transmit a scan signal from the outside and a data pad 125 extending from the data line 115 to a video signal are formed in the pad area. The first contact hole 151 from which the gate insulating layer 113 is removed is formed on the gate pad 122, and the gate insulating layer 113 and the protective layer 116 are formed on the data pad 125. The removed second contact hole 152 is formed and then connected to the external driving circuit.

In this case, the gate wiring 112, the gate electrode 112a, the storage electrode 132, and the gate pad 122 may be formed of copper (Cu), copper alloy (Cu Alloy), aluminum (Al), and aluminum alloy (AlNd). Metal layers 101 such as aluminum neodymium (Mo), molybdenum (Mo), molybdenum alloys, chromium (Cr), chromium alloys, titanium (Ti), titanium alloys, silver (Ag), silver alloys, indium tin oxide (ITO), The first transparent conductive film 102 such as IZO (Indium Zinc Oxide), AZO, ZnO, etc. is sequentially deposited and then patterned.

The data line 115, the source / drain electrodes 115a and 115b, the pixel electrode 117, and the data pad electrode 125 are formed of a transparent semiconductor film 103 such as AZO and ZnO, and AZO, ZnO, and S−. A second transparent conductive film 104, such as ITO (Super-Indium Tin Oxide), is sequentially deposited and patterned at the same time.

Although not shown, the TFT array substrate on which the pixel electrode and the thin film transistor are formed as described above is opposed to the opposing substrate on which the common electrode and the color filter layer are formed, and then the liquid crystal is filled between the two substrates to complete the liquid crystal display device. .

In order to form the TFT array substrate of the liquid crystal display device, first, as shown in FIG. 4A, copper (Cu), copper alloy (Cu Alloy), aluminum (Al), Metal layers 101 such as aluminum alloys (AlNd: Aluminum Neodymium), molybdenum (Mo), molybdenum alloys, chromium (Cr), chromium alloys, titanium (Ti), titanium alloys, silver (Ag), silver alloys, and ITO ( A first transparent conductive film 102 such as indium tin oxide (IZO), indium zinc oxide (IZO), AZO, and ZnO is sequentially formed and patterned by a photolithography process using a first exposure mask to form a gate wiring (112 in FIG. 2), The gate electrode 112a of the TFT region, the storage electrode 132 of the storage region, and the gate pad electrode 122 of the gate pad portion region GP are formed.

As illustrated in FIG. 4B, an inorganic material such as silicon nitride (SiNx) or silicon oxide (SiOx) is deposited at a high temperature on the entire surface including the gate electrode 112a to form a gate insulating layer 113.

Subsequently, a transparent semiconductor film 103 such as AZO and ZnO, and a second transparent conductive film 104 such as AZO, ZnO, and S-ITO (S-ITO) are sequentially deposited on the gate insulating layer 113.

The transparent semiconductor film 103 such as AZO and ZnO is deposited by a method such as sputtering, chemical vapor deposition (CVD), or PLD, and has a crystallinity at room temperature to 600 ° C. Deposit.

For example, as a method of depositing ZnO by RF sputter, a ZnO target is used, and an Ar + O ₂ gas is injected and deposited. The specific resistance of the deposited ZnO thin film is different depending on the flow rate of the O ₂ gas. As a semiconductor layer, a TFT is manufactured under process conditions having semiconductor characteristics.

On the other hand, transparent semiconductor films such as AZO and ZnO have various characteristics from non-conductors, semiconductors to conductors according to deposition conditions. Recently, studies on manufacturing TFTs using semiconductor characteristics such as AZO and ZnO have been continued.

Specifically, ZnO TFTs have a polycrystalline phase, and even TFTs manufactured at room temperature are known to have excellent TFT characteristics compared to a-Si TFTs. In addition, there is almost no degradation of the semiconductor layer due to the movement of the carrier. In this respect, ZnO TFTs are considered as candidates for materials that can replace a-Si. In addition, when ZnO has a semiconductor characteristic, the bandgap is 3.3 eV or less, which is a state where the energy gap is larger than that of visible light, and thus, such as an a-Si TFT. There is no photo current problem. In addition, since the semiconductor layer of the TFT is transparent, it is not necessary to block the TFT from backlight or other light, and thus the aperture ratio is improved, and the transparent TFT can be combined with the transparent electrode material to make the transparent TFT.

In addition, after the photoresist 108 of UV curable resin (Ultraviolet curable resin) is applied to the entire upper surface of the second transparent conductive film 104 by a spin method or a roll coating method. A second exposure mask (not shown) having a predetermined pattern formed on the photoresist is exposed and exposed to UV or x-ray wavelengths, and then the exposed photoresist is developed to develop a double-stage photoresist pattern. Form.

Here, the second exposure mask is a diffraction exposure mask, and a light shielding layer and a translucent layer of a metal material are formed on a transparent substrate, and are divided into three regions: a transparent region, a translucent region, and a light shielding region, and the light transmittance is 100 in the transparent region. %, The light blocking region has a light transmittance of 0%, and the translucent region has a light transmittance of 0% to 100%.

Therefore, the remaining thickness of the photoresist 108 subjected to diffraction exposure is also divided into three regions, in which the photoresist is completely exposed in accordance with the position of the transparent region of the diffraction exposure mask and removed in a subsequent development process, and the diffraction exposure mask The photoresist is completely unexposed to correspond to the position of the light shielding region of the photoresist, and the portion is not removed at all, and the portion having the intermediate step is diffracted and exposed to the position of the translucent region of the diffraction exposure mask. However, the photoresist in which the exposed portion is etched is limited to the positive photoresist, and in the negative photoresist, the unexposed portion is etched.

That is, the diffractive photoresist 108 has a double step. The photoresist 108 of the region where the data line is to be formed, the region where the pixel electrode is formed in the sub-pixel region, and the region where the data pad DP is to be formed is formed. ) Remains completely, and the photoresist corresponding to the channel layer of the TFT region is formed in the middle step, and the photoresist in other portions is completely removed.

Next, the second transparent conductive film 104 and the transparent semiconductor film 103 exposed therebetween are etched using the photoresist 108 as a mask to etch the data wiring (115 in FIG. 2) and the semiconductor layer 114 in the TFT region. ), The pixel electrode 117 of the pixel portion, and the data pad electrode 125 of the data pad portion DP. In this case, the pixel electrode 117 overlaps the lower storage electrode 132 and forms a storage capacitor together with the gate insulating layer 113 interposed therebetween.

In this case, the transparent semiconductor film 103 may be etched by wet etching with HNO ₃ (0.5%) solution, and the second transparent conductive film and the transparent semiconductor film may be simultaneously etched.

Then, the photoresist 108 is ashed to completely remove the low stepped photoresist of the TFT region channel portion, and the photoresist of the pixel portion and the data pad portion DP within the region where the data wiring is to be formed and the sub-pixel region is formed. Leaves.

As shown in FIG. 4C, the second transparent conductive film 104 of the TFT region channel portion is selectively etched to separate the second transparent conductive film 104 on the semiconductor layer 114 so that the source / drain electrodes 115a, 115b) is formed to define the channel portion of the semiconductor layer and strip off all remaining photoresist 108.

As a result, the data wiring, the source / drain electrodes 115a and 115b, the data pad electrode 125, the semiconductor layer 114, and the pixel electrode 117 are formed by one diffraction exposure. The data line vertically crosses the gate line to define a sub-pixel, and the semiconductor layer 114 and the source / drain electrodes 115a and 115b are sequentially overlapped on the gate electrode to form a thin film transistor.

However, since the transparent semiconductor layer film 103, which is the semiconductor layer material, and the second transparent conductive film 104, which is a data wiring layer material, are simultaneously patterned, the data wiring, the pixel electrode 117, and the data pad electrode 125 may be transparent semiconductor layer films. A double layer of the 103 and the second transparent conductive film 104 is formed.

Subsequently, as shown in FIG. 4D, an organic insulating material such as benzocyclobutene (BCB) and an acrylic material or an inorganic insulating material such as silicon nitride or silicon oxide is deposited on the front surface including the source / drain electrodes 115a and 115b. To form the passivation layer 116 and to open the gate pad electrode 122 and the data pad electrode 125 to the outside by a photolithography process using a third exposure mask, respectively. Form. External driving circuits are connected through the first and second contact holes 151 and 152 to provide various signals to the panel.

The first contact hole 151 is formed by selectively etching the passivation layer 116 and the gate insulating layer 113 on the gate pad electrode 122, and the second contact hole 152 is formed by the data pad electrode 125. The upper protective film 116 is formed by etching. In this case, since the gate pad electrode 122 and the data pad electrode 125 formed as the double layer include the first and second transparent conductive films 102 and 104 as upper layers, the gate pad electrode 122 and the data pad electrode 125 may be oxidized even when exposed to the outside.

Since the TFT array substrate according to the present invention formed as described above is completed using a total of three exposure masks, it is useful as a low mask technique.

Second Embodiment

In the first embodiment, the present invention is limited to the manufacturing method of the TN mode TFT array substrate. However, the inventive concept of the IPS mode TFT array substrate may be applied to the manufacturing method of the IPS mode TFT array substrate. The manufacturing method will be described in detail.

5 is a plan view of a TFT array substrate according to a second embodiment of the present invention, FIG. 6 is a cross-sectional view of a TFT array substrate according to a second embodiment of the present invention, and FIGS. 7A to 7D are a second embodiment of the present invention. The process cross section of the TFT array substrate by an example is shown.

In the TFT array substrate for a transverse electric field type liquid crystal display device according to the present invention, as shown in FIGS. 5 and 6, an active region in which a common electrode 524, a pixel electrode 517, and a thin film transistor TFT are formed is provided. And a pad portion region in which the gate pads GP and 522 and the data pads DP and 525 are formed, respectively.

Specifically, the active region may include a gate wiring 512 and a data wiring 515 that vertically cross each other to define a unit pixel, a common wiring 532 parallel to the gate wiring 512 and transmitting a Vcom signal; A thin film transistor (TFT) in which a gate electrode 512a, a gate insulating film 513, a semiconductor layer 514, and source / drain electrodes 515a and 515b are sequentially stacked at the intersection of the two wires, and the thin film transistor including the thin film transistor. A passivation layer 516 formed on the entire surface, a pixel electrode 517 extending integrally with the drain electrode 515b, and a common branch branching from the common wiring and generating a transverse electric field in parallel with the pixel electrode 517. An electrode 524 is formed.

In this case, the common wiring 532 overlaps the drain electrode 515b or the pixel electrode 517 with the gate insulating layer 513 therebetween to form a storage capacitor.

In addition, a gate pad 522 extending from the gate wiring 512 to transmit a scan signal from the outside, and a data pad 525 extending from the data wiring 515 to transfer a video signal in the pad region. The first contact hole 551 having the gate insulating layer 513 removed from the gate pad 522 is formed, and the gate insulating layer 513 and the protective layer 516 are formed on the data pad 525. The removed second contact hole 552 is formed and connected to the external driving circuit.

In this case, the gate wiring 512, the gate electrode 512a, the common wiring 532, the common electrode 524, and the gate pad 522 may be copper (Cu), copper alloy (Cu Alloy), or aluminum (Al). Metal layers such as aluminum alloy (AlNd: Aluminum Neodymium), molybdenum (Mo), molybdenum alloy, chromium (Cr), chromium alloy, titanium (Ti), titanium alloy, silver (Ag), silver alloy, and ITO (Indium Tin) Oxide), IZO (Indium Zinc Oxide), AZO, ZnO and the like to form a first transparent conductive film is sequentially deposited and then patterned.

The data line 515, the source / drain electrodes 515a and 515b, the pixel electrode 517, and the data pad electrode 535 are each formed of a transparent semiconductor film 503 such as AZO or ZnO, and AZO, ZnO, and S−. A second transparent conductive film 504 such as ITO (Super-Indium Tin Oxide) is sequentially deposited and then patterned at the same time. In this case, the semiconductor layer between the source electrode 515a and the drain electrode 515b is formed of the transparent semiconductor film.

Although not shown, the TFT array substrate on which the common electrode, the pixel electrode and the thin film transistor are formed as described above is bonded to the opposite substrate on which the color filter layer is formed, and then the liquid crystal is filled therebetween to complete the liquid crystal display device.

To form a TFT array substrate of the transverse electric field type liquid crystal display device, first, as shown in FIG. 7A, copper (Cu), copper alloy (Cu alloy), aluminum ( Al), aluminum alloy (AlNd: Aluminum Neodymium), molybdenum (Mo), molybdenum alloy, chromium (Cr), chromium alloy, titanium (Ti), titanium alloy, silver (Ag), and a metal layer (501) such as silver alloy and , A first transparent conductive film 502 such as indium tin oxide (ITO), indium zinc oxide (IZO), AZO, and ZnO are sequentially formed and patterned by a photolithography process using a first exposure mask to form a gate wiring (512 in FIG. 5). ), A gate electrode 512a in the TFT region branching from the gate wiring, a common wiring (525 in FIG. 5) parallel to the gate wiring, and a plurality of common electrodes 524 branching from the common wiring and parallel to each other. ) And a gate pad electrode 522 in the gate pad region GP. The. In this case, a portion of the common wiring line serves as a lower electrode of the storage capacitor.

As illustrated in FIG. 7B, an inorganic material such as silicon nitride (SiNx) or silicon oxide (SiOx) is deposited on the entire surface including the gate electrode 512a at a high temperature to form a gate insulating layer 513.

Subsequently, a transparent semiconductor film 503 such as AZO and ZnO and a second transparent conductive film 504 such as AZO, ZnO, and S-ITO (S-ITO) are sequentially deposited on the gate insulating film 513.

The transparent semiconductor film 503 such as AZO or ZnO is deposited by a method such as sputtering, chemical vapor deposition (CVD), or PLD, and has a crystallinity at room temperature to 600 ° C. Deposit.

For example, as a method of depositing ZnO by RF sputter, a ZnO target is used, and an Ar + O ₂ gas is injected and deposited. The specific resistance of the deposited ZnO thin film is different depending on the flow rate of the O ₂ gas. As a semiconductor layer, a TFT is manufactured under process conditions having semiconductor characteristics.

On the other hand, transparent semiconductor films such as AZO and ZnO have various characteristics from non-conductors, semiconductors to conductors according to deposition conditions. Recently, studies on manufacturing TFTs using semiconductor characteristics such as AZO and ZnO have been continued.

Specifically, ZnO TFTs have a polycrystalline phase, and even TFTs manufactured at room temperature are known to have excellent TFT characteristics compared to a-Si TFTs. In addition, there is almost no degradation of the semiconductor layer due to the movement of the carrier. In this respect, ZnO TFTs are considered as candidates for materials that can replace a-Si. In addition, when the ZnO has a semiconductor characteristic, the bandgap is 3.3 eV or less, which is a state where the energy gap is larger than that of visible light, and thus a photo such as a-Si TFT. There is no photo current problem. In addition, since the semiconductor layer of the TFT is transparent, there is no need to block the TFT from backlight or other light, and thus the aperture ratio is improved, and the transparent TFT can be combined with the transparent electrode material to make the transparent TFT.

In addition, after the photoresist 508 of UV curable resin (Ultraviolet curable resin) is applied to the entire upper surface of the second transparent conductive film 504 by a spin method or a roll coating method. A second exposure mask (not shown) having a predetermined pattern formed on the photoresist is exposed and exposed to UV or x-ray wavelengths, and then the exposed photoresist is developed to develop a double-stage photoresist pattern. Form.

Here, the second exposure mask is a diffraction exposure mask, and a light shielding layer and a translucent layer of a metal material are formed on a transparent substrate, and are divided into three regions: a transparent region, a translucent region, and a light shielding region, and the light transmittance is 100 in the transparent region. %, The light blocking region has a light transmittance of 0%, and the translucent region has a light transmittance of 0% to 100%.

Accordingly, the remaining thickness of the photoresist 508 subjected to diffraction exposure is also divided into three regions, in which the photoresist is completely exposed and removed according to the position of the transparent region of the diffraction exposure mask, and the light shielding region of the diffraction exposure mask. The photoresist is completely unexposed correspondingly to the position and is not removed at all, and the part having the intermediate step is diffracted and exposed according to the position of the translucent region of the diffraction exposure mask. However, the photoresist in which the exposed portion is etched is limited to the positive photoresist, and in the negative photoresist, the unexposed portion is etched.

That is, the diffractive photoresist 508 has a double step, and the photoresist 508 of the region where the data line is to be formed, the region where the pixel electrode is formed in the sub-pixel region, and the region where the data pad DP is to be formed. ) Remains completely, and the photoresist corresponding to the channel layer of the TFT region is formed in the middle step, and the photoresist in other portions is completely removed.

Next, using the photoresist 508 as a mask, the second transparent conductive film 504 and the transparent semiconductor film 503 exposed therebetween are etched to etch the data wiring (515 in FIG. 5) and the semiconductor layer 514 in the TFT region. And the source / drain electrodes 515a and 515b, the pixel electrode 517 of the pixel portion, and the data pad electrode 525 of the data pad portion DP. In this case, the drain electrode and the pixel electrode 517 are integrally connected, and the drain electrode 515b or the pixel electrode 517 extends over the common wiring 532 to form a storage capacitor.

In this case, the transparent semiconductor film 503 may be etched by wet etching with HNO ₃ (0.5%) solution, and the second transparent conductive film and the transparent semiconductor film may be simultaneously etched.

Thereafter, the photoresist 508 is ashed to completely remove the low stepped photoresist of the TFT region channel portion, and the photoresist of the pixel portion and the data pad portion DP within the region where the data wiring is to be formed and the sub-pixel region is formed. Leaves.

The second transparent conductive film 504 of the TFT region channel portion is selectively etched to separate the second transparent conductive film 504 on the semiconductor layer 514 to form source / drain electrodes 515a and 515b to form the semiconductor layer. Define the channel portion and strip off all remaining photoresist 508.

As a result, in one diffraction exposure, as illustrated in FIG. 7C, data wirings, source / drain electrodes 515a and 515b, data pad electrodes 525, semiconductor layers 514, and pixel electrodes 517 are formed. . The data line vertically crosses the gate line to define a sub-pixel, and the semiconductor layer 514 and the source / drain electrodes 515a and 515b are sequentially overlapped on the gate electrode to form a thin film transistor. 517 is formed parallel to the common electrode 524.

However, since the transparent semiconductor layer film 503, which is the semiconductor layer material, and the second transparent conductive film 504, which is a data wiring layer material, are simultaneously patterned, the data wiring, the source / drain electrodes 515a and 515b, the pixel electrode 517, and the like. The data pad electrode 525 is formed of a double layer of the transparent semiconductor layer film 503 and the second transparent conductive film 504.

Subsequently, as shown in FIG. 7D, an organic insulating material such as benzocyclobutene (BCB) and an acrylic material or an inorganic insulating material such as silicon nitride or silicon oxide is deposited on the front surface including the source / drain electrodes 515a and 515b. To form the passivation layer 516 and to open the gate pad electrode 522 and the data pad electrode 525 to the outside by a photolithography process using a third exposure mask, respectively. Form. External driving circuits are connected through the first and second contact holes 551 and 552 to provide various signals to the panel.

The first contact hole 551 is formed by selectively etching the passivation layer 516 and the gate insulating layer 513 on the gate pad electrode 522, and the second contact hole 552 is a data pad electrode 525. The upper protective film 516 is formed by etching. In this case, since the gate pad electrode 522 and the data pad electrode 525 include the first and second transparent conductive films 502 and 504 as upper layers, there is no fear of oxidation even when exposed to the outside.

As described above, since the TFT array substrate of the transverse electric field type liquid crystal display device is completed using a total of three exposure masks, it is useful as a low mask technology.

On the other hand, the present invention described above is not limited to the above-described embodiment and the accompanying drawings, it is possible that various substitutions, modifications and changes within the scope without departing from the technical spirit of the present invention. It will be apparent to those of ordinary skill in Esau.

The TFT array substrate of the present invention as described above and a manufacturing method thereof have the following effects.

First, by applying a transparent semiconductor film such as AZO or ZnO to the TFT, the aperture ratio can be improved and the active region can be extended, thereby increasing the current efficiency (high mobility).

Second, the TFT array substrate can be manufactured by applying a total of three exposure masks by simultaneously forming a data wiring, a semiconductor layer, and a pixel electrode by simultaneously diffraction patterning the laminated film of the transparent semiconductor film such as AZO and ZnO and the transparent conductive film. do.

As such, by reducing the number of times the mask is used, process cost can be reduced, process time can be reduced, and the probability of process error can be lowered.

In addition, the technical idea according to the present invention can be applied to an IPS mode liquid crystal display device in addition to the TN liquid crystal display device.

Claims (23)

A gate wiring and a data wiring vertically intersecting to define a unit pixel; A thin film transistor formed at an intersection of the two wires and including a transparent semiconductor film; A pixel electrode integrally extending from the drain electrode of the thin film transistor; A protective film formed on the front surface including the thin film transistor, A gate pad electrode extending from the gate wiring; And a data pad electrode extending from the data line, And the data wirings, the source / drain electrodes of the thin film transistors, the pixel electrodes, and the data pad electrodes are formed on the same layer as a laminated film of a transparent semiconductor film and a transparent conductive film. The method of claim 1, And the transparent semiconductor film is formed of AZO or ZnO. The method of claim 1, And the gate wirings, the gate electrodes of the thin film transistors, and the gate pad electrodes are formed on the same layer as a laminated film of a metal layer and a transparent conductive layer. The method of claim 3, wherein The metal layer is copper (Cu), copper alloy (Cu Alloy), aluminum (Al), aluminum alloy (AlNd: Aluminum Neodymium), molybdenum (Mo), molybdenum alloy, chromium (Cr), chromium alloy, titanium (Ti), TFT array substrate, characterized in that formed of titanium alloy, silver (Ag) or silver alloy. The method of claim 3, wherein The transparent conductive layer is a TFT array substrate, characterized in that formed of indium tin oxide (ITO), indium zinc oxide (IZO), AZO or ZnO. delete delete The method of claim 1, The transparent conductive film is a TFT array substrate, characterized in that formed of AZO, ZnO or S-ITO (Super-Indium Tin Oxide). The method of claim 1, And the pixel electrode is formed on the entire surface of the unit pixel. The method of claim 1, And a common electrode forming a transverse electric field parallel to the pixel electrode. The method of claim 1, And the gate pad electrode and the data pad electrode are exposed to the outside by selectively removing an upper gate insulating film or a protective film. Stacking a metal layer and a first transparent conductive layer on a substrate and forming a gate wiring, a gate electrode and a gate pad electrode by photolithography using a first mask; Forming a gate insulating film on the entire surface including the gate electrode; Stacking a transparent semiconductor layer and a second transparent conductive layer on the entire surface including the gate insulating layer and forming a semiconductor layer, data wiring, source / drain electrodes, data pad electrodes, and pixel electrodes by a photoetching technique using a second mask; Forming a protective film on the entire surface including the data line; And removing the gate insulating film and the protective film on the gate pad electrode and the data pad electrode by photolithography using a third mask to expose the gate pad electrode and the protective film to the outside. 13. The method of claim 12, The metal layer is copper (Cu), copper alloy (Cu Alloy), aluminum (Al), aluminum alloy (AlNd: Aluminum Neodymium), molybdenum (Mo), molybdenum alloy, chromium (Cr), chromium alloy, titanium (Ti), A method of manufacturing a TFT array substrate, characterized in that it is formed of titanium alloy, silver (Ag) or silver alloy. 13. The method of claim 12, The first transparent conductive layer is formed of indium tin oxide (ITO), indium zinc oxide (IZO), AZO or ZnO manufacturing method of a TFT array substrate. 13. The method of claim 12, And said transparent semiconductor film is formed of AZO or ZnO. 13. The method of claim 12, The transparent conductive layer is a method of manufacturing a TFT array substrate, characterized in that formed by AZO, ZnO or S-ITO (Super-Indium Tin Oxide). 13. The method of claim 12, Wherein the transparent semiconductor film is deposited by sputtering, chemical vapor deposition (CVD), or PLD. 13. The method of claim 12, The method of manufacturing a TFT array substrate, wherein the transparent semiconductor film is wet etched by HNO ₃ (0.5%) solution in the photoetching technique using the second mask. 13. The method of claim 12, And the second mask is a diffraction exposure mask. 20. The method of claim 19, The step of stacking the transparent semiconductor layer and the transparent conductive layer on the entire surface including the gate insulating film and forming a semiconductor layer, data wiring, source / drain electrode, data pad electrode and pixel electrode by photo etching using a second mask, Forming a double-stage photoresist on the transparent conductive layer; Forming a semiconductor layer, a data line, a source / drain electrode, a data pad electrode, and a pixel electrode by collectively etching the transparent semiconductor layer and the transparent conductive layer using the photoresist as a mask; Ashing the photoresist to remove the low step photoresist; Etching the transparent conductive layer on the semiconductor layer by using the first photoresist as a mask to separate and form the source / drain electrodes and to define a channel layer; And removing the photoresist. 13. The method of claim 12, And the pixel electrode is formed in the entire sub-pixel. 13. The method of claim 12, And a plurality of the pixel electrodes are formed inside the sub-pixel, and further forming a common electrode parallel to the pixel electrodes. 13. The method of claim 12, A common wiring parallel to the gate wiring; Further comprising a plurality of common electrodes branched from the common wiring and parallel to each other, And the common wiring and the common electrode are formed simultaneously with the gate wiring.

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