KR100772112B1 - Semiconductor package - Google Patents

Semiconductor package Download PDF

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Publication number
KR100772112B1
KR100772112B1 KR1020060095083A KR20060095083A KR100772112B1 KR 100772112 B1 KR100772112 B1 KR 100772112B1 KR 1020060095083 A KR1020060095083 A KR 1020060095083A KR 20060095083 A KR20060095083 A KR 20060095083A KR 100772112 B1 KR100772112 B1 KR 100772112B1
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South Korea
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substrate
semiconductor chip
semiconductor package
pin
semiconductor
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KR1020060095083A
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Korean (ko)
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유종우
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주식회사 하이닉스반도체
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49805—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers the leads being also applied on the sidewalls or the bottom of the substrate, e.g. leadless packages for surface mounting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49833—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers the chip support structure consisting of a plurality of insulating substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49838—Geometry or layout
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA

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  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Geometry (AREA)
  • Lead Frames For Integrated Circuits (AREA)

Abstract

A semiconductor package is provided to prevent formation of cracks due to voids of an adhesive by electrically and physically connecting semiconductor chips onto a substrate using a connecting pin, and to reduce manufacturing cost and time by omitting wire bonding. A substrate(1) with plural ball lands(4) on a bottom surface thereof, the ball land having a pin hole. A semiconductor chip(2) is disposed on the substrate, and has a groove at a portion corresponding to the pin hole of the substrate. A connecting pin(3) is inserted into the pin hole and the groove from the bottom surface of the substrate to fix the semiconductor chip onto the substrate. A sealing(6) seals an upper surface of the substrate, as well as the semiconductor chip.

Description

반도체 패키지{Semiconductor package}Semiconductor Package {Semiconductor package}

도 1a 및 1b는 본 발명의 실시예에 따른 반도체 패키지를 도시한 단면도.1A and 1B are cross-sectional views illustrating semiconductor packages in accordance with embodiments of the present invention.

도 2는 본 발명의 다른 실시예에 따른 반도체 패키지를 도시한 단면도.2 is a sectional view showing a semiconductor package according to another embodiment of the present invention.

* 도면의 주요 부분에 대한 부호의 설명 *Explanation of symbols on the main parts of the drawings

1, 23 : 기판 2, 24 : 반도체칩 1, 23: substrate 2, 24: semiconductor chip

3 : 연결핀(전도체) 4 : 볼랜드     3: connecting pin (conductor) 4: borland

5 : 솔더볼 6 : 봉지제     5: solder ball 6: sealing agent

7 : 핀 홀 8 : 홈     7: pinhole 8: groove

21 : 연결핀(절연체) 22 : 금속와이어    21: connecting pin (insulator) 22: metal wire

본 발명은 반도체 패키지에 관한 것으로, 보다 상세하게는 접착제를 사용하지 않고 구성한 반도체 패키지에 관한 것이다.The present invention relates to a semiconductor package, and more particularly to a semiconductor package configured without using an adhesive.

웨이퍼(wafer) 한 장에는 동일한 전기회로가 인쇄된 칩이 수백개에서 혹은 수천개가 구비된다. 그러나, 칩 자체만으로는 외부로부터 전기를 공급 받아 전기신호를 전달해 주거나 전달받을 수 없으며, 또한, 칩은 미세한 회로를 담고 있어 외 부충격에 쉽게 손상될 수도 있다. 따라서, 칩에 전기적인 연결을 해 주고, 외부의 충격에 견디도록, 밀봉 포장하여 물리적인 기능과 형상을 갖게 해주는 것이 반도체 패키지이다.One wafer contains hundreds or even thousands of chips printed with the same electrical circuit. However, the chip itself cannot receive or transmit electric signals by receiving electricity from the outside, and the chip also contains a fine circuit, which may be easily damaged by external shock. Therefore, the semiconductor package provides electrical connection to the chip and seals the package to have physical functions and shapes to withstand external shocks.

통상적으로 반도체 패키지는 금속재 등으로 만들어진 리드프레임, 소정의 회로경로가 집약된 수지계열의 인쇄회로기판 또는 회로필름 등과 같이 각종 자재(기판)를 이용하여 여러가지 구조로 제조되는 바, 최근에는 단위 시간당 생산성을 증대시키고자 매트릭스(matrix) 배열 구조의 칩 부착 영역을 갖는 기판을 이용하여, 반도체 칩 부착 공정, 와이어 본딩 공정, 몰딩 공정 등을 거치게 한 다음, 낱개로 소잉 내지 싱글레이션 공정 등을 거치게 하여 한번에 많은 반도체 패키지를 제조하는 추세에 있다.In general, semiconductor packages are manufactured in various structures using various materials (substrates), such as lead frames made of metals, resin-based printed circuit boards or circuit films in which predetermined circuit paths are concentrated, and in recent years, productivity per unit time. By using a substrate having a chip attachment region of a matrix array structure, the semiconductor chip attaching process, the wire bonding process, the molding process, and the like are subjected to a sawing or a singulation process. There is a trend to manufacture many semiconductor packages.

대개, 반도체 패키지는 기판에 칩을 부착하는 공정과, 칩과 기판간의 전기적 신호를 위한 와이어 본딩 공정, 칩과 와이어 등을 감싸는 몰딩 공정 및 인출단자(솔더볼) 부착 공정 등을 필수적으로 거쳐 제조된다.In general, a semiconductor package is manufactured through a process of attaching a chip to a substrate, a wire bonding process for electrical signals between the chip and the substrate, a molding process of wrapping the chip and the wire, and a process of attaching a lead terminal (solder ball).

그러나 상기와 같은 종래의 반도체 패키지는, 반도체칩과 기판 간을 부착시, 에폭시 계열의 접착제 또는 테입을 이용하는데, 반도체 패키지 제작 후의 신뢰성 테스트 후, 접착제에 발생된 보이드로 인해 반도체칩과 접착제 사이에서 박리가 늘어남은 물론 이에 따른 크랙이 발생하여 패키지가 손상되는 문제점이 있다. However, the conventional semiconductor package as described above uses an epoxy-based adhesive or tape when attaching the semiconductor chip to the substrate. After reliability test after fabrication of the semiconductor package, the void generated in the adhesive causes the gap between the semiconductor chip and the adhesive. There is a problem in that the peeling is increased as well as the resulting cracks damage the package.

따라서, 본 발명은 상기와 같은 문제점을 해결하고자 안출된 것으로서, 신뢰성 테스트 후에도 반도체칩과 접착제 사이의 크랙을 방지한 반도체 패키지를 제공 함에 그 목적이 있다.Accordingly, an object of the present invention is to provide a semiconductor package which prevents cracking between a semiconductor chip and an adhesive even after a reliability test.

상기와 같은 목적을 달성하기 위한 본 발명은 하면에 다수의 볼랜드가 구비되고, 상기 볼랜드에 핀 홀이 형성된 기판; 상기 기판 상에 배치되며, 상기 기판의 핀 홀과 대응되는 부분 각각에 홈이 형성된 반도체칩; 상기 기판 하면으로부터 핀 홀 및 홈에 삽입되어 상기 기판 상에 반도체칩을 고정시켜주는 연결 핀; 및 상기 반도체칩을 포함한 기판의 상면을 밀봉하는 봉지제;를 포함하는 것을 특징으로 하는 반도체 패키지를 제공한다.The present invention for achieving the above object is provided with a plurality of ball land on the lower surface, the substrate has a pin hole formed in the ball land; A semiconductor chip disposed on the substrate and having grooves formed in portions corresponding to the pin holes of the substrate; A connection pin inserted into the pin hole and the groove from the lower surface of the substrate to fix the semiconductor chip on the substrate; And an encapsulant for sealing an upper surface of the substrate including the semiconductor chip.

여기서, 상기 기판 하면의 볼랜드에 부착된 실장부재를 더 포함하는 것을 특징으로 한다.Here, the mounting member attached to the ball land on the lower surface of the substrate is characterized in that it further comprises.

상기 핀 홀은, 그 갯수가 상기 반도체 칩의 크기에 대비하여 증가 또는 감소 되어 형성되는 것을 특징으로 한다.The number of the pin holes is characterized in that the number is formed to increase or decrease relative to the size of the semiconductor chip.

상기 연결 핀은 전도체로 이루어져 반도체칩과 기판 간을 전기적으로 연결시키는 것을 특징으로 한다.The connection pin is made of a conductor, characterized in that for electrically connecting between the semiconductor chip and the substrate.

상기 연결 핀은 절연체로 형성된 것을 특징으로 한다.The connecting pin is characterized in that formed of an insulator.

상기 연결 핀이 절연체로 형성된 경우, 상기 기판과 반도체칩간을 전기적으로 연결하는 금속와이어를 더 포함하는 것을 특징으로 한다.When the connection pin is formed of an insulator, the connection pin further comprises a metal wire electrically connecting the substrate and the semiconductor chip.

(실시예)(Example)

이하, 첨부된 도면을 참조하여 본 발명의 바람직한 실시예를 상세하게 설명하도록 한다.Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

먼저, 본 발명의 기술적 원리를 간략하게 설명하면, 본 발명은 반도체 패키지를 구성함에 있어서, 기판상의 반도체칩 고정을 연결핀을 이용해서 달성한다.First, the technical principle of the present invention will be briefly described. In the present invention, in the construction of a semiconductor package, fixing of a semiconductor chip on a substrate is achieved by using a connection pin.

이 경우, 본 발명은 반도체칩과 기판간을 접착제를 이용하여 고정시키는 종래의 반도체 패키지와 달리 접착제가 배재된 연결핀으로 기판상에 반도체칩을 고정시켜 반도체 패키지를 구성함으로서, 접착제에 의해 발생되는 보이드에 의해 기인하는 크랙 발생에 의한 반도체 패키지의 불량을 감소시킬 수 있다. In this case, the present invention, unlike the conventional semiconductor package that is fixed between the semiconductor chip and the substrate using an adhesive, by forming a semiconductor package by fixing the semiconductor chip on the substrate with a connection pin, the adhesive is excluded, is generated by the adhesive Defects in the semiconductor package due to cracks caused by voids can be reduced.

또한, 본 발명은 반도체칩과 기판간을 연결시 접착제를 배재시켜 고정시킴으로서, 접착제 프린팅 공정이 제거됨에 따른 전체 패키지의 공정을 단축시킬 수 있으며, 접착제 미사용으로 인한 반도체 패키지 제조의 단가를 절감시킬 수 있다.In addition, the present invention by fixing the adhesive by excluding the adhesive when connecting the semiconductor chip and the substrate, it is possible to shorten the process of the entire package as the adhesive printing process is removed, and to reduce the cost of manufacturing the semiconductor package due to the use of the adhesive have.

구체적으로는, 도 1a 및 도 1b는 본 발명의 실시예에 따른 반도체 패키지를 도시한 단면도로서, 이를 설명하면 다음과 같다.Specifically, FIGS. 1A and 1B are cross-sectional views illustrating a semiconductor package according to an exemplary embodiment of the present invention.

도 1a를 참조하면 반도체칩(2)은 하면에 볼랜드(4) 및 상기 볼랜드(4)에 포함된 핀 홀(7)이 형성되고, 기판(1) 상에는 홈(8)이 형성된다. Referring to FIG. 1A, a borland 4 and a pin hole 7 included in the borland 4 are formed on a lower surface of the semiconductor chip 2, and a groove 8 is formed on the substrate 1.

상기 핀 홀(7) 및 홈(8)에는 접착제가 배재된 연결핀(3)에 의해 기판(2)상에 반도체칩(2)이 배치된다.In the pin hole 7 and the groove 8, the semiconductor chip 2 is disposed on the substrate 2 by a connection pin 3 having an adhesive.

아울러, 상기 반도체칩(2)을 포함하는 기판(1)의 상면을 봉지제(6)로 밀봉된다.In addition, the upper surface of the substrate 1 including the semiconductor chip 2 is sealed with an encapsulant 6.

또한, 상기 기판(1) 하면의 볼랜드(4)에는 실장수단으로서 솔더볼(5)이 부착된다.In addition, a solder ball 5 is attached to the ball land 4 on the lower surface of the substrate 1 as mounting means.

자세하게, 도 1b를 참조하면, 상기 기판(1)은 하면에 다수의 볼랜드(4)를 구 비하고, 상기 다수의 모든 볼랜드(4)에는 핀 홀(7)이 형성된다. In detail, referring to FIG. 1B, the substrate 1 includes a plurality of ball lands 4 on a lower surface thereof, and pin holes 7 are formed in all of the plurality of ball lands 4.

상기 기판(1)상에 배치되는 상기 반도체칩(2)은 상기 기판의 핀 홀과 대응되는 부분에 다수의 홈(8)이 형성된다.In the semiconductor chip 2 disposed on the substrate 1, a plurality of grooves 8 are formed in portions corresponding to the pin holes of the substrate.

여기서, 상기 기판(1)과 반도체칩(2)에 형성되는 핀 홀(7) 및 홈(8)의 갯수는 상기 반도체칩(2)의 크기에 고려하여 형성되는 것이 바람직하다.Herein, the number of the pinholes 7 and the grooves 8 formed in the substrate 1 and the semiconductor chip 2 may be formed in consideration of the size of the semiconductor chip 2.

또한, 상기 핀 홀(7)을 관통하고 홈(8)에 삽입되는 형태로 상기 기판 상에 반도체칩을 고정시키는 연결 핀(3)은, 상기 반도체칩(2)과 기판(1)간을 전기적으로 연결시킬 수 있도록 전도체로 형성하여 마련된다.In addition, the connecting pins 3, which penetrate the pin holes 7 and are inserted into the grooves 8, to fix the semiconductor chips on the substrate, are electrically connected between the semiconductor chips 2 and the substrate 1. It is formed by forming a conductor so that it can be connected.

따라서, 본 발명의 반도체 패키지는, 접착제를 사용하여 기판상에 반도체칩을 부착하는 종래의 반도체 패키지와 달리, 상기 기판에는 핀 홀을 형성하고, 반도체칩에는 홈을 형성시켜, 상기 핀 홀을 관통하고 홈에 삽입되는 연결 핀만을 사용하여 기판 상에 반도체칩을 부착하여 접착제의 사용을 배재함으로써, 크랙이 발생되는 문제점을 근본적으로 해결할 수 있다.Accordingly, the semiconductor package of the present invention, unlike the conventional semiconductor package that attaches the semiconductor chip on the substrate using an adhesive, forms a pin hole in the substrate and a groove in the semiconductor chip to penetrate the pin hole. And by using only the connection pin inserted in the groove by attaching the semiconductor chip on the substrate to exclude the use of the adhesive, it is possible to fundamentally solve the problem that the crack occurs.

또한, 기판 상에 반도체칩을 고정시키는 연결핀을 전도체로 구성하여 상기 반도체칩과 기판간을 와이어본딩이 없이도 전기적으로 연결할 수 있음으로서, 종래의 반도체 패키지의 와이어본딩을 생략하여 이에 따른 패키지의 단가 및 공정 시간을 감소시킬 수 있다. In addition, since the connecting pin for fixing the semiconductor chip on the substrate can be electrically connected between the semiconductor chip and the substrate without wire bonding, wire bonding of the conventional semiconductor package is omitted, and thus the unit cost of the package is omitted. And process time can be reduced.

도 2는 본 발명의 다른 실시예에 따른 반도체 패키지를 도시한 단면도로서 이를 설명하면 다음과 같다.2 is a cross-sectional view illustrating a semiconductor package according to another embodiment of the present invention.

도시된 바와 같이, 본 발명의 다른 실시예에 따른 반도체 패키지는, 본 발명 의 실시예의 구성과 거의 흡사하며, 다만 기판(23) 상에 반도체칩(24)을 부착시 사용하는 연결 핀(21)을 본 발명의 실시예와 같이 전도체로 형성하는 것과 달리, 절연체로 형성하여 구성한다.As shown, the semiconductor package according to another embodiment of the present invention is almost similar to the configuration of the embodiment of the present invention, except that the connecting pin 21 used when attaching the semiconductor chip 24 on the substrate 23. It is formed by forming an insulator, unlike the form of a conductor as in the embodiment of the present invention.

여기서, 상기 연결 핀(21)을 절연체로 형성시에는, 기판(23)과 반도체칩(24)간을 전기적으로 연결시키기 위한 금속와이어(22)를 본딩한다.Here, when the connecting pin 21 is formed of an insulator, the metal wires 22 for electrically connecting the substrate 23 and the semiconductor chip 24 are bonded.

그 이외의 나머지 구성요소들은 전술한 본 발명의 실시예의 그것과 동일하며, 여기서는 그 설명을 생략하도록 한다. The other components are the same as those of the above-described embodiment of the present invention, and the description thereof will be omitted.

이 경우, 본 발명의 반도체 패키지는 본 발명의 실시예와 마찬가지로 접착제가 배재된 연결 핀을 사용하여 기판상에 반도체칩을 물리적으로 고정시킴으로서, 종래의 반도체 패키지에서와 같은 접착제 보이드에 의해 기인하는 크랙의 발생을 방지할 수 있다.In this case, the semiconductor package of the present invention, like the embodiment of the present invention, by physically fixing the semiconductor chip on the substrate using a connection pin with an adhesive, cracks caused by the adhesive voids as in the conventional semiconductor package Can be prevented.

한편, 이하에서는 도시하지는 않았지만 본 발명의 실시예에 따른 반도체 패키지의 제조방법을 간략하게 설명하도록 한다.On the other hand, although not shown below will be briefly described a method of manufacturing a semiconductor package according to an embodiment of the present invention.

홈이 형성된 반도체칩을 종래와 같은 진공 부착-툴을 이용하여 들어올려 핀 홀이 형성된 기판상에 배치시키고, 상기 반도체칩이 기판상에 배치되자마자 상기 진공 부착-툴의 진공방향을 반대로 작용하게 하여 반도체칩을 기판방향으로 밀어준다.The grooved semiconductor chip is lifted up using a conventional vacuum attachment tool and placed on a substrate having pinholes, and as soon as the semiconductor chip is disposed on the substrate, the vacuum direction of the vacuum attachment tool is reversed. To push the semiconductor chip toward the substrate.

이 때, 상기와 같이 반도체칩을 기판방향으로 밀어주면서 동시에 기판의 하면에는 상기 반도체칩과 기판간을 고정시키는 연결핀을 핀 홀을 관통하고 홈에 삽입하여 반도체칩과 기판간을 고정시킨다.At this time, the semiconductor chip is pushed in the direction of the substrate as described above, and at the same time, a connecting pin for fixing the semiconductor chip and the substrate to the lower surface of the substrate is inserted through the pin hole and inserted into the groove to fix the semiconductor chip and the substrate.

이 경우, 상기 연결핀을 삽입하면서 반대방향으로는 반도체칩을 진공으로 밀어주기 때문에, 상기 연결핀으로 상기 기판상에 반도체칩을 단단하게 고정시킬 수 있다.In this case, since the semiconductor chip is pushed in a vacuum in the opposite direction while the connecting pin is inserted, the semiconductor chip can be firmly fixed on the substrate by the connecting pin.

이 후의 제조방법은 종래의 반도체 패키지의 그것과 동일하여 생략하도록 한다.The subsequent manufacturing method is the same as that of the conventional semiconductor package, and will be omitted.

결국, 본 발명의 반도체 패키지는 접착제를 사용하지 않고 접착제가 배재된 연결핀을 사용하여 기판상에 반도체칩을 전기적 및 물리적으로 고정시킴으로서, 종래의 반도체 패키지에서와 같은 접착제 보이드에 의한 크랙의 발생을 방지할 수 있다.As a result, the semiconductor package of the present invention uses the connection pins without the adhesive to fix the semiconductor chip on the substrate electrically and physically, thereby preventing the occurrence of cracks due to the adhesive voids as in the conventional semiconductor package. You can prevent it.

또한, 상기 연결핀이 전도체로 형성시킬 경우, 상기 기판상에 반도체칩을 전기적으로 연결함으로서, 와이어본딩이 생략되어 그에 따른 패키지의 단가 및 공정시간을 감소시킬 수 있다.In addition, when the connecting pin is formed of a conductor, wire bonding is omitted by electrically connecting the semiconductor chip on the substrate, thereby reducing the unit cost and processing time of the package.

이상, 여기에서는 본 발명을 특정 실시예에 관련하여 도시하고 설명하였지만, 본 발명이 그에 한정되는 것은 아니며, 이하의 특허청구의 범위는 본 발명의 정신과 분야를 이탈하지 않는 한도 내에서 본 발명이 다양하게 개조 및 변형될 수 있다는 것을 당업계에서 통상의 지식을 가진 자가 용이하게 알 수 있다.As mentioned above, although the present invention has been illustrated and described with reference to specific embodiments, the present invention is not limited thereto, and the scope of the following claims is not limited to the scope of the present invention. It can be easily understood by those skilled in the art that can be modified and modified.

이상에서와 같이, 본 발명은 반도체 패키지를 구성함에 있어서, 접착제가 배재된 연결핀을 사용하여 기판상에 반도체칩을 전기적 및 물리적으로 연결함으로서, 종래의 접착제 보이드에 기인한 크랙의 발생을 방지할 수 있다.As described above, the present invention in the construction of the semiconductor package, by using the connection pins, the adhesive is excluded, by electrically and physically connecting the semiconductor chip on the substrate, it is possible to prevent the occurrence of cracks due to conventional adhesive voids Can be.

또한, 연결핀을 전도체로 형성하여 반도체 패키지를 구성시, 와이어본딩이 생략되어 그에 따른 패키지의 단가 및 공정시간을 감소시킬 수 있다.In addition, when the connecting pin is formed of a conductor to form a semiconductor package, wire bonding may be omitted, thereby reducing the cost and processing time of the package.

Claims (6)

하면에 다수의 볼랜드가 구비되고, 상기 볼랜드에 핀 홀이 형성된 기판;A substrate having a plurality of ball lands on a lower surface thereof, the pin holes being formed in the ball lands; 상기 기판 상에 배치되며, 상기 기판의 핀 홀과 대응되는 부분 각각에 홈이 형성된 반도체칩;A semiconductor chip disposed on the substrate and having grooves formed in portions corresponding to the pin holes of the substrate; 상기 기판 하면으로부터 핀 홀 및 홈에 삽입되어 상기 기판 상에 반도체칩을 고정시켜주는 연결 핀; 및A connection pin inserted into the pin hole and the groove from the lower surface of the substrate to fix the semiconductor chip on the substrate; And 상기 반도체칩을 포함한 기판의 상면을 밀봉하는 봉지제;An encapsulant for sealing an upper surface of the substrate including the semiconductor chip; 를 포함하는 것을 특징으로 하는 반도체 패키지.Semiconductor package comprising a. 제 1 항에 있어서, The method of claim 1, 상기 기판 하면의 볼랜드에 부착된 실장부재를 더 포함하는 것을 특징으로 하는 반도체 패키지.The semiconductor package further comprises a mounting member attached to the ball land on the lower surface of the substrate. 제 1 항에 있어서, The method of claim 1, 상기 핀 홀은, 그 갯수가 상기 반도체 칩의 크기에 대비하여 증가 또는 감소 되어 형성되는 것을 특징으로 하는 반도체 패키지.The pin hole is a semiconductor package, characterized in that the number is formed to increase or decrease relative to the size of the semiconductor chip. 제 1 항에 있어서, The method of claim 1, 상기 연결 핀은 전도체로 이루어져 반도체칩과 기판 간을 전기적으로 연결시 키는 것을 특징으로 하는 반도체 패키지.The connecting pin is made of a conductor, characterized in that for electrically connecting between the semiconductor chip and the substrate. 제 1 항에 있어서, The method of claim 1, 상기 연결 핀은 절연체로 형성된 것을 특징으로 하는 반도체 패키지.The connecting pin is a semiconductor package, characterized in that formed of an insulator. 제 5 항에 있어서, The method of claim 5, 상기 연결 핀이 절연체로 형성된 경우, 상기 기판과 반도체칩간을 전기적으로 연결하는 금속와이어를 더 포함하는 것을 특징으로 하는 반도체 패키지.When the connection pin is formed of an insulator, the semiconductor package further comprises a metal wire for electrically connecting the substrate and the semiconductor chip.
KR1020060095083A 2006-09-28 2006-09-28 Semiconductor package KR100772112B1 (en)

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Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH03110887A (en) * 1989-09-25 1991-05-10 Fujitsu Ltd Wiring of remodeled wire
JP2005347513A (en) 2004-06-03 2005-12-15 Matsushita Electric Ind Co Ltd Semiconductor device and its manufacturing method

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH03110887A (en) * 1989-09-25 1991-05-10 Fujitsu Ltd Wiring of remodeled wire
JP2005347513A (en) 2004-06-03 2005-12-15 Matsushita Electric Ind Co Ltd Semiconductor device and its manufacturing method

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