KR100699847B1 - Pixel circuit having narrow band-gap photodiode in image sensor - Google Patents

Abstract

Disclosed is a pixel circuit having a narrow bandgap optical element in an image sensor. In the image sensor, long wavelength light may be easily absorbed even at a shallow position from the semiconductor surface by an optical device having a narrow band gap.

Description

Pixel circuit having narrow band-gap photodiode in image sensor

BRIEF DESCRIPTION OF THE DRAWINGS In order to better understand the drawings cited in the detailed description of the invention, a brief description of each drawing is provided.

1 is a block diagram illustrating a general image sensor.

FIG. 2 is an example illustrating a color filter pattern of the APS array of FIG. 1.

3 is a unit pixel driving circuit diagram of the APS array of FIG. 1.

4 shows a general cross-sectional structure of the optical device of FIG.

5 illustrates pixel driving circuits of an image sensor according to an exemplary embodiment of the present invention.

6A to 6C show a cross-sectional structure in the manufacturing process of the optical device of FIG.

FIG. 7 is a timing diagram for signals of the pixel driving circuit of FIG. 5.

The present invention relates to an image sensor, and more particularly to a pixel circuit of an image sensor of a CMOS image sensor (CIS) type.

The CMOS image sensor is mounted on a mobile phone camera, a digital still camera, or the like, and captures an image deployed in a field of view, converts it into an electrical signal, and converts the converted image signal into a digital signal. The digital image signal output from the CMOS image sensor is three color (Red, Green, Blue) color image data, and the digital image signal is processed to drive a display device such as a liquid crystal display (LCD).

1 is a block diagram illustrating a general CMOS image sensor 100. Referring to FIG. 1, the image sensor 100 includes an active pixel sensor (APS) array 110, a row driver 120, and an analog-digital converter (ADC) 130. It is provided.

The row driver 120 receives a control signal from a row decoder (not shown), and the analog-to-digital converter 130 receives a control signal from a column decoder (not shown). In addition, the image sensor 100 includes a control unit (not shown) for generating general timing control signals and addressing signals for selecting each pixel and outputting a sensed image signal.

2 illustrates an example of a color filter pattern of the APS array 110 of FIG. 1. In general, in the case of the color image sensor 100, as shown in FIG. 2, a color filter is installed to receive only light of a specific color on each pixel forming the APS array 110. Place at least three kinds of color filters. The most common color filter array is Bayer, where the patterns of two colors R (red) and G (green) are arranged in one row, and the patterns of two colors G (green) and B (blue) are arranged in another row. ) Has a pattern. At this time, the G (green) color closely related to the luminance signal is arranged in all rows, and the R (red) color and the B (blue) color are alternately arranged in each row to increase the luminance resolution. Digital still cameras, etc. are applied to a CIS array of many million pixels or more in order to increase the resolution.

In the image sensor 100 having such a pixel structure, the APS array 110 detects light using a photodiode and converts the light into an electrical signal to generate an image signal. The video signal output from the APS array 110 is an analog signal of three colors of red (R), green (G), and blue (B). The analog-digital converter 130 receives an analog image signal output from the pixel array 110 and converts the analog image signal into a digital signal. When the image signal sensed by the optical device is converted into a digital signal by the analog-to-digital converter 130, a correlated double sampling (CDS) method is used. Such a CDS driving method is well known.

3 is a unit pixel driving circuit diagram of the APS array 110 of FIG. 1. Referring to FIG. 3, the unit pixel driving circuit 300 of the APS array 110 generally includes an optical device PD and four transistors. In the analog-to-digital conversion of the CDS method, when the reset control signal RX is activated at each pixel of the row selected by the row select signal SEL, the signal of the floating diffusion node transmitted from the power supply VDD is reset. VRES) and a signal sensed by the optical device PD and transmitted to the FD node when the transfer control signal TX is activated are output as the image signal VSIG, thereby resetting the reset signal VRES and the image signal VSIG. Conversion to digital signal is made according to the difference of The row select signal SEL, the reset control signal RX, and the transfer control signal TX may be generated by the row driver 120.

As illustrated in FIG. 3, the pixel circuit 300 of the image sensor is composed of transistors for outputting an optical device PD, a reset signal VRES, and an image signal VSIG at an appropriate timing. Recently, as the image sensor has evolved to a high pixel, the demand for small size pixels is increasing, so that the pixel circuit 300 of the pixel circuit 300 may be improved to improve the display quality using the high pixel APS array 110. Optical devices and transistors should be designed with appropriate sizes.

In particular, smaller pixel sizes also require scaling in the depth direction of the semiconductor substrate from which the pixels are manufactured. However, there is a limit to vertical scaling in relation to the sensitivity characteristic of the optical device PD. 4 illustrates a general cross-sectional structure of the optical device PD of FIG. 3. Referring to FIG. 4, typically, the optical device PD has a structure of a P-N diode formed on a “Deep P-well” layer. Here, in order not to reduce the sensitivity to long wavelengths such as R (red) color, "Deep P-well" is formed at a depth of about 3 to 4 µm from the surface. In such an optical device (PD) structure, there is no problem when the pixel size is large, but as the pixel size is reduced, crosstalk with neighboring optical devices may occur, thereby degrading image quality. In order to reduce crosstalk, it is necessary to make the “Deep P-well” layer shallow, but there is a problem in that the sensitivity of the optical device PD is weakened.

Accordingly, an object of the present invention is to provide a pixel circuit of an image sensor employing a narrow bandgap optical element capable of scaling in a vertical direction of a semiconductor in order to reduce crosstalk in response to pixel reduction.

A pixel circuit of an image sensor according to an aspect of the present invention for achieving the above technical problem, the optical element; A transfer transistor operating according to a transfer control signal; A reset transistor operating according to the reset control signal; And a source-follower transistor operating according to a signal transmitted to the FD node, the reset signal based on the signal transmitted to the FD node through the reset transistor and the FD from the optical device by the transfer transistor. An image signal based on a signal transmitted to a node is output through the source-follower transistor, and the optical device is formed to have a narrow bandgap semiconductor layer in a semiconductor substrate.

The pixel circuit may further include a row select transistor that selectively outputs or does not output the source-follower transistor output according to a row select signal. The reset signal and the image signal are output from the source follower transistor to the output node while the row select signal is activated.

The narrow bandgap semiconductor layer is characterized in that the SiGe layer or SiGeC.

According to another aspect of the present invention, a pixel circuit of an image sensor includes a gate electrode receiving a row selection signal, one of the source / drain electrodes connected to a first node, and the other of the pixel circuits of the image sensor. A first MOSFET connected to the node; The gate electrode receives a reset control signal, one of the source / drain electrodes connected to a first power supply, and the other of the gate / drain electrodes connected to a second node; A third MOSFET connected to the second node, one of the source / drain electrodes connected to the first power supply, and the other of the gate / drain electrodes connected to the first node; A fourth MOSFET receiving a transfer control signal, one side of the source / drain electrodes connected to the second node, and the other side connected to the third node; And an optical device for photoelectric conversion between the second power supply and the third node, wherein the optical device is formed to have a narrow bandgap semiconductor layer in the semiconductor substrate.

The pixel circuit may form an APS array of Bayer patterns, and only the photons corresponding to the G and B patterns of the Bayer patterns may have the narrow bandgap semiconductor layer. The optical device further has a silicon epitaxial layer over the narrow bandgap semiconductor layer, wherein a diode structure is formed in the diode layer in the silicon epitaxial layer. The first to fourth MOSFETs may be formed in the silicon epitaxial layer.

Outputting a reset signal based on a signal transmitted from the first power source to the second node in response to the reset control signal through the output node connected to a bias circuit when the row selection signal is activated; And in response to a transfer control signal, output a video signal based on a signal transmitted photoelectrically converted from the optical device to the second node.

In order to fully understand the present invention, the operational advantages of the present invention, and the objects achieved by the practice of the present invention, reference should be made to the accompanying drawings which illustrate preferred embodiments of the present invention and the contents described in the accompanying drawings.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. Like reference numerals in the drawings denote like elements.

5 illustrates pixel driving circuits 500 of a CMOS image sensor according to an embodiment of the present invention. Referring to FIG. 5, the pixel driving circuits 500 according to an exemplary embodiment of the present invention bias the unit pixel circuit 510 and the output (VRES / VSIG) node of the unit pixel circuit 510. Bias circuit 520). Although the unit pixel circuit 510 is two-dimensionally arranged to form an APS array, only one pixel circuit 510 of the pixel circuits forming the APS array is illustrated in FIG. 5. The bias circuit 520 may be disposed around the top or bottom vertically from the APS array region. The image sensor according to an embodiment of the present invention may include a row driver as shown in FIG. 1 and an analog-digital converter (ADC). The row driver (not shown) may generate the row select signal SEL, the reset control signal RX, and the transfer control signal TX of FIG. 5. The analog-to-digital converter (not shown) may receive an analog reset signal VRES and an image signal VSIG output from the output VRES / VSIG node of the image sensor and perform digital conversion.

For example, the unit pixel circuit 510 constituting the APS array of the image sensor according to an embodiment of the present invention may include a row select transistor M1, a reset transistor M2, and a source. A source follower transistor M3, a transfer transistor M4 and an optical device PD. These transistors are all shown as being N-type MOSFETs, but the shape of the MOSFETs may be different.

In the row select transistor M1, a gate electrode receives a row select signal SEL, one side of the source / drain electrodes is connected to the first node ND1, and the other side is connected to the output VRES / VSIG node. Connected. In the reset transistor M2, the gate electrode receives the reset control signal RX, one side of the source / drain electrodes is connected to a constant power supply VDD, and the other side is connected to the FD node. In the source-follower transistor M3, a gate electrode is connected to the FD node, one side of the source / drain electrodes is connected to the constant power supply VDD, and the other side is connected to the first node ND1. Connected. In the transfer transistor M4, a gate electrode receives the transfer control signal TX, one of the source / drain electrodes is connected to the FD node, and the other is connected to the third node ND3. The optical device PD performs photoelectric conversion between a power supply VSS (eg, ground) and the third node ND3.

The optical device PD is formed to have a narrow band gap semiconductor layer 620 in the semiconductor substrate 610. 6A to 6C show cross-sectional structures in the manufacturing process of the optical device PD of FIG. 5. Referring to FIG. 6A, first, a SiGe (Silicon-Germanium) layer 620 is formed on a prepared N-type or P-type Si (Silicon) semiconductor substrate 610, or a chemical vapor deposition (CVD) or molecular beam epitaxial (MBE) method. Grows. For example, it grows so that it may be Si: 70% and Ge: 30%, and about 1 micrometer is suitable for the thickness of a crystal | crystallization, for example. Considering the lattice distortion occurring between the Si substrate 610 and the SiGe layer 620, a SiGeC structure including carbon (C) instead of the SiGe layer 620 is possible. The SiGe layer 620 or SiGeC layer has a narrow bandgap.

Next, as shown in FIG. 6B, a Si epitaxial layer 630 is deposited. For example, the thickness of the Si epitaxial layer 630 is 1 μm. Thereafter, as shown in FIG. 6C, a "deep p-well" is formed at a depth of about 2 μm over the SiGe layer 620 and the Si substrate 610, and the side trench and side “p-well” are formed. After forming the etc., a diode form necessary for N and P type impurity doping process may be formed in the Si epitaxial layer 630. In this case, MOSFETs M1 to M4 of FIG. 5 may also be formed in the Si epitaxial layer 630.

Most of the light incident on the B (Blue) pattern of the APS array is absorbed by the Si epitaxial layer 630. Light incident in a G (Geen) pattern is absorbed in both the Si epitaxial layer 630 and the narrow bandgap layer 620. Part of the light incident in the R (Red) pattern may be absorbed in the Si epitaxial layer 630, but most of the light is absorbed in the narrow bandgap layer 620.

SiGe crystals have a narrower bandgap width than Si crystals. Therefore, the absorption coefficient is large for a long wavelength such as R (Red), and accordingly, light of a long wavelength can be absorbed at a short distance. Since light can be absorbed at a short distance, the sensitivity does not decrease even if the depth of forming the "Deep P-well" is as shallow as 2 μm as shown in FIG. 6C. Therefore, when the pixel is scaled small, by forming the "Deep P-well" of the optical element PD in such a shallow position, it is possible to significantly reduce crosstalk with neighboring optical elements.

In essence, for the B (Blue) pattern optical device PD, the narrow bandgap layer 620 may be unnecessary. That is, in the arrangement of the narrow bandgap layer 620, in the long-wavelength patterns such as R (Red) and G (Green), the narrow-bandgap layer 620 is provided, and short-wavelength such as the B (Blue) pattern The pattern may be designed not to have the narrow bandgap layer 620.

7 is a timing diagram of signals for operating the pixel driving circuit 510 of FIG. 5. Referring to FIG. 7, the pixel circuit 510 of FIG. 5 operates according to the row select signal SEL, the reset control signal RX, and the transfer control signal TX. The row select signal SEL is activated at a logic high state once in a vertical scan period to select a corresponding row. The reset control signal RX is activated to a logic low state for a predetermined period of the active period of the row select signal SEL. The transfer control signal TX is activated to a logic high state for a predetermined period of the logic low state period of the reset control signal RX.

 For example, before the row select signal SEL is activated, the reset control signal RX is in a logic high state, and at this time, the power supply VDD is transmitted to the FD node through the reset transistor M2. Accordingly, the logic high signal for resetting the FD node is stably transmitted to the FD node.

On the other hand, the row select transistor M1 selectively or does not transfer the output of the source-follower transistor M3 to the output VRES / VSIG node according to the row select signal SEL. When the row select signal SEL is active, the reset control signal RX goes to a logic low level. At this time, the source-follower transistor M3 is in response to the reset control signal RX of the neighboring pixel transferred to the FD node. Operation to output a corresponding current proportional thereto. Accordingly, the row select transistor M1 receives the output of the source follower transistor M3 and is analog-digital as a reset signal VRES through the source terminal of the row select transistor M1 connected to the bias circuit 520. Read out to a converter (not shown).

The transfer transistor M4 selectively or does not transfer the optical device PD output to the FD node according to a transfer control signal TX. After the reset signal VRES is read, the transfer control signal TX is activated to a logic high state for a predetermined period, and thus the photoelectrically converted signal from the optical device PD is transferred to the FD node. When the transfer control signal TX changes to a logic low and the photoelectrically converted signal is transferred to the FD node, the source-follower transistor M3 operates to be proportional to the photoelectrically converted signal transferred to the FD node. Output the corresponding current. Accordingly, the row select transistor M1 receives the output of the source follower transistor M3 and is analog-digital as the image signal VSIG through the source terminal of the row select transistor M1 connected to the bias circuit 520. Read out to a converter (not shown).

By the operation of the pixel circuit 510, whenever the row selection signal SEL of FIG. 5 is activated in sequence in each row, corresponding reset signals VRES and image signals VSIG are applied to the pixels of each row. Outputs

The analog-digital converter (not shown) may operate in a CDS method. That is, the analog signal corresponding to the difference between the image signal VSIG and the output reset signal VRES may be converted into a digital signal and output. The digital signal converted as described above is output to a digital signal processor (not shown) and subjected to a predetermined interpolation process. In addition, the digital signal processor generates driving signals suitable for a corresponding resolution of a display device such as an LCD to drive the display device.

As described above, in the image sensor according to the exemplary embodiment of the present invention, the long wavelength light may be easily absorbed even at a shallow position from the semiconductor surface by the optical device PD having the narrow band gap.

As described above, optimal embodiments have been disclosed in the drawings and the specification. Although specific terms have been used herein, they are used only for the purpose of describing the present invention and are not intended to limit the scope of the invention as defined in the claims or the claims. Therefore, those skilled in the art will understand that various modifications and equivalent other embodiments are possible from this. Therefore, the true technical protection scope of the present invention will be defined by the technical spirit of the appended claims.

As described above, in the image sensor according to the present invention, the narrow bandgap optical element is applied to increase the absorption coefficient of the long wavelength light, thereby enabling scaling in the vertical direction. As a result, crosstalk between neighboring optical devices is reduced, thereby increasing the signal-to-noise ratio (SNR) of the image signal with respect to the reset signal, thereby improving the image quality displayed on the LCD.

Claims (13)

Optical elements; A transfer transistor operating according to a transfer control signal; A reset transistor operating according to the reset control signal; And A source-follower transistor that operates in accordance with the signal delivered to the FD node, The reset signal based on the signal transmitted to the FD node through the reset transistor and the image signal based on the signal transmitted from the optical device to the FD node by the transfer transistor are transmitted through the source-follower transistor. Output, And the optical device is formed to have a narrow bandgap semiconductor layer in a semiconductor substrate. The method of claim 1, wherein the narrow bandgap semiconductor layer is a SiGe layer, The SiGe layer is grown to be Si: 70% and Ge: 30%, the thickness of the pixel circuit of the image sensor, characterized in that 1μm. The pixel circuit of claim 1, wherein the narrow bandgap semiconductor layer is a SiGeC layer. The method of claim 1, And a row select transistor for selectively outputting or not outputting the source-follower transistor output in accordance with a row select signal. 5. The pixel circuit according to claim 4, wherein the reset signal and the image signal are output from the source follower transistor to the output node while the row select signal is activated. The gate electrode receives a row selection signal, one of the source / drain electrodes connected to a first node, and the other one of which is connected to an output node; The gate electrode receives a reset control signal, one of the source / drain electrodes connected to a first power supply, and the other of the gate / drain electrodes connected to a second node; A third MOSFET connected to the second node, one of the source / drain electrodes connected to the first power supply, and the other of the gate / drain electrodes connected to the first node; A fourth MOSFET receiving a transfer control signal, one side of the source / drain electrodes connected to the second node, and the other side connected to the third node; And An optical device for photoelectric conversion between a second power supply and the third node, And the optical device is formed to have a narrow bandgap semiconductor layer in a semiconductor substrate. The method of claim 6, wherein the narrow bandgap semiconductor layer is a SiGe layer, The SiGe layer is grown to be Si: 70% and Ge: 30%, the thickness of the pixel circuit of the image sensor, characterized in that 1μm. 7. The pixel circuit of claim 6, wherein the narrow bandgap semiconductor layer is a SiGeC layer. 7. The pixel circuit according to claim 6, wherein said pixel circuit forms an APS array of Bayer patterns. 10. The pixel circuit according to claim 9, wherein only photons corresponding to G and B patterns of the Bayer pattern have the narrow bandgap semiconductor layer. 10. The pixel circuit according to claim 9, wherein the optical device further has a silicon epitaxial layer on the narrow bandgap semiconductor layer, and a diode structure is formed in the silicon epitaxial layer. 12. The pixel circuit according to claim 11, wherein said first to fourth MOSFETs are formed in said silicon epitaxial layer. The reset circuit of claim 6, wherein the first power is reset based on a signal transmitted from the first power source to the second node in response to the reset control signal through the output node connected to a bias circuit when the row selection signal is activated. Outputting a signal and outputting an image signal based on a signal in which a photoelectrically converted signal from the optical device is transmitted to the second node in response to the transfer control signal.

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