KR100676834B1 - Level conversion circuit - Google Patents

Abstract

A MOS capacitor for receiving the sampling clock signal / CLK and the complementary clock signal CLK is provided at an input portion of the clocked inverter CIV which is activated after sampling the input signal IN and performs level conversion. The charge pump operation of the MOS capacitor 6 is executed in parallel with the activation of the clocked inverter. Accordingly, the power consumption and the area occupied by the level converting circuit for converting the voltage amplitude of the input signal are reduced without compromising high speed operability.

Sampling, Power Consumption, High Speed, Transistor, EL, Liquid Crystal, Driving Device

Description

LEVEL CONVERSION CIRCUIT}

1 is a diagram showing the configuration of a level converting circuit according to Embodiment 1 of the present invention.

FIG. 2A shows the configuration of the inverter shown in FIG. 1, and FIG. 2B is a diagram showing the structure of the clocked inverter shown in FIG. 1.

3 is a timing diagram illustrating an operation of the level conversion circuit shown in FIG. 1.

4 is a diagram showing the configuration of the level conversion circuit according to the second embodiment of the present invention.

FIG. 5 is a diagram for describing an operation timing margin of the level conversion circuit shown in FIG. 4.

FIG. 6 is a timing diagram showing the operation of the level conversion circuit shown in FIG.

FIG. 7 is a diagram illustrating an example of a configuration of a portion that generates the two-phase clock signal shown in FIG. 4.

8 is a diagram showing the configuration of the level conversion circuit according to the third embodiment of the present invention.

9 is a diagram showing the configuration of the level conversion circuit according to the fourth embodiment of the present invention.

FIG. 10 is a diagram showing the voltage amplitude of the clock signal shown in FIG.

Fig. 11 is a diagram showing the configuration of the level conversion circuit according to the fifth embodiment of the present invention.

FIG. 12 is a timing diagram showing an operation of the level conversion circuit shown in FIG.

Fig. 13 is a diagram showing the configuration of the level conversion circuit according to the sixth embodiment of the present invention.

14 is a diagram showing the configuration of the level conversion circuit according to the seventh embodiment of the present invention.

Fig. 15 is a diagram showing the configuration of the level conversion circuit according to the eighth embodiment of the present invention.

FIG. 16 is a diagram schematically showing the configuration of a serial / parallel conversion circuit having a level conversion function according to Embodiment 9 of the present invention.

FIG. 17 is a diagram specifically showing the configuration of the serial / parallel conversion circuit of the level conversion function shown in FIG.

18 is a timing diagram illustrating the operation of the circuit shown in FIG. 17.

Fig. 19 is a diagram showing a level conversion circuit of a modification of the ninth embodiment of the present invention.

20 is a diagram schematically showing the configuration of a serial / parallel conversion circuit having a level conversion function according to a tenth embodiment of the present invention.

FIG. 21 is a diagram specifically showing the configuration of the level conversion circuit, latch circuit, and shift latch circuit shown in FIG.

22 is a timing diagram illustrating the operation of the circuit shown in FIG. 20.

Fig. 23 is a diagram showing the configuration of the level conversion circuit of the modification of the tenth embodiment of the present invention.

FIG. 24 is a diagram schematically showing the configuration of the serial / parallel conversion circuit of the level conversion function according to the eleventh embodiment of the present invention.

FIG. 25 is a diagram specifically showing the configuration of the level conversion circuit, latch circuit, and shift latch circuit shown in FIG.

FIG. 26 is a timing diagram illustrating the operation of the circuit shown in FIG. 25.

Fig. 27 is a diagram showing the configuration of the level conversion circuit of the modification of the eleventh embodiment of the present invention.

28 is a diagram schematically showing another modification of the level conversion circuit according to the eleventh embodiment of the present invention.

29 is a timing diagram illustrating the operation of the circuit shown in FIG. 28.

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a level conversion circuit using an insulated gate field effect transistor (MOS transistor), and more particularly, to a level shift circuit having a latch function used in a display device such as a liquid crystal device and an electroluminescence (EL) device. It is about. More specifically, the present invention relates to a configuration of a circuit for latching and level shifting pixel data signals supplied to display pixels.

In a display device using a liquid crystal element or an organic EL (electroluminescence) element as a display pixel element, a level converting circuit is used to enlarge the signal amplitude. For example, in order to accurately drive a display pixel element in accordance with a display signal to perform gradation display, an amplitude of the image data signal is enlarged to generate a display signal and supply it to the pixel element.

In such a display device, it is generally required to reduce power consumption in order to prevent heat generation, and also to reduce power consumption when used for the purpose of using a battery of a portable device as a power source. The structure of the level conversion circuit which intends to reduce such power consumption is shown by prior document 1 (Unexamined-Japanese-Patent No. 2003-115758).

In the configuration shown in Patent Literature 1, the input signal is held in the first capacitor according to the sampling pulse, and after completion of the sampling, the MOS drive stage having the level conversion function is driven in accordance with the voltage held in the first capacitor. do. The second capacitor is charged in accordance with the output signal of the MOS drive stage to generate a level conversion signal. In the structure shown in this patent document 1, in addition to the consumption current reduction, level conversion of an input signal is aimed at with a small number of elements.

In addition, a level conversion circuit which intends to reduce power consumption is shown in prior document 2 (Japanese Patent Laid-Open No. 2002-358055). In the level converting circuit shown in this patent document 2, the current mirror input buffer circuit for comparing an input signal with a reference voltage is activated for the activation period of the vertical scan start instruction signal, The output signal is latched by a latch circuit having a level conversion function when the vertical scan start instruction signal is deactivated. The current mirror type input buffer circuit is operated for a minimum period of time necessary, and then the output signal is latched to the latch circuit, and the level conversion is performed by the latch circuit to reduce the current consumption.

In addition, a level conversion circuit for the purpose of realizing high-speed operation in addition to the reduction of power consumption is shown in the prior document 3 (Japanese Patent Laid-Open No. 2001-320268). In the structure shown in this prior document 3, an amplitude limited control signal is generated in accordance with the input clock signal, and the output drive stage is driven in accordance with the amplitude limited control signal. In the amplitude limitation, when the output drive stage is constituted by a CMOS inverter using the threshold constant voltage drop of the MOS transistor (insulated gate type field effect transistor), one of these drive transistors is in a strong on state and the other is in a weak on state. It is in a state. By simply controlling the degree of ON state of the output drive transistor, high speed operation is realized. In addition, it is possible to shorten the transition period of the potential level of the output node, to reduce the period in which the through current flows, and to reduce the power consumption.

Further, a configuration aimed at reducing the power consumption of the level conversion circuit for enlarging the signal amplitude in the image display device is shown in the prior document 4 (Japanese Patent Laid-Open No. 2002-251174). In the structure shown in this prior document 4, the gate of an output drive transistor is clamped by diode-connecting a MOS transistor, and an input signal is transmitted to the gate of this output drive transistor via a capacitor. The gate potential of the output drive transistor is changed by capacitive coupling by the capacitor, and the output drive transistor is driven in the on / off state at high speed, thereby reducing the through current and reducing the power consumption.

In a display device such as a liquid crystal display device, a thin film transistor (TFT) is used as the MOS transistor. In this case, in order to prevent deterioration of the characteristics of the display pixel element, a low temperature polysilicon TFT is used. Since such low-temperature polysilicon TFTs are only heat-treated at low temperatures and have poor crystal quality compared to MOS transistors using single-crystal polysilicon, the variation in threshold voltage is large and the channel resistance (on resistance) during conduction is also large. .

In the configuration shown in Document 1, during the level conversion operation, the output drive transistor is driven in accordance with the small amplitude input signal held in the first capacitor to discharge the voltage held in the second capacitor. Therefore, a problem arises in that the current driving force of the output drive transistor is small, the large amplitude level-converted signal held in the second capacitor can not be discharged at high speed, and the high speed operability is not guaranteed.

In the configuration shown in Document 2, in order to identify the voltage level of the input signal, a current mirror type buffer circuit is used, the reference voltage is compared with the input signal, an internal signal is generated according to the result of the comparison, and latched. Latch to the circuit. Therefore, there is a problem that the number of transistor elements of the input buffer circuit is large, and the occupied area cannot be reduced. In addition, when the threshold voltage of the transistor element fluctuates, the offset of the comparison stage of this current mirror type input buffer circuit cannot be compensated, and a problem arises in that an accurate input signal cannot be generated.

In the structure shown in the document 3, the gate potential of the transistor of the output drive stage which performs level conversion is level-shifted by the diode-connected MOS transistor, and the grade of the ON state of an output drive transistor is changed according to an input signal. . Therefore, in the output drive stage, both the charging and discharging drive transistors are in an on state, and a problem arises that a through current always flows.

In the structure shown in the document 4, the gate potential of the output drive transistor for level conversion is clamped by the diode-connected MOS transistor, and the gate potential of these drive transistors is changed by the capacitive coupling of an input signal. Therefore, at the node receiving the input signal, a capacitor must be provided for each of the high side drive transistor and the low side transistor, resulting in a problem that the load of the input signal is increased. In this document 4, as another configuration, there is shown a configuration for driving an internal output node by capacitive coupling of input signals. That is, a capacitive element for receiving an input signal is connected between the gate of the first drive transistor and the internal output node, and the internal output node is coupled to the input signal through the second drive transistor by an inverted signal of the input signal. have. Therefore, when skew occurs between the complementary input signals, the signal of the internal output node may be coupled to the input signal through the second drive transistor, and the internal output node may not be sufficiently charged. The problem arises that the signal cannot be generated.

An object of the present invention is to provide a level conversion circuit capable of converting a signal of small voltage amplitude into a signal of large voltage amplitude at high speed and low power consumption, and a series / parallel conversion circuit using the same.

The level conversion circuit according to the first aspect of the present invention is a first insulated gate of a first conductivity type that transmits an input signal provided to an input node to a first internal node in accordance with a first clock signal from a first clock input node. An insulated gate connected between the type field effect transistor and the second clock input node for inputting the second clock signal and the first internal node, and selectively forming capacitance according to the potential difference between the internal node and the second clock input node; MOS type capacitance element formed of the type field effect transistor and one of the first clock signal and the clock signal with respect to the first clock signal and the second clock signal selectively activated during non-conduction of the first insulated gate type field effect transistor And a clocked inverter that, upon activation, inverts the potential of the first internal node to generate a signal having a amplitude greater than that of the input signal to the second internal node.

A level converting circuit according to a second aspect of the present invention includes a first conductivity type insulated gate field effect transistor for transmitting an input signal to a first internal node in accordance with a clock signal from a first clock input node, and A second insulated gate field effect transistor of a first conductivity type which transfers a second clock signal supplied to the second clock input node to the second internal node according to the voltage of the first internal node, and a clock signal of the first clock input node. And a low driving circuit for driving the second internal node at a low voltage level of the low power supply node according to the clock signal of the in-phase, and a clock signal corresponding to the clock signals of the first and second clock input nodes and the clock signal of the in-phase clock signal. And a clocked inverter that is selectively activated accordingly and, upon activation, drives the third internal node in accordance with the signal of the second internal node.

The level converting circuit according to the third aspect of the present invention is a clocked inverter that is activated in response to a first clock signal and, upon activation, inverts the signal of the first node and transmits the signal to the second node. It is formed of a first insulated gate field effect transistor that conducts when activated, and transmits an input signal to the first node, and is connected between the first node and the third node and is formed of an insulated gate field effect transistor that, when conducting, And a MOS type capacitor configured to perform a charge pump operation in response to the first clock signal when the clocked inverter is activated.

In the invention according to the first aspect, the input signal is held in the MOS capacitor. Therefore, when the input signal is sampled, the operation as the capacitor element of the MOS capacitor is stopped, whereby the MOS capacitor capacitor holding voltage can be changed in accordance with the input signal at high speed, and high-speed level conversion can be realized. In addition, according to the charge voltage of the MOS type capacitor, the clocked inverter is driven, and the clocked inverter is driven only for the required period, so that the current consumption can be reduced. In addition, by supplying the clock signal of the second clock input node to the MOS capacitor, this holding voltage can be boosted by the charge pump operation, and the clocked inverter of the next stage can be driven reliably. The period represented by the through current at can be reduced, thus reducing the current consumption.

In the invention according to the second aspect of the present invention, an input signal is sampled, and a second clock signal is transmitted to the next stage clocked inverter in accordance with the sampling voltage, and the next stage clocked inverter transmits the transmitted signal. The internal node is being driven accordingly. By this second clock signal, the second MOS transistor can be operated as a MOS capacitor, and the gate potential thereof can be raised to change the potential of the internal output node at high speed.

According to the third aspect of the present invention, similarly to the invention of the first aspect, the input signal is held by the MOS capacitor, and the input signal is boosted by the charge pump operation of the MOS capacitor. Therefore, the level conversion can be performed by latching the input signal at a high speed. In addition, by using separate clock signals for the conduction control of the first insulated gate field effect transistor and the charge pump control of the MOS capacitor, the sampling timing of the input signal can be optimized, and the level conversion can be performed accurately with low current consumption. Can be.

The above and other objects, features, aspects and advantages of the present invention will become apparent from the following detailed description of the invention which is understood in connection with the accompanying drawings.

[Examples of the Invention]

(Example 1)

Fig. 1 is a diagram showing the configuration of the level converting circuit according to the first embodiment of the present invention. In Fig. 1, the level converting circuit is an N-channel MOS transistor (isolated gate type field effect transistor) which transfers the input signal IN provided to the input node DN5 to the internal node DN7 in accordance with the clock signal / CLK provided to the input node DN4. (5), an MOS type capacitor (hereinafter referred to as MOS capacitor) 6 coupled to the internal node DN7 and selectively forming capacitance in accordance with the clock signal CLK from the clock input node DN3, and the clock signal CLK and / CLK selectively activated according to / CLK, and when activated, a clocked inverter (CIV) for driving the internal output node DN6 in accordance with the signal of the internal node DN7, and an inverter for configuring a latch circuit for latching the signal voltage on the internal output node DN6. (7) and clocked inverter (8).

When this level conversion circuit is used for a display device (display panel), the input signal IN is a signal supplied from an external LSI (large scale integrated circuit chip) such as a driver IC, for example, between 0V and 3V. Is a signal that changes. The clock signals CLK and / CLK are formed in this display device and are changed between the reference voltage VSS and the power supply voltage VDD. This voltage VDD is a voltage level higher than the H level (logical high level) VIH of the input signal IN, and is a power supply voltage of this display device, for example, 5V. The voltage VSS is a reference voltage, for example, a ground voltage.

Clocked inverter CIV is a P-channel MOS transistor 1 and 2 connected in series between high side power supply node DN1 and internal output node DN6, and N connected in series between internal output node DN6 and low side power supply node DN2. Channel MOS transistors 3 and 4; The gate of the P-channel MOS transistor 1 is provided with a clock signal / CLK. The gates of the MOS transistors 2 and 3 are commonly connected to the internal node DN7. The gate of the N-channel MOS transistor 4 is provided with a clock signal CLK.

The MOS capacitor 6 is composed of N-channel MOS transistors, the gate of which is connected to the internal node DN7, and the source and drain nodes thereof are connected to the clock input node DN3. When the voltage level of the gate is higher than the voltage level of the source / drain node, the MOS capacitor 6 forms a channel between the source drains and functions as a capacitor. On the other hand, this MOS capacitor 6 has no channel formed when the difference between the gate voltage and the voltages of the source and drain is equal to or less than the threshold voltage, and simply, at the overlapping portion between the source, drain, and gate electrode. The dose of acts as the dose for internal node DN7.

Inverter 7 inverts the voltage of internal output node DN6 and transmits it to internal node DN8, and clocked inverter 8 inverts the signal on internal node DN8 and transmits it to internal output node DN6. The operating power supply voltages of these inverters 7 and clocked inverters 8 are the voltages VDD and VSS similarly to the clocked inverter CIV.

FIG. 2A is a diagram specifically showing the configuration of the inverter 7 shown in FIG. 1. As shown in FIG. 2A, the inverter 7 includes a P-channel MOS transistor PQ1 and an N-channel MOS transistor NQ1 connected between the high side power supply node DN1 and the low side power supply node DN2. That is, inverter 7 is comprised with the CMOS inverter which receives voltage VDD and VSS as an operation power supply voltage.

FIG. 2B is a diagram specifically showing the configuration of the clocked inverter 8 shown in FIG. 1. As shown in Fig. 2B, the clocked inverter 8 is connected in series between the P-channel MOS transistors PQ2 and PQ3 connected in series between the high-side power supply node DN1 and the output node, and between the output node and the low-side power supply node DN2. N-channel MOS transistors NQ2 and NQ3. At the gates of the MOS transistors PQ2 and NQ3, clock signals CLK and / CLK are provided, respectively. The gates of the MOS transistors PQ3 and NQ2 are interconnected and connected to the internal output node DN8 shown in FIG.

As shown in FIG. 2B, the clocked inverter 8 operates complementary to the clocked inverter CIV. Therefore, when the clocked inverter CIV is brought into the output high impedance state, the inverter latch composed of the inverter 7 and the clocked inverter 8 operates to latch the signal on the internal output node DN6. On the contrary, when the clocked inverter CIV is activated, the clocked inverter 8 is in an output high impedance state, and the internal output node DN6 is released from the latched state and driven by the clocked inverter CIV.

FIG. 3 is a signal waveform diagram showing the operation of the level conversion circuit shown in FIG. In Fig. 3, an example is shown in which an input signal is changed between 3V and 0V, and this voltage amplitude is converted into a signal in which a 3V signal is changed between 5V and 0V. That is, the 3V H level of the input signal IN is converted to the 5V H level and output to the internal output node DN6. For the L level, both the input signal IN and the internal signal (signal on node DN6) are 0V, and no level conversion is performed.

It is also assumed that the N-channel MOS transistors constituting the N-channel MOS transistors 3-5 and the MOS capacitor 6 have a threshold voltage of 2 V, and the P-channel MOS transistors 1 and 2 have a threshold voltage of -2 V. do. The value of the threshold voltage of this MOS transistor is the same also about the component of the inverter 7 and the clocked inverter 8.

At time t0, the input signal IN7 is at the H level (logical high level), the clock signal / CLK is at the H level, and the clock signal CLK is at the L level (logical low level). In this state, the MOS transistor 5 is turned on, and the H level of the input signal IN is transmitted to the internal node DN7. At this time, since the clock signal CLK is at the L level, the voltage difference between the internal node DN7 and the clock input node DN3 becomes 3V. Since the voltage difference between the internal node DN7 and the clock input node DN3 is larger than the threshold voltage (2V) of the MOS transistor constituting the MOS capacitor 6, a channel is formed in the MOS capacitor 6, and the MOS capacitor 6 is formed. The capacitance corresponding to the gate area of the MOS transistor to be formed is formed, and the H level of the input signal IN is held in the capacitance of the MOS capacitor 6.

The clocked inverter CIV has MOS transistors 1 and 4 in a non-conductive state, an inactive state, and an output high impedance state. Clocked inverter 8 is active, operating as an inverter, and the state of the cycle before internal output node DN6 is maintained. In Fig. 3, the state in which the signal of the H level is transmitted to and maintained in the internal output node DN6 in all cycles is displayed. Since internal output node DN6 is H level, internal node DN8 is L level of ground voltage level.

At time t1, the clock signal CLK rises to the H level after the clock signal / CLK falls to the L level. The voltage change 5V of the clock signal CLK is transmitted to the internal node DN7 by the charge pump operation of the MOS capacitor 6, and the voltage of the internal node DN7 rises by ΔVH. This voltage change amount ΔVH is expressed by the following equation (1).

ΔVH = (VCH-VCL) · C6H / (C6H + CST)... (One)

Here, VCH and VCL represent H level (5V) and L level (0V) of clock signals CLK and / CLK, respectively, C6H represents the capacitance value of MOS capacitor 6 at the time of channel formation, and CST is an internal node. The dose value of the parasitic dose (not shown) which exists in DN7 is shown. Therefore, (VCH-VCL) represents the voltage amplitudes of the clock signals CLK and / CLK, and the above formula (1) shows that the charge injected into the internal node DN7 by the MOS capacitor 6 is not shown in the MOS capacitor 6 and the figure. Distribution to parasitic doses.

For example, in said Formula (1), when C6H = CST is set, the said Formula (1) will be converted into the following Formula (2).

ΔVH = (VCH-VCL) · (1/2)... (2)

Under this condition, the voltage change amount [Delta] VH becomes 1/2 times (= 2.5 V) the voltage amplitude of the clock signal CLK. In this case, the voltage level of the internal node DN7 is 5.5V. This voltage level is a voltage level at which the P-channel MOS transistor 2 can be turned off and the N-channel MOS transistor 3 can be turned on in the clocked inverter CIV, similarly to an internal circuit operating at the power supply voltage VDD. It is possible to activate the CIV and to perform the operation of generating a two-value signal having an amplitude of 5V accurately.

In accordance with the voltage level of the internal node DN7, the voltage level of the internal output node DN6 becomes L level, and the inverter 7 causes the internal node DN8 to become H level. At this time, the clocked inverter 8 is in an inactive state and can drive the internal node DN6 at high speed according to the voltage level of the internal node DN7.

At time t2, the input signal IN changes from the H level to the L level. At this time t2, clock signals CLK and / CLK are at H level and L level, respectively, and clocked inverters CIV and 8 are in an active state and an inactive state, respectively. The time from this time t2 to the time t3 when the clock signal / CLK transitions to the H level becomes the setup time for latching the input signal IN to the level conversion circuit. In this setup period, the MOS transistor 5 is in an off state.

At the time t3, when the clock signal CLK falls to the L level, the charge pump operation caused by the capacitance of the MOS capacitor 6 also lowers the voltage level of the internal node DN7, and the voltage level is the H level of the input signal IN. , 3V.

When the clock signal / CLK becomes H level after the clock signal CLK falls to the L level, the MOS transistor 5 is turned on, the input signal IN is transmitted to the internal node DN7, and the voltage level of the internal node DN7 is the input signal IN. The voltage level (0V) is equal to the L level. At this time, the clock signal CLK is L level, the voltage level of the clock input node DN3 is the ground voltage level, the voltage level of the internal node DN7 and the clock input node DN3 is the same, and in the MOS capacitor 6, no channel is formed. In this state, the capacitance between the internal node DN7 and the clock input node DN3 is only a small amount formed at the overlapping portion of the gate and drain / source region of the transistor constituting the MOS capacitor 6.

Also, as the clock signals CLK and / CLK fall and rise, the clocked inverter CIV becomes inactive and becomes an output high impedance state. In addition, the clocked inverter 8 is activated, and inverts the H level signal of the internal node DN8 to the output node DN6, and the internal output node DN6 is brought to the L level by a latch circuit composed of the inverter 7 and the clocked inverter 8. maintain.

At time t4, the clock signal CLK rises to the H level after the clock signal / CLK falls to the L level. At this time, in the MOS capacitor 6, no MOS capacitor is formed. Only a small capacitance exists between the gate and the source / drain of the MOS transistor constituting the MOS capacitor 6. Even when the internal node DN7 is in a floating state and the clock signal CLK is at the H level, the charge pump operation is simply performed by this minute capacitance, and the voltage level of the internal node DN7 is changed by ΔVL. If the voltage change amount DELTA VL is sufficiently smaller than 2V of the threshold voltage of the MOS transistor 3, the MOS transistor 3 remains in the off state, and the internal node DN7 is judged by the clocked inverter CIV if it is substantially at the L level.

When the clocked inverter CIV is activated as the clock signal / CLK falls and the clock signal CLK rises, the internal output node DN6 is driven according to the voltage level of the internal node DN7, and the voltage level of the internal output node DN6 is H level. The internal node DN8 is driven to the L level by the inverter 7. At this time, the clocked inverter 8 is in an inactive state, and the internal output node DN6 is driven by the clocked inverter CIV at high speed.

At time t5, the input signal IN changes from the L level to the H level. In this state, the clock signal / CLK is at the L level, the MOS transistor 5 is in the off state, and the internal node DN7 is maintained at the L level (voltage DELTA VL level). The time from this time t5 until the time t6 at which the clock signal / CLK rises to the H level becomes the setup time of the input signal IN.

At the time t6, when the clock signal CLK becomes L level, the clocked inverter CIV is driven in an inactive state, and the clock signal / CLK rises to the H level, the MOS transistor 5 is turned on, and the input signal IN is It is passed to internal node DN7. Therefore, the voltage level of the internal node DN7 becomes the voltage level (3V) corresponding to the H level of the input signal IN. Thereafter, the same operation as that from the time t0 is performed.

At this time t6, when the clock signal CLK falls, the voltage level of the internal node DN7 is once lowered to the ground voltage level and then driven to the H level (VIH) level of the input signal IN in accordance with the input signal IN. .

As described above, the MOS capacitor 6 is connected to the internal node DN7, the input signal IN is transmitted to the internal node DN7, the internal node DN7 is floated, and the MOS capacitor 6 is driven by the clock signal to charge pump operation. Is doing. Therefore, the voltage level of the internal node DN7 can be stepped up accurately to the voltage level at which the clocked inverter CIV having the internal power supply voltage VDD as the operating power supply voltage is normally operated. In the step-up operation of the internal node, the charge pump operation of the MOS capacitor is simply used, and no current consumption occurs. Similarly, when the internal node DN7 is driven to the L level, the formation of the MOS capacitor is stopped, and the voltage level of the internal node can be changed at high speed. Therefore, the internal signal is generated by level converting the input signal at high speed. can do.

(Example 2)

4 is a diagram showing the configuration of the level conversion circuit according to the second embodiment of the present invention. The configuration of the level conversion circuit shown in FIG. 4 differs from the level conversion circuit shown in FIG. 1 in the following points. That is, the clock signal / CLK is provided to the low-side power supply node DN2 of the clocked inverter CIV instead of the reference voltage (ground voltage VSS). The other configuration of the level conversion circuit shown in FIG. 4 is the same as that of the level conversion circuit shown in FIG. 1, and the same reference numerals are attached to corresponding parts, and detailed description thereof is omitted.

In the level converting circuit shown in FIG. 4, the clock signal CLK changes more slowly than the clock signal CLK.

FIG. 5 is a signal waveform diagram showing the operation of the level conversion circuit shown in FIG. 4 when the clock skew is large. As shown in Fig. 5, it is assumed that the input signal IN is at the L level (0V), the clock signal CLK is at the H level, and the clock signal / CLK is at the L level. At this time, the state held at the level of the boosted voltage (3V + ΔVH) is further considered in the internal node DN7.

Consider a state where the clock signal CLK has fallen from the H level to the L level when the clock signal / CLK is at the L level at time ta. At this time, since the MOS transistor 5 is in the off state, the charge pump operation of the MOS capacitor 6 lowers the voltage level of the internal node DN7 to the H level (3V) of the input signal IN. Since the clock signal / CLK is at the L level, the P-channel MOS transistor 1 is turned on in the clocked inverter CIV. When the power supply voltage VDD is 5V, the voltage between the gate source of the MOS transistor 2 becomes -2V. Therefore, when the variation in the threshold voltage of the MOS transistor 2 is large, for example, -1.5 V, the MOS transistor 2 conducts, the internal node DN6 is charged, and the voltage level rises. At this time, when the inverter 7 is operated and the internal node DN8 is driven to the L level in accordance with the voltage level of the internal output node DN6, in the clocked inverter 8, the P-channel MOS transistor for charging is supplied in accordance with the L level of the clock signal CLK. On, the internal output node DN6 is driven to H level.

At the time t3, when the clock signal / CLK rises to the H level, the clocked inverter CIV is deactivated and the output high impedance state is entered. At this time, even when the internal node DN7 is driven to the L level (ground voltage level) by the input signal IN provided through the MOS transistor 5, the clocked inverter CIV is inactive and the internal node DN6 is maintained at the H level. . Therefore, precisely, since the H level is output from the internal output node DN6 which should maintain the L level, malfunction occurs. This skew of the clock signal causes the clock signal CLK to fall lower than the clock signal / CLK in order to prevent the timing margin of the clock signal from decreasing.

FIG. 6 is a signal waveform diagram showing the operation of the level conversion circuit shown in FIG. Hereinafter, with reference to FIG. 6, the operation | movement of the level conversion circuit shown in FIG. 4 is demonstrated.

From time t0 to time t2, an operation similar to the signal waveform shown in FIG. 3 is first performed. That is, at time t2, the input signal IN is lowered from the H level to the L level, and the input signal IN is set up.

At this time, the internal node DN7 is the voltage level of the boosted voltage 3V + ΔVH, the internal output node DN6 is L level, and the internal node DN8 is H level.

At time t3, the internal clock signal / CLK rises from the L level to the H level. At this time, the clock signal CLK is at the H level. Therefore, the MOS transistor 5 is turned on, and the internal node DN7 is driven at the ground voltage level low in accordance with the input signal IN. In this operation, the clock signals CA K and / CLK are all at the H level, and the MOS transistor 4 has the same gate and source potentials and maintains an off state. The MOS transistor 3 also maintains the off state in accordance with the voltage level of the internal node DN7. In addition, the P-channel MOS transistor 1 is turned off. Therefore, even if the clocked inverter CIV becomes inactive during the period when both the clock signals CLK and / CLK are at the H level, and the voltage level of the internal node DN7 decreases, the internal output node DN6 is not affected by the L level. Keep it.

At time t3a, clock signal CLK falls to L level. Thus, the MOS transistor 4 is in a deep off state. The internal node DN7 is coupled to the input node DN5, and even if this clock signal CLK falls, the internal node DN7 maintains the same voltage level as that of the input signal IN.

At time t4, the clock signal / CLK drops from the H level to the L level, after which the clock signal CLK rises from the L level to the H level. At this time, in the clocked inverter CIV, when the clock signal CLK becomes H level, the clock signal / CLK of the low-side power supply node DN2 is L level, and the clocked inverter CIV is activated. However, since the voltage level of the internal node DN7 is L level, and no capacitance is formed in the MOS capacitor 6, the voltage level of the internal node DN7 rises by the voltage DELTA VL and maintains the L level. In response to the fall of clock signal / CLK at time t4, clocked inverter CIV is activated and drives internal output node DN6 to H level (5V).

At time t5, the input signal IN rises from the L level to the H level.

At time t6, the clock signal / CLK rises from the L level to the H level. At this time, the clock signal CLK maintains the H level. The clock signal CLK drops to L level at time t6a. Between the time t6 and the time t6a, in the clocked inverter CIV, the MOS transistor 4 maintains the off state. Therefore, even when the voltage level of the internal node DN7 rises to the voltage level of 3V in accordance with the H level of the input signal IN, and the MOS transistor 3 is in a conductive state, the discharge path in the clocked inverter CIV is blocked, so the internal output The voltage level of the node DN6 maintains the H level.

When the clock signal CLK falls to the L level at time t6a, in the clocked inverter CIV, the MOS transistor 4 is turned off and the discharge path is reliably cut off.

Therefore, by changing the clock signal CLK slower than the clock signal / CLK, it is possible to accurately sample the input signal IN, perform level conversion, and generate an internal signal. Here, sampling represents an operation of latching and latching an input signal. In other words, if the condition that the clock signal CLK is changed slower than the clock signal / CLK is satisfied, the correct level conversion operation and the output of the level conversion signal are guaranteed, so that the level conversion circuit shown in Fig. 4 can increase the timing margin. have.

In order for the MOS capacitor 6 to perform the charge pump operation to change the voltage level, it is required that the MOS transistor 5 is turned off and the internal node DN7 is kept in the floating state. Therefore, the clock signal CLK rises to the H level after the clock signal / CLK falls, whereby the MOS capacitor 6 can be subjected to the boost operation by the charge pump operation.

Fig. 7 is a diagram showing an example of the configuration of the portion that generates the clock signal in the second embodiment of the present invention. In FIG. 7, the clock signal generator includes, as an example, cascaded inverters IV1-IV4 which are paired means (four stages in FIG. 7) for receiving the main clock signal MCLK. A complementary clock signal / CLK is generated from the first stage inverter IV1, and a clock signal CLK is generated from the inverter stage IV4 of the final stage.

The main clock signal MCLK is a clock signal supplied from the outside, and defines a clock cycle to which the input signal IN is supplied. In the configuration of the clock signal generation circuit shown in FIG. 7, the clock signal / CLK is delayed by the delay time of the inverters IV2-IV4 and inverted to generate the clock signal CLK. Therefore, the clock signal CLK can always be changed after the clock signal / CLK changes, and the level conversion of the input signal IN can be performed correctly.

At this time, the clock signals CLK and / CLK may be generated by performing phase adjustment using a circuit such as a PLL (phase synchronization circuit).

As described above, according to the second embodiment of the present invention, the sampling timing (timing for latching and latching the input signal; the MOS transistor 5 is turned off) is supplied to the low-side power node of the clocked inverter that performs level conversion of the input signal. The timing margin of the clock signal of the level conversion circuit can be increased, and the internal signal can be generated by latching the input signal to perform level conversion.

(Example 3)

Fig. 8 is a diagram showing the configuration of the level converting circuit according to the third embodiment of the present invention. The level conversion circuit shown in FIG. 8 is different from the level conversion circuit shown in FIG. 1 or 4 in the following points. That is, in the clocked inverter CIV, the gate of the P-channel MOS transistor 1 connected to the high side power supply node DN1 is clocked into the gate of the P-channel MOS transistor 2 connected to the internal node DN7 and connected to the internal output node DN6. Signal / CLK is provided. Similarly, the clock signal CLK is provided to the gate of the channel MOS transistor 3, and the gate of the N-channel MOS transistor 4 connected to the low side power supply node DN2 is connected to the internal node DN7. The low side power supply node DN2 is provided with a reference voltage VSS or a clock signal / CLK. The other configuration of the level conversion circuit shown in FIG. 8 is the same as that of the level conversion circuit shown in FIG. 1 or 4, and the same reference numerals are attached to corresponding parts, and detailed description thereof is omitted.

That is, in this clocked inverter CIV, clock signals / CLK and CLK are supplied to the gates of the MOS transistors 2 and 3 connected to the internal output node DN6. The clock signal / CLK is at the H level, the clock signal CLK is at the L level, and during the operation period for inputting the input signal IN, the MOS transistors 2 and 3 are in an off state. Therefore, the capacitive coupling between the nodes DN6 and DN7 is sufficiently suppressed, and it is possible to suppress that the change in the voltage level of the internal node DN7 affects the voltage level of the internal output node DN6.

After sampling, even when the internal node DN6 is in a floating state, even if the voltage level of the internal output node DN6 is changed by the clocked inverter CIV, the capacitive coupling of the nodes DN7 and DN6 through the parasitic capacitances 1 and 4 of the MOS transistor is maintained. It is possible to suppress and accurately maintain the voltage level of the internal node DN7 at the voltage level according to the sampled input signal.

Further, when the MOS transistors 2 and 3 are turned off to the internal output node DN6, only their drain junction capacitances are connected, and the load when the clocked inverter CIV of the internal output node DN6 is deactivated can be reduced. The clocked inverter 8 can drive the internal output node DN6 at high speed.

As described above, according to the third embodiment of the present invention, a MOS transistor for receiving a clock signal at a gate is connected to an internal output node of a clocked inverter for level conversion, and the MOS of the clocked inverter CIV for level conversion is connected. Capacitive coupling between internal nodes through the transistor can be reduced, and the internal node can be stably maintained at a voltage level according to the sampled input signal.

(Example 4)

9 is a diagram showing the configuration of the level conversion circuit according to the fourth embodiment of the present invention. The level conversion circuit shown in FIG. 9 is different from the level conversion circuit shown in FIG. 8 in the following points. That is, the clock signal / CLKK is provided to the gate of the N-channel MOS transistor 5 for sampling through the clock input node DN4a. The H level of the clock signal / CLKK is a voltage level higher than the H level of the clock signal / CLK. The other configuration of the level conversion circuit shown in FIG. 9 is the same as that of the level conversion circuit shown in FIG. 8, and the same reference numerals are attached to corresponding parts, and detailed description thereof is omitted.

When the threshold voltage is increased due to a change in the threshold voltage, the MOS transistor 5 generates a threshold voltage loss at the H level of the clock signal / CLK, and can transmit the input signal IN to the internal node DN6 at 100%. There is a possibility to disappear. In order to prevent this threshold voltage loss from occurring, as shown in FIG. 10, the N-channel MOS transistor for sampling the clock signal / CLKK whose H level is sufficiently high to compensate for the variation in the threshold voltage. To 5 gates. Even if the threshold voltage of the MOS transistor 5 fluctuates, the input signal IN can be reliably transmitted to the internal node DN6.

At this time, when a large amplitude clock signal / CLKK is used, the large amplitude clock signal / CLKK may be provided to the low-side power supply node DN2 of the clocked inverter CIV. It is not necessary to supply the ground voltage to the low-side power node DN2, and the freedom of layout can be improved.

At this time, in the configuration of the level conversion circuit shown in Fig. 9, MOS transistors 2 and 3 which receive the clock signals / CLK and CLK to the gate are connected to the internal output node DN6. However, the structure using this large amplitude clock signal / CLKK may be used in the structure shown in FIG.

As described above, according to the fourth embodiment of the present invention, a large amplitude clock signal is provided to the gate of the MOS transistor for sampling, and even if the threshold voltage fluctuates, the threshold voltage loss is certainly not followed. , Input signal IN can be transmitted to internal node.

(Example 5)

Fig. 11 is a diagram showing the configuration of the level conversion circuit according to the fifth embodiment of the present invention. The level converting circuit shown in FIG. 11 selectively transfers the clock signal CLK to the input node DN7 of the internal node clock inverter CIV in accordance with the charging voltage of the MOS capacitor 6. That is, the level converting circuit shown in FIG. 11 includes an N-channel MOS transistor 5 which transfers the input signal IN provided to the input node DN5 to the internal node DN9 in accordance with the clock signal / CLK of the beam from the clock input node DN4, and the clock input. MOS capacitor 6 which selectively forms a capacitance according to the potential difference between clock signal CLK of node DN3 and internal node DN9, and N which selectively transfers clock signal CLK on clock input node DN3 to internal node DN7 according to the voltage on internal node DN9. The channel MOS transistor 9, the N-channel MOS transistor 10 which drives the internal node DN7 at the voltage level of the low-side power supply node DN2 in accordance with the clock signal / CLK, and the internal output node DN6 by level conversion in accordance with the signal on the internal node DN7 And a clocked inverter CIV which constitutes a clocked inverter CIV to be transmitted to and a latch circuit for latching a signal on the internal output node DN6.

The clocked inverter CIV has the configuration of any of the clocked inverters of the first to fourth embodiments, and is activated when the clock signals CLK and / CLK are at the H level and the L level, respectively, in accordance with the signal of the internal node DN7. Drive the internal output node DN6. The clocked inverter CIV becomes inactive when the clock signals CLK and / CLK are at the L level and the H level, respectively, and becomes an output high impedance state.

The amplitudes of the clock signals CLK and / CLK are larger than the input signal IN, respectively. First, the relationship between the voltage amplitudes as in the first to fourth embodiments is established between the clock signals CLK and / CLK and the input signal IN.

The reference voltage VSS is provided to the source node DN2a of the N-channel MOS transistor 10 which functions as a low drive circuit for driving the internal node DN7 to L level. As described later, a clock signal may be provided to this source node DN2a.

The latching operations by the clocked inverters 8 and 7 are the same as those described in the first to fourth embodiments.

FIG. 12 is a signal waveform diagram showing the operation of the level conversion circuit shown in FIG. 12, the operation of the level converting circuit shown in FIG. 11 will be described.

Now, at time t10, it is assumed that the input signal IN is at the H level (3 V), the clock signal / CLK is at the H level (5 V), and the clock signal CLK is at the L level (0 V). In this state, the MOS transistor 5 is in the on state, and the internal node DN9 receives the input signal IN and becomes H level (3V). The clock signal CLK is at L level, the MOS transistor 9 is conducting, and the L level (ground voltage level) is transmitted to the internal node DN7. The clocked inverter CIV is in an inactive state, and the internal output node DN6 is maintained at the H level (5V) by the inverter 7 and the clocked inverter 8.

At time t11, clock signal / CLK becomes L level, and then clock signal CLK is raised to H level. MOS transistor 5 is turned off and internal node DN9 is in a floating state. At this time, in the MOS capacitor 6, a channel is formed, operating as a MOS capacitor, and in response to the rise of the clock signal CLK, charge is supplied to the internal node DN9 by charge pump operation, and the voltage level of the internal node N9 is increased. , ΔVH rises. The voltage level of the node DN9 due to ΔVH is sufficiently higher than the H level of the clock signal CLK by the increase of the voltage, the MOS transistor 9 is turned on, and the clock signal CLK of the H level is transferred to the internal node DN7. The voltage level of the internal node DN7 becomes H level. At this time, the MOS transistor 10 is in an off state. Since the clocked inverter CIV is in the active state, the L level signal is transmitted to the internal output node DN6 in accordance with the H level signal of the internal node DN7.

At time t12, the input signal IN becomes L level. At this time, the clock signal / CLK is at the L level, the MOS transistor 5 is in the off state, and the setup for the sampling operation of the input signal IN is performed.

At time t13, clock signal / CLK becomes H level, input signal IN of input node DN5 is transmitted to internal node DN9, and voltage level of internal node DN9 becomes L level equal to input signal IN. In response to the rise of the clock signal / CLK, the MOS transistor 10 is turned on, and the internal node DN7 is discharged to the ground voltage VSS level. When the clock signal CLK falls, the MOS transistor 5 is in the on state and the internal node DN9 is not in the floating state. Therefore, the charge pump operation by the MOS capacitor 6 is not performed, and the internal node DN9 is the input signal. It is maintained at the L level of IN.

In this state, the clocked inverter CIV becomes inactive, the internal node DN7 and the internal output node DN6 are separated, and the internal node DN6 is maintained at the L level.

At time t14, the clock signal / CLK drops to L level, and then the clock signal CLK becomes H level. At this time, the internal node DN9 is at the L level, and no channel is formed in the MOS capacitor 6. Therefore, in response to the rise of the clock signal CLK, the parasitic capacitance of the MOS capacitor 6 causes the voltage level of the internal node DN9 to rise by ΔVL. However, this voltage DELTA VL is sufficiently smaller than the threshold voltage of the MOS transistor 9, and the MOS transistor 9 maintains the off state. The internal node DN7 is at the L level, and the charging operation of the clocked inverter CIV is activated in response to the fall of the clock signal / CLK, and the final output node DN6 is driven at the H level of 5V.

At time t15, again, due to the setup of the input signal IN, the input signal IN is raised from the L level to the H level.

At time t16, the clock signal / CLK becomes H level and sampling of the input signal IN is started. Thereafter, the operation from time t10 is repeated.

In the level conversion circuit shown in Fig. 11, the node DN9 is connected to the gate of the MOS transistor 9, and the parasitic capacitance of the internal node DN9 can be reduced. Therefore, first, the value of parasitic capacitance CST in Equation (1) can be reduced, and the voltage increase amount ΔVH can be increased, and the input voltage DN7 of the clocked inverter CIV can be reliably corrected with the signal of the power supply voltage VDD level. I can deliver it.

At this time, in the configuration of the level conversion circuit shown in Fig. 11, a large amplitude clock signal / CLKK may be provided to the gate of the MOS transistor 5. The clock signal CLK may be provided to the source node DN2a of the MOS transistor 10 constituting the low driving circuit. When the internal node DN7 is discharged to the L level, the clock signal / CLK is at the H level, the clock signal CLK is at the L level, and the internal node DN7 can be surely driven to the L level. At this time, it is required to supply the clock signal / CLK to the low-side power supply node DN2 of the clocked inverter CIV (see Fig. 4; to reliably block the discharge path).

As described above, according to the fifth embodiment of the present invention, the MOS transistor 9 is driven in accordance with the charging voltage of the MOS capacitor 6 boosting the sampled input signal to transfer the clock signal to the clocked inverter CIV through the internal node. . Therefore, the parasitic capacitance of the internal node DN9 to which this MOS capacitor 6 is connected can be reduced, the step-up operation of the sampled input signal can be efficiently performed, and the high-speed, level-converted signal can be transferred to the clocked inverter. Can be.

(Example 6)

Fig. 13 is a diagram showing the configuration of the level conversion circuit according to the sixth embodiment of the present invention. The level conversion circuit shown in FIG. 13 differs from the configuration of the level conversion circuit shown in FIG. 11 in the following points. That is, in the level conversion circuit shown in FIG. 13, the source / drain node of the MOS transistors constituting the MOS capacitor 6 is connected to the internal node DN7 connected to the input of the clocked inverter CIV. The other configuration of the level conversion circuit shown in FIG. 13 is the same as that of the level conversion circuit shown in FIG. 11, and the same reference numerals are attached to corresponding parts, and detailed description thereof is omitted.

In the configuration of the level conversion circuit shown in Fig. 13, the clock signal / CLK becomes L level while the internal node DN9 is at the H level (3 V) of the input signal IN, and then the clock signal CLK is brought to the H level. When the MOS transistor 9 is in a weakly ON state, the clock signal CLK is transmitted to the internal node DN7, and the voltage level of the internal node DN7 rises. As the voltage level of the internal node DN7 rises, the voltage level of the internal node DN9 increases due to the capacitive coupling of the MOS capacitor 6, and the MOS transistor 9 becomes deeper on, and the H level of the clock signal CLK is increased. Is passed to internal node DN7. Therefore, the positive feedback operation of the MOS capacitor 6 makes it possible to increase the voltage level of the internal node DN7 at high speed.

When the internal node DN9 is at the L level, the MOS transistor 9 remains off and the internal node DN7 maintains the floating level at the L level even when the clock signal CLK rises to the H level.

Since the clock signal for driving the MOS capacitor 6 is not used in the configuration of the level conversion circuit shown in FIG. 13, wiring of the clock signal to the MOS capacitor 6 becomes unnecessary, and layout design becomes easy.

(Example 7)

Fig. 14 is a diagram showing the configuration of the level conversion circuit according to the seventh embodiment of the present invention. The configuration of the level conversion circuit shown in FIG. 14 differs from the level conversion circuit shown in FIGS. 11 and 13 in the following points. That is, the MOS capacitor 6 is not installed. In order to operate the MOS transistor 9 whose gate is connected to the internal node DN9 as the MOS capacitor, an N-channel MOS transistor 9w whose channel width is sufficiently large is used. The other configuration of the level conversion circuit shown in Fig. 14 is the same as that of the level conversion circuit shown in Figs. 11 and 13, and the same reference numerals are attached to corresponding parts, and the detailed description thereof is omitted.

In the level conversion circuit shown in Fig. 14, when the internal node DN9 is at the H level, and the clock signal CLK is at the H level after the clock signal / CLK is at the L level, a channel is formed in the MOS transistor 9w. Due to the capacitance between the channel region and the gate, the voltage level of the internal node DN9 increases, and the clock signal CLK of the H level is transmitted to the internal node DN7. In other words, using the self-bootstrap action of the MOS transistor 9w, the voltage level of the internal node DN9 is increased with the rise of the clock signal CLK, and the clock signal CLK is increased without the loss of the threshold voltage of the MOS transistor 9w. Pass to node DN7.

When the internal node DN9 is at the L level, the MOS transistor 9w is in an off state and even if the clock signal CLK is raised, the voltage level of the internal node DN9 is only slightly increased by the capacitance between the gate drains of the MOS transistor 9w. Transistor 9w remains off and internal node DN7 remains at L level.

In the configuration of the level conversion circuit shown in Fig. 14, the MOS transistor 9w for transmitting the signal after the level conversion is acted as a MOS capacitor, and there is no need to provide another boosting MOS capacitor, and the layout area is reduced, resulting in a layout. The degree of freedom is improved. In addition, the channel width of the MOS transistor 9w is large, the current driving force is increased, and the internal node DN7 can be driven at a high level at high speed.

(Example 8)

Fig. 15 is a diagram showing the configuration of the level conversion circuit according to the eighth embodiment of the present invention. In the level conversion circuit shown in FIG. 15, the configuration of the row drive circuit for driving the internal node DN7 at the L level is different from the configuration shown in FIG. That is, as this low drive circuit, a P-channel MOS transistor 11 connected between the power supply node DN1 and the internal node DN10 and receiving a clock signal CLK from the clock input node DN3 at its gate, the internal node DN10, and the low side power supply. An N-channel MOS transistor 12 is further provided which is connected between the nodes DN2b and whose gate is connected to the internal node DN7. The gate of the MOS transistor 10 is connected to the internal node DN10.

The other configuration of the level conversion circuit shown in FIG. 15 is the same as that of the level conversion circuit shown in FIG. 14, and the same reference numerals are attached to corresponding parts, and detailed description thereof is omitted.

In the configuration of the level conversion circuit shown in Fig. 15, when the clock signal CLK is at the L level, the MOS transistor 11 is turned on and the internal node DN10 is driven to the H level. Therefore, the MOS transistor 10 is turned on, and the internal node DN7 is driven to the voltage level on the low side power supply node DN2a, that is, the ground voltage VSS level. Since this internal node DN7 is connected to the low-side power supply node DN2a via the MOS transistor 10, when the clock signal CLK is at the L level, the internal node DN7 can be prevented from floating and noise is prevented from the internal node DN7. Can be prevented from overlapping.

When the clock signal CLK is at the L level, the clock signal / CLK is at the H level, and the input signal IN is transmitted to the internal node DN9. After the clock signal / CLK falls to the L level and the internal node DN9 becomes the floating state, the clock signal CLK rises to the H level. Therefore, the MOS transistor 11 is turned off. When the input signal IN is at the H level, the voltage level on the internal node DN9 rises in response to the rise of this clock signal CLK, so that the voltage level of the internal node DN7 also rises to the H level (5V level). As the voltage level of the internal node DN7 rises, the MOS transistor 12 transitions to the on state, the low level drive of the internal node DN10, and the MOS transistor 10 is driven to the off state. Therefore, it is possible to level-convert the sampled input signal IN and transfer it to the internal node DN7.

When the sampled input signal IN is at L level, the MOS transistor 9w is in an off state, and the clock signal CLK is not transmitted to the internal node DN7 through the MOS transistor 9w. In this state, the MOS transistor 12 is in the off state, the MOS transistor 10 is in the on state, and the internal node DN7 is similarly maintained at the voltage VSS level on the low side power supply node DN2a. Therefore, even in this state, the internal node DN7 can be prevented from floating, and the internal node DN7 can be stably maintained at the ground voltage level.

In this configuration, when the clock signal CLK is provided to the low-side power node DN2a, when the internal node DN7 is at the L level, the clock signal CLK at the H level is transmitted through the MOS transistor 10, and the voltage level of the internal node DN7 is provided. There is a possibility of this falsification. Therefore, in the structure shown in FIG. 15, the low side power supply node DN2a is maintained at the reference voltage VSS level.

At this time, in the level conversion circuit shown in Fig. 15, a boosting MOS capacitor may be connected to the internal node DN9.

As described above, according to the seventh embodiment of the present invention, when the L level signal is transmitted to the input node DN7 of the clocked inverter CIV by using the low driving circuit, the node DN7 is kept at the low impedance at the L level, It is possible to prevent the potential rise of the internal node DN7 due to this, thereby preventing the malfunction of the clocked inverter CIV.

(Example 9)

Fig. 16 is a diagram schematically showing the configuration of the serial / parallel conversion circuit of the level conversion function according to the ninth embodiment of the present invention. In Fig. 16, a serial / parallel conversion circuit having a level conversion function includes a level conversion circuit 20 for sampling an input signal IN according to clock signals / CLK and CLK, and converting and outputting a voltage level. A latch circuit 22 for latching the output signal of the latch signal when the clock signal / CLK is at the H level, and activated when the clock signal CLK is at the H level, and transmitting and latching the latch signal of the latch circuit 22. A shift latch circuit which is activated when the latch circuit 24 and the clock signal / CLK are at the H level, and shifts and latches the output signal of the shift latch circuit 24 upon activation to generate the output pixel signals / OTD and OTD. (26), the level converting circuit 30 which samples the input signal IN according to the clock signals CLK and / CLK, and performs level conversion and outputs it, and is activated when the clock signal / CLK is at the H level. To transmit and latch the output signal of the circuit 30 And a shift latch circuit 32 for generating output pixel signals OTE and / OTE.

The level converting circuits 20 and 30 operate complementarily, and these have any of the configurations of the level converting circuits shown in the first to eighth embodiments. The level conversion circuit 20 samples the input signal IN when the clock signal / CLK is at the H level, and performs level conversion of the sampled input signal when the clock signal CLK is at the H level. On the other hand, the level conversion circuit 30 samples the input signal IN when the clock signal CLK is at the H level, and generates a level conversion signal by performing level conversion of the sampled input signal when the clock signal / CLK is at the H level.

The input signal IN is supplied at a frequency twice the frequencies of the clock signals CLK and / CLK. When the clock signal CLK is at the H level, the level conversion circuit 30 performs a sampling operation. When the clock signal / CLK is at the H level, the level conversion circuit 20 performs a sampling operation. From the shift latch circuits 26 and 32, the pixel signal is output in parallel when the clock signal CLK is at the H level. Therefore, in the serial / parallel conversion circuit of the level conversion function shown in FIG. 16, the input signal IN is divided by the frequency of 1/2 times and output. This lowers the operating frequency in the circuit of the next stage and increases the operating margin.

FIG. 17 is a diagram showing an example of the configuration of the serial / parallel conversion circuit of the level conversion function shown in FIG. In FIG. 17, the level converting circuit 20 has the same configuration as that of the level converting circuit shown in FIG. Is raised to the H level, the MOS capacitor 6a which performs charge pump operation to supply charge to the internal node DN7a, and is activated when the clock signals / CLK and CLK are at the L level and the H level, respectively, to the signal of the internal node DN7a. And includes a clocked inverter CIVa for driving the internal node DN6.

As with the first embodiment, the latch circuit 22 is activated when the CMOS inverter 7 which inverts the signal of the internal node DN6 and when the clock signals CLK and / CLK are at the L level and the H level, respectively. Clocked inverter 8 for inverting the output signal and driving to internal node DN6 is included.

The shift latch circuit 24 is activated when the clock signals CLK and / CLK are at the L level and the H level, respectively. The clock latch inverter 40 inverts the signal of the internal node DN6 and transfers the internal node DN11 to the internal node DN11 when activated. An inverter 41 for inverting the signal of the phase and a clocked inverter 42 that is activated when the clock signals / CLK and CLK are at the L level and the H level, respectively, and, when activated, inverts the signal of the inverter 41 and transmits the signal to the internal node DN11. . By these inverters 41 and clocked inverters 42, an inverter latch is formed upon activation of the clocked inverter 42.

The shift latch circuit 26 is activated when the clock signals / CLK and CLK are at the L level and the H level, respectively. The clock latch inverter 43 inverts the latch signal of the shift latch circuit 24 and transmits it to the internal node DN13 when activated. An inverter 44 that inverts the signal of the node DN13, and a clocked inverter 45 that is activated when the clock signals CLK and / CLK are at the L level and the H level, respectively, and, upon activation, inverts the signal of the inverter 44 and transmits it to the internal node DN13; And an inverter 46 which inverts the output signal of the inverter 44 to generate the output signal / OTD, and an inverter 47 which inverts the signal on the internal node DN13 to generate the output signal OTD.

The level converting circuit 30 has the same configuration as the level converting circuit 20, and charges the internal node DN7b in response to the rise of the clock signal / CLK and the N-channel MOS transistor 5b which transfers the input signal IN in response to the clock signal CLK. The MOS capacitor 6b to be supplied is activated when the clock signals CLK and / CLK are at the L level and the H level, respectively, and a clocked inverter CIVb for driving the internal node DN17 according to the signal of the internal node DN7b when activated.

The shift latch circuit 32 is activated when the clock signals / CLK and CLK are at the L level and the H level, respectively, and when activated, the clocked inverter 50 which inverts the signal on the internal node DN17 and transmits it to the internal node DN18, and the internal node DN18. Inverter 51 for inverting the phase of the signal and clock signals CLK and / CLK are activated at the L level and H level, respectively. When activated, the clocked inverter 52 inverts the output signal of the inverter 51 and transmits it on the internal node DN18. And an inverter 53 which inverts the output signal of the inverter 51 to generate the output signal OTE, and an inverter 54 which inverts the signal on the internal node DN18 to generate the output signal / OTE.

Therefore, in the configuration of the serial / parallel conversion circuit of the level conversion function shown in FIG. 17, the level conversion circuits 20 and 30 alternately perform the sampling operation and the level conversion operation in accordance with the clock signals CLK and / CLK. 26 and 32 perform latch and output operations of the signals in parallel. Next, the operation of the serial / parallel conversion circuit of the level conversion function shown in FIG. 17 will be described with reference to the timing chart shown in FIG.

At time t30, the input signal CLK rises to the H level, and the clock signal / CLK falls to the L level. The relationship between the change timings of the clock signals CLK and / CLK is the same as that described in the first to eighth embodiments. That is, the clock signal CLK changes after the clock signal / CLK is changed.

In the level converting circuit 20, sampling of the input signal D1 is completed, and the level converting operation by the clocked inverter CIVa is performed. In the latch circuit 22, the clocked inverter 8 is in an inactive state and no latch operation is performed. At this time, in the shift latch circuit 24, the clocked inverter 40 is in an inactive state and is in a latched state, and the output signal of the level conversion circuit 20 is not latched. On the other hand, the shift latch circuit 26 activates the clocked inverter 43 of the first stage and latches the output signal of the shift latch circuit 24. However, in this case, the signal is different from the input signal D1 and is an invalid signal.

On the other hand, in the level conversion circuit 30, the input signal IN is latched in accordance with the rise of this clock signal CLK. However, in this state, the clocked inverter CIVb is in an inactive state, and the signal of the internal node DN17 is an invalid signal. In the shift latch circuit 32, the clocked inverter 50 of the first stage is activated, and generates the output signal OTE according to the signal on this internal node DN17. However, also in this case, the signal on the internal node DN17 is a signal irrelevant to the input signal D1 and is an invalid signal.

When the level conversion operation in the level conversion circuit 20 and the sampling operation in the level conversion circuit 30 are performed in parallel, the input signal IN is changed to the second signal D2. At this time, the clock signal CLK is at the H level, and the setup of the input signal D2 is performed.

When the clock signal CLK falls to the L level at time t31 and the clock signal / CLK rises to the H level, the clocked inverter CIVa enters the output high impedance state in the level conversion circuit 20. In addition, the latched circuit 22 activates the clocked inverter 8 to enter the latched state. At this time, in the shift latch circuit 24, the clock inverter 40 of the first stage is activated, and the first signal D1 on the internal node DN6 is inverted and transmitted to the internal node DN11. On the other hand, in the shift latch circuit 26, the clocked inverter 43 of the first stage is in an inactive state, becomes a latched state, and the signal is not latched. Briefly, in the shift latch circuit 24, the signal is changed.

On the other hand, in the level conversion circuit 30, the second data signal D2 is latched in response to the fall of the clock signal CLK. At this time, the clocked inverter CIVb is in an inactive state, and the state of the internal node DN17 is not changed. In the shift latch circuit 32, the clocked inverter 50 becomes inactive, the shift latch circuit 32 becomes a latched state, its input and output are separated, and the output signals OTE and / OTE do not change.

After the third input signal D3 is set up, at time t32, the clock signal CLK rises to the H level, and the clock signal / CLK falls to the L level. In the level conversion circuit 20, sampling of the third input signal D3 is completed, and in response to the rise of the clock signal CLK, the charge pump operation for the internal node DN7a is performed. At this time, the clocked inverter CIVa is also activated, and the signal after level conversion corresponding to the third input signal D3 is output from the level converter circuit 20 (when the input signal D3 is at the H level). The shift latch circuit 24 responds to the rise of the clock signal CLK, and the clocked inverter 40 in the first stage is inactive, and the first data signal D1 latched in every cycle is held at its output.

On the other hand, in the shift latch circuit 32, in response to the rise of the clock signal CLK and the fall of the clock signal / CLK at this time t32, the clocked inverter 50 is activated, and the through state is electrically coupled with its input and output. The signal after the level conversion operation corresponding to the input signal D2 on the internal node DN11 is output as the output signal OTE. Also in the shift latch circuit 26, the clocked inverter 43 at the first input stage is activated, and the signal OTD after the level conversion operation corresponding to the input signal D1 at the first stage is generated in accordance with the latch signal of the shift latch circuit 24 at the front end.

At this time, in the following description, for the sake of simplicity, the "signal after level conversion" indicates "signal output from clock inverter CIVa or CIVb".

At time t33, clock signal CLK falls and clock signal / CLK becomes H level. Therefore, in the level conversion circuit 20, the clocked inverter CIVa is brought into an output high impedance state, and the sampling operation for the input signal IN is started. On the other hand, in the level conversion circuit 30, the charge pump operation is performed in response to the rise of the clock signal / CLK. When the input signal D4 is at the H level, the internal node DN7b is boosted to the boost level. In addition, the clocked inverter CIVb is activated, and the signal after the level conversion corresponding to the fourth data signal D4 is output to the internal node DN17. On the other hand, the shift latch circuit 24 enters the through state, and transmits the signal after the level conversion corresponding to the third input signal D3. Since the shift latch circuit 26 is in a latched state, the output signals OTD and / OTD are not changed.

When the clock signal / CLK falls to the L level and the clock signal CLK rises to the H level at time t34, the sampling operation in the level conversion circuit 30 starts, while the level conversion operation is performed in the level conversion circuit 20. Is executed. At this time, the shift latch circuit 24 is in a latched state, while the shift latch circuit 26 is activated, and the clocked inverter 13 at the first stage of the input is activated to become a through state, and an output signal OTD corresponding to the third input signal D3 is generated. do. At this time, also in the shift latch circuit 32, the clocked inverter 50 is activated, and the signal after the level conversion corresponding to the fourth input signal D4 is output as the output signal OTE.

Therefore, the odd-numbered signal in the input sequence of the input signal IN is output from the level conversion circuit 20 in accordance with the fall of the clock signal / CLK at the period of 2 · Tcy, while the input signal IN is input from the level conversion circuit 30. The even-numbered signal of the input sequence of is output as the clock signal CLK falls.

The shift latch circuit 24 outputs the output signal of the level conversion circuit 20 with a half cycle Tcy delay of the clock signals CLK and / CLK, and the shift latch circuit 26 outputs the output signal of the shift latch circuit 24 to the clock signals CLK and /. Outputs with a half cycle Tcy delay of CLK. On the other hand, the shift latch circuit 32 outputs the output signal of the level conversion circuit 30 by delaying the clock signal CLK and the half clock cycle Tcy of / CLK.

Therefore, the odd-numbered signal of the input signal IN is output from the level conversion circuit 20 every cycle of the clock signal CLK, and from the level-conversion circuit 30, the even-numbered signal of the input signal IN is lowered as the clock signal CLK falls. The signal is output. As a result, after the first input signal D1 is provided as the input signal IN, after one clock cycle of the clock signals CLK and / CLK, the even-numbered signal and the odd-numbered signal of the input signal IN become the clock signal CLK. In synchronization with the rising of the signal, the signal is output in one clock cycle, i.e., twice the period Tcy of the input signal IN. Thereby, the level conversion of the input signal IN of period Tcy is performed, and the output signals OTD and OTE of period 2Tcy can be obtained.

Therefore, even if the input signal IN is a high speed signal, the level converting circuits 20 and 30 can be operated at a frequency 1/2 times the frequency of the input signal IN, and the sampling and level converting operations can be performed reliably, and the next stage circuit can be operated. Can be transferred to.

In the level conversion circuits 20 and 30 shown in FIG. 17, the configuration of the level conversion circuit shown in FIG. 3 is used. However, as the configuration of these level conversion circuits 20 and 30, other configurations shown in Figs. 1, 8 and 9 may be used.

[Change example]

Fig. 19 is a diagram showing the configuration of main parts of the serial / parallel conversion circuit of the level conversion function according to the ninth embodiment of the present invention. Fig. 19 shows the configuration of portions of the level conversion circuits 20 and 30 of the serial / parallel conversion circuit having the level conversion function. In Fig. 19, the level converting circuit 20 selectively performs a charge pump operation in response to the rising of the clock signal CLK and the N-channel MOS transistor 5a which transfers the input signal IN to the internal node DN9a when the clock signal / CLK is at the H level. The MOS capacitor 6a for supplying charge to the internal node DN9a, the N-channel MOS transistor 9a for transferring the clock signal CLK to the internal node DN7a according to the signal potential on the internal node DN9a, and the internal node DN7a to the L signal according to the clock signal CLK. N-channel MOS transistor 10a to be low-charged, and clocked inverter CIVa which is activated when clock signals CLK and / CLK are at H level and L level, respectively, and inverts the signal on internal node DN7a.

The level converting circuit 30 has the same configuration as that of the level converting circuit 20, and responds to the rise of the N-channel MOS transistor 5b that transfers the input signal IN to the internal node DN9b when the clock signal CLK is at the H level, and the rise of the clock signal / CLK. A MOS capacitor 6 which selectively charges the battery to supply charge to the internal node DN9b, and an N-channel MOS transistor 9b that selectively transfers the clock signal / CLK to the internal node DN7b according to the signal potential on the internal node DN9b, and a clock. N-channel MOS transistor 10b which conducts when signal CLK is at H level, precharges internal node DN7b to low level, and is activated when clock signals CLK and / CLK are at L level and H level, respectively. Clocked inverter CIVb that inverts the phase of the signal.

The configuration of the level conversion circuits 20 and 30 shown in these FIG. 19 is the same as that of the level conversion circuit shown in FIG. A latch circuit 22 and shift latch circuits 24 and 26 shown in FIG. 16 are provided at the rear end of the level converting circuit 20, and a shift latch circuit 32 shown in FIG. 16 is provided at the next stage after the level converting circuit 30. FIG.

Also in the configuration of the serial / parallel conversion circuit of the level conversion function shown in Fig. 19, the level conversion circuits 20 and 30 alternately sample the input signal IN in accordance with the clock signals CLK and / CLK and perform level conversion. That is, when the clock signal CLK is at the H level, the level converting circuit 30 latches the input signal IN, while the level converting circuit 20 selectively performs the level converting operation in accordance with the signal latched in the cycle at this time. The inverter CIVa outputs the signal after level conversion.

On the other hand, when the clock signal / CLK is at the H level and the clock signal CLK is at the L level, the level conversion circuit 20 latches the input signal IN, and at this time, the clocked inverter CIVa is in an inactive state. On the other hand, in the level conversion circuit 30, a selective charge pump operation by the MOS capacitor 6 is performed in accordance with the sampled signal, and the clock signal / CLK is selectively transmitted to the clocked inverter CIVb through the MOS transistor 9b. Clocked inverter CIVb is activated, and the signal after level conversion is generated by this clocked inverter CIVb.

Therefore, even in the configuration shown in Fig. 19, the level conversion circuits 20 and 30 alternately sample the input signals IN at the cycles of the clock signals CLK and / CLK, thereby performing level conversion. Therefore, twice the cycle of the input signal IN is performed. The internal signal can be generated by the cycle of.

At this time, also in the configuration of the level conversion circuits 20 and 30 shown in FIG. 19, the configuration of another embodiment may be used.

As described above, according to the ninth embodiment of the present invention, the level conversion function circuits are provided in parallel with respect to the input nodes, and are operated alternately according to these complementary clock signals, and the sampling operation and the level conversion operation are performed. In this way, the period of the input signal IN is doubled, and the level shifting operation can be performed.

At this time, when the output signals OTE and OTD of the serial / parallel conversion circuit of the level conversion function are display signals supplied to the pixels, the horizontal driver registers the horizontal data driver to drive the pixel data lines at the same period as the input signal IN. By activating, the pixel signal can be written to the pixel element according to the dot sequential method.

(Example 10)

20 is a diagram schematically showing the configuration of a serial / parallel conversion circuit having a level conversion function according to a tenth embodiment of the present invention. In Fig. 20, the serial / parallel conversion circuit of the level conversion function is provided in parallel with respect to the input nodes, and latches the provided input signal IN according to each of the shift clock signals / SH1- / SHn from the shift register circuit 60. Level conversion circuits LCK1-LCKn for level conversion and level conversion circuits LCK1-LCKn are provided in correspondence with each other and are activated when the corresponding shift clock signal / SH1- / SHn is at L level, and corresponding level conversion circuit LCK1-LCKn. The latch circuit LLK1-LLKn and the level conversion circuit LCK1-LCKn, which latch the output signal, respectively, correspond to each other and are in a through state when the latch instruction signal LAT is at the H level, and are latched when the latch instruction signal LAT is at the L level. Shift latch circuits SLK1-SLKn.

The output signals of the shift latch circuits SLK1-SLKn are provided in parallel to the digital / analog conversion circuit (DAC) 65. The output signals PX1-PXm of this digital / analog conversion circuit 65 are supplied to select pixels provided in the pixel matrix (not shown). That is, the serial / parallel conversion circuit of the level conversion function shown in FIG. 20 converts display data IN input in series into a parallel signal in a display device such as a liquid crystal element or an organic EL. An analog signal corresponding to the input digital data is generated by the digital / analog conversion circuit 65, and the generated analog signal is recorded as a pixel display signal on the display element. The digital / analog conversion circuit 65 generates one analog pixel display signal PXi (i = 1-m) from a plurality of bits of digital signals in accordance with the gradation of the pixel display.

The shift register circuit 60 performs a shift operation in accordance with the clock signal CLK in accordance with the supply start instruction signal Vst of the input signal IN, and shifts the shift clock signal / SH1- / SHn by about half a period out of phase with respect to the input signal IN. Activate it. In the level converting circuits LCK1-LCKn, an operation of sequentially leveling the input signal IN by latching is performed. Subsequently, in accordance with the latch instruction signal LAT, the output latches of the level converter circuits LCK1-LCKn corresponding to the shift latch circuits SLK1-SLKn are latched in parallel, and the signals after parallel low level conversion are output to the digital / analog converter circuit 65. do. Next, digital / analog conversion is performed in accordance with the signals after these level conversions, and display signals PX1-PXm for the pixel elements are generated.

FIG. 21 is a diagram showing an example of the configuration of a portion for generating a signal after level conversion of one stage of the serial / parallel conversion circuit of the level conversion function shown in FIG. In Fig. 21, the shift clock signal / SHi from the shift register circuit 60 is provided as a sampling / level conversion timing signal.

In Fig. 21, the level converting circuit LCKi includes an N-channel MOS transistor 70 for transmitting the input signal IN to the internal node DNi when the shift clock signal / SHi is at the H level, an inverter 71 for inverting the shift clock signal / SHi, and an inverter. MOS capacitor 72 which selectively charges operation in response to rising output signal SHi of 71 to supply charge to internal node DNi, and selectively activates according to shift clock signals / SHi and SHi, and when activated, internal node DNi And a clocked inverter CIVI for generating a signal after the level change in the internal node DNj according to the signal on the phase.

The power supply voltage VDD is supplied to the high side power supply node of the clocked inverter CIV1, and the shift clock signal / SHi is supplied to the low power supply node.

The latch circuit LLKi is selectively activated according to the inverter 73 inverting the signal of the internal node DNj and the shift clock signals SHi and / SHi, and when activated, the clocked inverter driving the internal node DNj according to the output signal of the inverter 73. Contains 74. The clocked inverter 74 is activated when the shift clock signals SHi and / SHi are at the L level and the H level, respectively, complementarily with the clocked inverter CIV1, and inverts the output signal of the inverter 73 when activated.

The shift latch circuit SLKi includes a clocked inverter 75 which inverts a signal on the internal node DNj according to the latch instruction signal LAT and the latch instruction signal / LAT of the beam, an inverter 76 that inverts the output signal of the clocked inverter 75, and a latch instruction. And a clocked inverter 77 which is selectively activated according to the signals LAT and / LAT and, upon activation, inverts the output signal of the inverter 76 to transfer the inverted signal to the internal node DNk.

The clocked inverter 75 is activated when the latch instruction signals LAT and / LAT are at the H level and the L level, respectively. The clocked inverter 77 has the latch level LAT and / LAT at the L level and H level, respectively. Is activated when These clocked inverters 74, 75 and 77 enter an output high impedance state when deactivated.

In the level converting circuit LCKi, the shift clock signal / CHi is provided to the low-side power supply node of the clocked inverter CIV1, which eliminates the need for wiring to transfer the ground voltage VSS, and improves the freedom in designing the wiring layout. .

The configuration of the level conversion circuit LCKi shown in FIG. 21 is substantially the same as the configuration of the level conversion circuit shown in FIG. Therefore, when the shift clock signal / SHi is at the H level, the input signal IN is latched, and when the shift clock signal / SHi is at the L level, the latched input signal IN is level-converted to the internal node DNj from the clocked inverter CIV1. Outputs the signal after level conversion. The signal on this internal node DNj is latched by the latch circuit LLKi when the shift clock signals SHi and / SHi are L level and H level, respectively.

The shift latch circuit SLKi is in a latched state when the latch instruction signal LAT is at the L level, and is in a through state when the latch instruction signal LAT is at the H level. The shift latch circuit SLKi inverts the signal latched by the corresponding latch circuit LLKi to invert the digital / Output to analog conversion circuit 65.

FIG. 22 is a timing diagram illustrating a serial / parallel conversion circuit of the level conversion function shown in FIG. 20. As shown in FIG. 22, the delay clock signal / SH1- / SHn is sequentially set to the L level of one cycle period of the input signal IN by delaying a half clock cycle with respect to the transmission cycle of the input signal IN. Therefore, the input signal IN has a setup time for each of the level conversion circuits LCK1-LCKn, and is latched in response to the falling of the corresponding sampling clock signal / SH1- / SHn. In response to the drop of the corresponding sampling clock signal / SH1- / SHn, in the level converting circuit LCK1-LCKn, the selective boosting operation of the latched signal is performed, and the level converting operation is performed.

Next, when the corresponding sampling clock signal / SH1- / SHn rises to the H level, the clocked inverter CIV1 is inactivated in the level conversion circuit LCK1-LCKn, and the output high impedance state is reached. Therefore, even if the input signal IN is changed, the signal after the level conversion of the input signal IN is latched by the corresponding latch circuit LLK1-LLKn without any influence on the signal after the level conversion.

When the last shift clock signal / SHn rises from the L level to the H level, the latch instruction signal LAT goes to the H level, and the shift latch circuits SLK1-SLKn go through, and the signal latched to the latch circuits LLK1-LLKn. Is generated and transmitted to the digital / analog conversion circuit 65.

At this time, the latch instruction signal LAT is driven to the H level at a proper timing after the shift clock signal / SHn is raised to the H level after the predetermined number of input signals IN are latched. Therefore, the latch instruction signal LAT may be generated from the register stage next to the shift register stage which generates the shift clock signal / SHn from the shift register circuit 60, and is generated based on a signal that defines other suitable digital / analog conversion timing. You may be.

The shift clock signal / SH1- / SHn may be a signal having a phase difference between the periods of the input signal IN, and may be a signal different from the output signal of the shift register circuit 60.

In the serial / parallel conversion circuit of the level conversion function, the output signal is supplied to the digital / analog conversion circuit in order to generate an analog signal to the pixel elements of the pixel matrix. However, the signal output by this serial / parallel conversion circuit may be used for other purposes, and is generally a portion of a circuit which performs serial / parallel conversion, and is provided at a portion where the voltage amplitude of the serial input signal and the parallel conversion signal is different. The serial / parallel conversion circuit of this level conversion function can be applied.

(Change example)

FIG. 23 is a diagram showing a modification of the level conversion circuit LCK1-LCKn shown in FIG. 20. In FIG. 23, since the level conversion circuits LCK1-LCKn have the same configuration, the configuration of the level conversion circuit LCKi (i = 1-n) is representatively shown. In Fig. 23, the level converting circuit LCKi includes an N-channel MOS transistor 80 for transmitting the input signal IN to the internal node DNs according to the shift clock signal / SHi, an inverter 81 for inverting the shift clock signal SHi, and a signal of the internal node DNs. N-channel MOS transistor 82 which selectively transfers output signal SHi of inverter 81 to internal node DNt in accordance with the potential, is connected at H level of shift clock signal / SHi, and internal node DNt is connected to ground voltage level (shift clock signal). An N-channel MOS transistor 83 precharged to the low level of SHi, and a clocked inverter CIV2 that is selectively activated according to the shift clock signals SHi and / SHi and inverts the signal of the internal node DNt when activated.

The clocked inverter CIV2 is activated when the shift clock signal / SHi is at the L level and the shift clock signal SHi is at the H level, and operates as an inverter.

The configuration of the level conversion circuit LCKi shown in FIG. 23 is the same as that of the level conversion circuit shown in FIG. That is, when the shift clock signal / SHi is at the H level, the input signal IN is latched. When the shift clock signal / SHi goes to the L level, the MOS transistor 80 is turned off, and the output signal SHi of the inverter 81 rises to the H level, and by the self-bootstrap action of the MOS transistor 82, The voltage level rises, and the H level of this signal SHi is transmitted to the internal node DNt (when sampling the H level signal). At this time, the clocked inverter CIV2 is also activated, and the signal transmitted to the internal node DNt is inverted, transferred to the latch circuit LLKi at the next stage shown in FIG. 20 and latched.

When the shift clock signal / SHi rises from the L level to the H level, the output signal SHi of the inverter 81 goes to the L level, the clocked inverter CIV2 becomes inactive, and the input and output of the clocked inverter CIV2 are separated. In this state, the MOS transistor 83 is in the on state, and the internal node DNt is precharged to the L level. In addition, even when the input signal IN is provided sequentially and the voltage level of the internal node DNs is changed, the output signal SHi of the inverter 81 is kept at the L level, and the internal node DNt is kept at the L level.

Therefore, even if the level conversion circuit LCKi shown in FIG. 23 is used, serial / parallel conversion and level conversion can be efficiently performed.

As described above, according to the tenth embodiment of the present invention, level conversion circuits are provided in parallel, and the sampling and level conversion operations of these level conversion circuits are sequentially shifted to efficiently convert serial input signals into parallel signals. In addition, the voltage amplitude of the serial input signal can be converted.

(Example 11)

Fig. 24 is a diagram schematically showing the configuration of the serial / parallel conversion circuit of the level conversion function according to the eleventh embodiment of the present invention. The serial / parallel conversion circuit of the level conversion function shown in FIG. 24 is different from the configuration of the serial / parallel conversion circuit of the level conversion function shown in FIG. 20 in the following points. That is, in the level conversion circuit LCK1-LCKn for level conversion of the input signal IN, the input signal is sampled in accordance with the shift clock signals SH0-SH (n-1) from the level conversion circuit in the previous stage, and the corresponding shift clock signal Perform level conversion according to / SH1- / SHn. The other structure of the serial / parallel conversion circuit of the level conversion function shown in FIG. 24 is the same as that shown in FIG. 20, and the same reference numerals are attached to corresponding parts, and the detailed description thereof is omitted.

In the level converting circuit LCK1-LCKn shown in FIG. 24, the input signal IN is latched when the level converting operation is performed in the previous level converting circuit. After latching the input signal IN, the previous shift clock signal is kept in an inactive state at the H level. Therefore, in the level conversion circuits LCK1-LCKn, only when the input signal IN is latched, the MOS transistor (MOS transistor 70 in FIG. 21 or MOS transistor 80 in FIG. 21) of the input terminal is turned on. Therefore, the input signal IN is only required to drive the internal node of the selected level converting circuit and the capacitor connected to it (when the MOS capacitor is set), and the load can be reduced, thus reducing power consumption. can do.

FIG. 25 is a diagram showing an example of the configuration of the level conversion circuit LCK1-LCKn shown in FIG. 24. In FIG. 25, the structure of the level conversion circuit LCKi is shown typically. This level conversion circuit LCKi shown in FIG. 25 is different from the level conversion circuit LCKi shown in FIG. 21 in the following points. That is, the output signal of the inverter 90 which receives the corresponding shift clock signal / SHi is provided to the electrode node (source / drain node) of the MOS capacitor 72, and the gate of the active control N-channel MOS transistor 4 of the clocked inverter CIV1. Is provided. The output signal of the inverter 90 is also provided as a sampling timing signal of the next level conversion circuit LCK (i + 1). The gate of the N-channel MOS transistor 70 at the input terminal is provided with a shift timing signal SH (i-1) for the level conversion circuit LCK (i-1) at the front end. The other configuration of the level conversion circuit LCKi shown in FIG. 25 is the same as that of the level conversion circuit shown in FIG. 21, and the same reference numerals are attached to corresponding parts, and detailed description thereof is omitted.

Incidentally, the configurations of the latch circuit LLKi and the shift latch circuit SLKi are the same as those shown in Fig. 24, and the same reference numerals are attached to corresponding parts, and the detailed description thereof is omitted.

At this time, the operation timing of the level conversion circuit LCKi shown in FIG. 25 is the same as the operation timing shown in FIG. That is, the shift register circuit 60 performs the same operation as the shift register circuit 60 shown in FIG. 20 except that the sampling timing signal SH0 for the first stage level conversion circuit LCK1 is generated.

FIG. 26 is a timing diagram illustrating the operation of the level conversion circuit LCKi shown in FIG. 25. Hereinafter, with reference to FIG. 26, the operation | movement of the level conversion circuit LCKi shown in FIG. 25 is demonstrated.

When the shift clock signal / SH (i-1) from the shift register circuit 60 falls from the H level to the L level, the inverted shift clock signal (sampling timing signal) SH (i-1) goes from the L level to the H level. Therefore, the MOS transistor 70 shown in FIG. 25 is turned on, and the input signal IN is transmitted to the internal node DNi. At this time, in the level conversion circuit LCK (i-1), the level conversion operation is performed in accordance with the shift clock signal / SH (i-1). In the period in which the inverted shift clock signal SH (i-1) is at the H level, the input signal IN is changed to the i-th signal. Next, when the shift clock signal / SH (i-1) rises to the H level, the inverted shift clock signal SH (i-1) becomes the L level, and the MOS transistor 70 shown in FIG. 25 is turned off. At this time, the shift clock signal / SHi becomes L level, the clocked inverter CIV1 is activated, and a selective level shift operation is performed on the sampled signal. In the level shift operation in the level shift circuit LCKi, the inverted shift clock signal SHi output from the inverter 90 is H level, and in the next level shift circuit LCK (i + 1), the shift shift clock signal SHi is performed. Is used as the sampling timing signal, the MOS transistor 70 at the input terminal conducts, and the input signal IN is latched. When the shift clock signal / SHi is at the H level, the clocked inverter CIV1 is deactivated in the level conversion circuit LCKi, and the signal after the level conversion is latched by the latch circuit LLKi at a later stage.

After the completion of the sampling operation, the level conversion circuit LCK (i + 1) of the next stage performs the level conversion operation and latch in accordance with the shift clock signal / SH (i + 1).

Therefore, in the level conversion circuit LCK1-LCKn, when the input signal IN is latched, the MOS transistor (transistor 70) at the input terminal is turned on. After completion of the sampling operation, the MOS transistor 70 at the input terminal is turned off. Keep it. Therefore, for the input signal IN, only the internal node DNi of the selected level converting circuit is always coupled, and the load can be reduced.

[Change example]

27 is a diagram showing a modification of the level conversion circuit according to the eleventh embodiment of the present invention. The level conversion circuit LCKi shown in FIG. 27 differs in configuration from the level conversion circuit shown in FIG. 23 in the following points. That is, the inverted shift clock signal SH (i-1) to the level conversion circuit LCK (i-1) of the previous stage is provided as a sampling timing signal to the gate of the MOS transistor 80 at the input terminal. The inverted shift clock signal SHi from the inverter 81 is provided as a sampling timing signal to the gate of the MOS transistor at the input of the next level converting circuit LCK (i + 1). The other structure of the level conversion circuit shown in FIG. 27 is the same as that of the level conversion circuit LCKi shown in FIG. 23, and the same reference numerals are attached to corresponding parts, and the detailed description thereof is omitted.

Also in the configuration of the level converting circuit LCKi shown in FIG. 27, when the level converting circuit LCKi is selected, the inverted shift clock signal SH (i-1) becomes H level, the MOS transistor 80 is turned on, and is connected to the internal node DNs. Input signal IN is transmitted. When the inverted shift clock signal SH (i-1) falls to L level, the MOS transistor 80 is in a non-conductive state. Accordingly, the shift clock signal / SHi becomes L level, the inverted shift clock signal SHi from the inverter 81 becomes H level, the internal node DNt is driven in accordance with the signal transmitted to the input node DNs, and the clocked inverter CIV2 When activated, a signal after level conversion is generated and latched by a latch circuit LLKi (not shown).

When the shift clock signal / SHi rises to the H level, the inverted shift clock signal SHi goes to the L level, and the internal node DNt is again maintained at the ground voltage level to prevent the internal node DNt from floating.

Even when the level conversion circuit LCKi shown in FIG. 27 is used, the input signal IN is similarly coupled to the internal node only for the selection level conversion circuit, thereby reducing the load of the input signal IN.

(Change example 2)

Fig. 28 is a diagram showing another modification of the level conversion circuit according to the eleventh embodiment of the present invention. In the level converting circuit shown in Fig. 28, the input signal IN is provided once, and the level of the input signal IN provided once is converted. That is, the level converting circuit shown in Fig. 28 performs level conversion of the MOS transistor 100 which transmits the input signal IN in accordance with the clock signal CLK1, and the signal transferred through the MOS transistor 100 in accordance with the clock signals CLK2 and / CLK2. And a level converting section 102 to latch. This level converting section 102 has a circuit configuration of excluding the MOS transistors at the input ends of the level converting circuits shown in the first to ninth embodiments. When the clock signal CLK2 is at the H level and the clock signal / CLK2 is at the L level, this level converter 102 is activated to convert the H level of the sampling signal into a signal of an H level having a voltage level higher than that.

FIG. 29 is a signal waveform diagram showing the operation of the level conversion circuit shown in FIG. 29, the operation of the level converting circuit shown in FIG. 28 will be briefly described.

When the clock signal CLK1 becomes H level, the MOS transistor 100 is turned on, and the input signal IN is transmitted to the level converter 102. At this time, the level converter 102 maintains the inactive state at the clock signals CLK2 and / CLK2 at L level and H level, respectively.

When the clock signal CLK1 falls to the L level, the MOS transistor 100 becomes active and the sampling period of the input signal IN is completed.

When the sampling of the input signal IN is completed, the clock signal CLK2 is at the H level, and the clock signal / CLK2 is at the L level. Therefore, the level converting unit 102 is activated to perform level conversion of the sampled input signal IN to generate an internal signal. When the clock signals CLK2 and / CLK2 are at the L level and the H level, respectively, the level converting unit 102 is made inactive again and the output high impedance state is reached. At this time, the clock signal CLK1 is at the L level, and the level converting operation of the input signal IN provided only once is completed.

Therefore, the clock signals CLK1, CLK2 and / CLK2 can reliably latch the input signal IN and perform the level shift operation by setting the voltage level in accordance with the timing at which the input signal IN is provided. In particular, by forming the clock signals CLK1 and the clock signals CLK2 and / CLK2 in different paths, it is possible to reliably perform the level conversion operation in the level conversion section 102 after sampling.

As described above, according to the eleventh embodiment of the present invention, when performing the serial / parallel conversion operation and performing the level conversion operation, the input signal is transmitted only to the selected level conversion circuit, and the latched input signal is applied. The level conversion operation is performed in accordance with a clock signal (shift clock signal). Therefore, only the selection level converting circuit, its internal node is coupled to the input signal IN, and the load of the input signal IN is reduced.

In the case of performing the level conversion of the single input signal IN, the timing margin can be increased by forming a separate clock signal in another path.

At this time, the configuration of another embodiment may be used as the configuration of the level conversion circuit LCKi shown in FIGS. 25 and 27.

Also, as shown in FIG. 9, as shown in FIG. 9, a MOS transistor coupled to an internal node is coupled to a high and low side power supply, and a MOS transistor receiving a clock signal to a gate is connected to an output node of the clocked inverter. Combining configurations may be used.

 The present invention is generally applicable to a level converting circuit for converting the voltage amplitude of an input signal, and is particularly applicable to a display device using a liquid crystal element or an organic EL element which requires such level conversion.

In a configuration in which a plurality of power sources are used in the system LSI or the like, the level converting circuit according to the present invention can be applied to an interface portion between power supplies of different voltage levels.

While the invention has been described in detail, it is to be understood that this is for illustration only and is not intended to limit the invention, the spirit and scope of the invention being limited only by the claims.

Claims (3)

A first insulated gate field effect transistor for transmitting an input signal provided to the input node to the first internal node according to the first clock signal from the first clock input node; An insulated gate field effect transistor having a gate connected to the first internal node and a source and a drain connected to the second clock input node, and between the second clock input node and the first internal node receiving the second clock signal. A MOS capacitor connected to the capacitor and selectively forming a capacitance according to a potential difference between the first internal node and the second clock input node; When the first insulated gate field effect transistor is not conducting, it is selectively activated according to the first clock signal and the second clock signal, and when activated, the potential of the first internal node is inverted to provide a second internal node. And a clocked inverter for generating a signal having an amplitude greater than that of the input signal. A first insulated gate field effect transistor for transmitting an input signal to the first internal node according to the first clock signal from the first clock input node; A second insulated gate field effect transistor for transmitting a second clock signal provided to a second clock input node to a second internal node according to the potential of the first internal node; A low driving circuit for driving the second internal node to a voltage level of a low side power node according to a clock signal in phase with the first clock signal of the first clock input node; And a clocked inverter activated according to clock signals in phase with the clock signals of the first and second clock input nodes and driving a third internal node according to the signal potential of the second internal node. Conversion circuit. A clocked inverter that is activated in response to the first clock signal, and inverts a signal of the first node and transmits the signal to the second node upon activation; A first insulated gate field effect transistor configured to receive the first clock signal at a gate and to be in a conductive state when the clocked inverter is disabled, and to transmit an input signal to the first node; A gate is connected to the first node, and a drain and a source are composed of an insulated gate field effect transistor connected commonly at a third node. The first node receives a clock signal inverting the first node and the first clock signal. And a MOS type capacitance element connected between third nodes, the charge pump operation in response to a clock signal of the third node to supply charge to the first node.

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