KR100253171B1 - Error correcting circuit and method - Google Patents

Abstract

PURPOSE: A method and circuit for correcting a data error is provided to devise an error number deciding condition used in an error correction process from the PGZ complex algorithm. CONSTITUTION: The first deinterleaving unit(1A) restores data interleaved and recorded in a recording medium into the original information data. The first error calculating unit(20) is controlled by a GF calculation unit(3) and a control unit(4), and receives data outputted from the first deinterleaving unit(1A), and calculates syndromes(S0, S1, S2, S3), (S0, S2+S1, S1), an error number, a position of error and single and double error value. An error flag adding and error value storing unit(10A) adds an error flag to output data of the first error calculating unit(20). An exclusive-OR gate unit(11A) exclusively ORs data inputted from the first deinterleaving unit(1A) through a data absorbing unit(2A) and data outputted from the error flag adding and error value storing unit(10A), and completes the first error correction. The second deinterleaving unit(1B) performs a deinterleaving of first error correction data again. The second error calculating unit(30) receives output data outputted of the second deinterleaving unit(1B) and calculates syndromes(S0, S1, S2, S3), (S0, S2+S1, S1), an error number, a position of error and single and double error value, and sets an average range of error flag number in non-error, single error and double error, and compares the range with a calculated value calculated in a total number calculation unit(12), and decides a coefficient of reliability. An exclusive-OR gate unit(11B) exclusively ORs data inputted from the second deinterleaving unit(1B) and the error flag adding unit(10B) through a data absorbing unit(2B) and the error flag adding unit(10B). An average value interpolation unit(14) performs an average value interpolation of an output data of the exclusive-OR gate unit(11B).

Description

Data error correction method and circuit

1 is a signal flow diagram for general error correction.

2 is a data error correction block diagram of the present invention.

3 is a signal flow diagram for error correction of the present invention.

* Explanation of symbols for main parts of the drawings

1A: 1st deinterleave part 1B: 2nd deinterleave part

2A, 2B: data buffer part 3: GF calculation part

4: control unit 5A: first syndrome calculation unit

5B: the second syndrome calculation unit _{6A, 6B: S 0 · S} 2 + S 1 · S 1 operating section

7A, 7B: Error count determining unit 8A, 8B: Error position calculating unit

9A, 9B: Single, double error calculation unit

10A, 10B: Error flag and error value storage

11A, 11B: Exclusive Oagate Part

12: error flag total calculation unit 13: reliability determination unit

20: the first error calculation unit 30: the second error calculation unit

BACKGROUND OF THE INVENTION 1. Field of the Invention [0001] The present invention relates to digital signal processing techniques, and more particularly, to an error correction method and circuit for data in which the equation is suitable for further simplifying the error correction algorithm using a simple decoding algorithm when the error correction capability is two symbols. .

In general, a decoding technique for correcting an error occurring on a channel is as follows. First, a syndrome is calculated for each frame of the received digital data series. Second, the number of errors is determined by the calculated syndrome. Third, the error position and error value are calculated for each error case in the state where the error is determined. Fourth, the error correction is performed by using the Exclusive-Or calculation of the existing data (symbol unit) and the calculated error value at the corresponding location using the data on the error location and the error value.

1 is a signal flow diagram for a general error correction basically following the error correction procedure.

This assumes that the received data is encoded (CIRC) by two interleaves at the transmitter. Since there are two interleaving processes, two deinterleave processes are required, and thus two error correction procedures are required.

Therefore, the basic process is as follows. First, a syndrome is calculated from data received through a first deinterleave process. Second, by using the calculated syndrome, the error-free detection condition, single error detection condition, double error detection condition, and triple error detection condition are created, and the errors existing in each received frame are detected and error correction is performed. Add an error flag to the number of errors in. Third, the first error corrected data is calculated through the second deinterleave process, and the total number of error flags existing in one frame is calculated. The fourth is similar to the first error correction except that the error is corrected after the reliability is determined by the total number of error flags.

However, in the conventional error correction system, since the error is corrected by classifying each error number into four in the first error correction process, this procedure becomes complicated, and each error number is classified into four in the second error correction process. In addition, since each reliability is determined, the complexity is increased. As a result, the number of logic gates in the digital signal processing processor increases, resulting in a defect that takes a long time for error correction.

The present invention has been made from the PGZ complex algorithm to solve such a conventional defect, the error number determination condition which is an important part in the error correction process, will be described in detail by the accompanying drawings.

3 is an error correction block diagram of the data of the present invention, as shown therein, the first deinterleave unit 1A and the GF operation unit 3 which interleave and restore the data recorded on the recording medium to the original information data. And under the control of the control unit 4, the data output from the first deinterleave unit 1A is supplied, and the syndromes S0, S1, S2, S3, (S0 S2 + S1 S1), the number of errors, A first error calculation unit 20 for calculating a position of an error, single and double error values, and an error flag addition and error value storage unit 10A for adding an error flag to the output data of the first error calculation unit 20. And an exclusive ord operation on the data input from the first deinterleave unit 1A through the data buffer unit 2A and the data output from the error flag addition and the error value storage unit 10A. Exclusive oragate portion 11A for completing error correction of the above, and The second deinterleave unit 1B for deinterleaving the first error corrected data and the output data of the second deinterleave unit 1B are supplied, and the syndromes S0, S1, S2, S3), (S0 · S2 + S1 · S1), the number of errors, the location of errors, single and double error values are calculated, and the average range of error flags for no error, single error, and double error is set and the total number of error flags. The second deinterleave through the second error operation unit 30, the data buffer unit 2B, and the error flag adding unit 10B, respectively, which compare the value calculated by the calculation unit 12 to determine the reliability thereof. The exclusive oragate part 11B which performs exclusive ora operation on the data input from the part 1B, the error flag addition, and the error value storage part 10B, and the exclusive oragate part 11B. It is composed of an average value interpolation section 14 that performs average value interpolation on output data. When described in detail with reference to Figure 3 attached to the present invention configured as described above are as follows.

In the PGZ complex algorithm, the equation representing the relationship between the syndrome and the error position polynomial (δ (x) = X ² + δ ₁ X + δ ₂ = 0) is defined as follows.

Where

X _1, X _2: the error locator, Y _1, Y _2: La error position, and obtain and Mμ (S) by taking the determinant, │Mμ (S) │ = │A│ · │B│ · │A T │ If the number of errors actually occurred is smaller than μ = 2, then B│ = 0, so that │Mμ (S) │ = 0, and if the number of errors actually occurred μ = 2, │B│ ≠ 0, │A│ ≠ 0, | A ^T | ≠ 0, so | Mμ (S) | ≠ 0.

Therefore, when there is one error, Mμ (S) = S ₀ S ₂ + S ₁ S ₁ = 0, and when there are two errors, M μ (S) S = S ₀ S ₂ + S _{1 When 1} ≠ 0 and there is no error, generally S ₀ = S ₁ = S ₂ = S ₃ = 0, and thus, the error discrimination condition formula is derived as follows.

Without error: S ₀ = S ₁ = S ₂ = S ₃ = 0

When there is only one error: S ₀ S ₂ + S ₁ S ₁ = 0

When there are two errors: S ₀ S ₂ + S ₁ S ₁ ≠ 0

First, a syndrome is calculated by first deinterleaving the received digital data.

Second, if the condition S ₀ = S ₁ = S ₂ = S ₃ = 0 is satisfied by the syndrome value, the second deinterleave step is directly entered, and if S ₀ S ₂ + S ₁ S ₁ = 0, Single error processing, if S ₀ S ₂ + S ₁ S ₁ ? 0, double error processing is performed to correct the error, and then an error flag is inserted for each error position, and then the second deinterleave step is entered. .

Third, through the second deinterleave step, the first and second steps are the same, but reliability is determined only for each error-free and single error, and error correction is performed. This reliability determination may vary depending on the application (digital audio and video, digital communications, database…) and the environment, and to apply to CDs, the size of the error flag depends on the size of the error (dust, scratches, etc.) on the compact disc. Since the total number of is different, it is good to use the average calculated value for the most common errors.

Fourth, the data of which the reliability is determined and error corrected are again interpolated by the error flag to correct the error and terminate.

On the other hand, the data interleaved (delayed and rearranged) and recorded on the disk are supplied to the first interleave unit 1A and returned to the original information data, and the 8-bit symbols outputted through the first interleave unit 1A are It is supplied to and accumulated in the data buffer 2A, which is held during the determination of error and the error value.

The 8-bit symbol output from the first interleave unit 1A is controlled by the GF (hereinafter, referred to as a Gallo field) 2 ⁸ operation unit 3 and the control unit 4, and is then controlled by the first syndrome calculation unit 5A. Four symbols S ₀ , S ₁ , S ₂ , and S ₃ for determining whether an error exists in one frame are generated, and then S ₀ S ₂ + S ₁ S ₂ calculation unit 6A and error number determination unit 7A. ), The error position calculation unit 8A, the single, double error value operation unit 9A, if the operation is performed, the error flag addition and error value storage unit 10A checks the result of the above operation, and if the error exists, the corresponding error The flag "1" is added immediately before the most significant bit of the symbol, and the error value is temporarily stored in order to match the corresponding error symbol with the time input to the exclusive oragate part 11A, and the exclusive oragate part 11A adds an error flag and stores an error value to data output from the data buffer 2A. Adding the error flag outputted from (10A) to the first error correction is finished.

Here, the GF operation unit 3 provides an 8-bit operation unit in each unit, and the control unit 4 controls the data input / output and the operation order and timing of each unit, and S ₀ S ₂ + S ₁ S ₂ operation unit 6A. Calculates vertical S ₀ S ₂ + S ₁ S ₂ on which the single error and double error are judged on the field, and the error count determination unit 7A calculates four syndrome symbols S ₀ , S ₁ , S ₂ , and S ₃ . If all zero _{error-free, S 0 · S 2 + S} 1 · S 1 = 0 If the _{single-error, S 0 · S 2 + S} 1 · S 1 ≠ 0 is, determined by the double error, and the error position calculation unit (8A) is 1, The number of symbols in the frame calculates which error is an error, and the single and double error value calculating section 9A is a circuit that calculates one error value for a single error and two error values for a double error.

The second deinterleave unit 1B receives 9 bits of data output from the exclusive oragate unit 11A, the error flag addition unit, and the error value storage unit 10A. (2B), on the other hand, the second syndrome calculating section 5B, S ₀ S ₂ + S ₁ S ₂ calculating section 6B, error number determining section 7B, reliability determining section 13, and error position calculating section (8B), the corresponding operation is performed in the single and double error value calculating section 9B, and accordingly the error flag addition and error value storing section 12 outputs the error flag according to the result of the above calculation, thereby causing the execlue. The sieve oragate unit 11B adds an error flag to the data output from the data buffer 2B and an error flag output from the error value storage unit 12, and the average value interpolator 14 adds the error. Sheave OA gate part 11B, error flag addition and error value reduction When the output data of the book 10B is supplied and there is a symbol (error symbol) with an error flag of "1" between symbols (non-error) with an error flag of "0", the average value of both symbols is calculated and the value is calculated. The second error correction is terminated by replacing the error symbol.

Here, the error flag total calculation unit 12 calculates the total number of error flags in one frame during the second error correction process, and the reliability determination unit 13 determines the number of error flags in the case of no error, single error, or double error. The average range is set and compared with the value calculated by the error flag total calculation section 12. As a result, the circuit is trusted if the number of error flags falls within the set range, and is not trusted otherwise.

As a result, the data stored in the data buffer 2B and the data stored in the error flag addition and the error value storage 10B are added in the exclusive oragate unit 11B at an appropriate timing to be added to the first and second orders. Error correction is terminated.

As described in detail above, the present invention uses the simple PGZ decoding algorithm when the error correction capability is two symbols in the error determination process to simplify the error correction process, and to experience the reliability on any channel to inquire about its reliability. By calculating the average value of the number of error flags and determining the reliability thereof, there is an effect of correcting errors accurately and at high speed.

Claims (3)

(Correction) After calculating the syndromes for the received symbols in the unit of frame, if the syndromes S ₀ , S ₁ , S ₂ , and S ₃ are all 0, it is determined that the received data does not have an error symbol. If the condition is not satisfied, S ₀ · S ₂ + S ₁ · S ₁ = 0 is checked, and if it is 0, it is determined as a single error. How to correct data errors. The method of claim 1, wherein the second error correction is performed by repeating the first error correction, and a reliability determination technique is applied thereto. A deinterleave unit 1A for interleaving and restoring data recorded on the recording medium to the original information data, and under the control of the GF operation unit 3 and the control unit 4, and outputted from the first interleave unit 1A. The first data supplied to calculate syndromes (S ₀ , S ₁ , S ₂ , S ₃ ), (S ₀ · S ₂ + S ₁ · S ₁ ), number of errors, location of errors, single and double error values An error flag addition and error value storage unit 10A which adds an error flag to the output data of the first error operation unit 20, an error flag storage unit 10A, and a data buffer unit 2A. Exclusive oragate unit 11A which completes the first error correction by performing an exclusive ora operation on data input from the interleave unit 1A and data output from the error flag addition and error value storage unit 10A. ), And reconstruct each part used in the first error correction, wherein no error, a single error, The average value interpolation is performed on the final output data, and the reliability determination unit 13, which sets the average range of error flags in the case of double errors and compares it with the value calculated by the error flag total calculation unit 12, determines the reliability accordingly. A data error correction circuit comprising an average value interpolation section 14 to be performed.