KR0154470B1 - Circuit for interfacing between auxiliary processor and external device - Google Patents

Abstract

This matching circuit is for simplifying the processing of the processor in the auxiliary control device during communication between the auxiliary control device and the external device in the all-electronic exchange. The circuit includes a latch and a coding unit, a state register, a mode / address register, An internal register consisting of a data register and a control register; Transmitter that selectively transmits the signal output from the mode / address register and the data register to an external device, and transmits the signal transmitted from the external device to the data register: When an error signal is transmitted, the signal is transmitted to the mode / address register and the data register. A retransmission attempt unit requesting retransmission of the stored signal; Transmission control unit for controlling the transmission operation of the signal transmission unit: DTACK generation that generates a signal indicating the normal data transfer status (DTACK) by the transmission assert signal (TAST), the received assert signal (RAST) and the error signal (ERR) And a portion 670.

Description

Matching circuit between auxiliary controller and external device

1 is a block diagram between a conventional auxiliary control device and an external device.

2 is a detailed view of the matching circuit shown in FIG.

3 is a process flow diagram of the processor shown in FIG.

4 is an operation timing diagram between external devices of the auxiliary control apparatus shown in FIG.

5 is a block diagram between an auxiliary control device and an external device according to the present invention.

6 is a detail view of the matching circuit shown in FIG.

7 is an operation timing diagram between an external device and an auxiliary control device according to the present invention.

8 is a process flow diagram of a processor according to the present invention.

* Explanation of symbols for main parts of the drawings

600: latch and coding unit 610: internal register

620: control signal transmission unit 630: multiplexer / demultiplexer

640: multiplexer / demultiplexer control unit 650: retransmission attempt unit

660: interrupt processing unit

670: DTACK (DaTa ACKnowledge) generation unit

The present invention relates to a matching circuit between an auxiliary control device and an external device in an all-electronic exchange, and more particularly, to a matching circuit for efficient operation of a processor in an auxiliary control device during communication between the auxiliary control device and an external device.

The electronic switchboard is operated with a main control unit that manages all functions and an auxiliary control unit that specializes in one or more functions under the control of the main control unit. The external device is controlled by the above-described auxiliary control device to perform a corresponding function, for example, an input / output device. The external device and the auxiliary control device are provided with a matching circuit 102, also referred to as a communication bus controller, between the processor 101 and the external device 110 in the auxiliary control device 100 as shown in FIG. Mode and Wait DTACK mode.

The wait DTACK mode is a method of terminating a cycle when a DTACK signal, which is a transmission end signal, is transmitted after transmitting information necessary for communication in the processor 101 to the external device 110 through the matching circuit 102. As described above, a matching circuit configured to include an address decoder 200, a data decoder 210, an internal register 220, a control signal transmitter 230, a multiplexer / demultiplexer 240, and an encoder 250 ( 102 will be described in more detail below.

First, the processor 101 sets the mode of the control register 224 in the matching circuit 220 to the Wait DTACK mode. In the setting process, like the other registers to be described later, the processor 101 provides an address for designating the control register 224 through the address decoding unit 200, and the information according to the mode setting is provided through the data coding unit 210. When transmitted, the control register 224 is set to the Wait DTACK mode.

When the information to be transmitted from the processor 101 is generated after the data transmission preparation process is completed, the processor 101 checks the contents of the status register 221 in the matching circuit 102 to determine whether the bus can be used. (Step 301 of FIG. 3). The verification operation is performed by the address decoding unit 200 enabled by the address enable signal AS_ provided by the processor 101 to decode the address signal A [19: 0] transmitted from the processor 101. One value is achieved by designating the state register 221. The status register 221 informs the processor 101 whether the bus is used through the data coding unit 210.

As a result of the check, if the bus is available, the processor 101 addresses the mode / address register 222 to be designated to the address decoding unit 200 in order to write the necessary mode to the mode / address register 222 in the internal register 220. The data coding unit 210 transmits and writes mode data to be written (step 302 of FIG. 3). Through the same process as that described above, the processor 101 writes the corresponding address (step 303 of FIG. 3). Data to be transmitted is written to the data register 224 (step 304 of FIG. 3). The matching circuit 102 outputs the contents described in the mode / address register 222 and the data register 223 through the multiplexer / demultiplexer 240, and the output signal is outputted through an EIA-422 cable. It is transmitted to the 110 (step 305). As shown in FIG. 4, an address of the data transmitted as described above is transmitted in a 4-bit parallel form when frame frame SYNC is active in synchronization with the system clock signal SCLK transmitted from the processor 101. The transmission data TXD is transmitted while the ready signal RDY_ transmitted from the external device 110 is active.

When data is received from the external device 110 (that is, when data is read), after the address data transmission, the ready signal RDY_ transmitted from the external device 110 is activated, and then half a clock is received.

Since the data transfer process is performed in the wait mode, the processor 101 proceeds from step 306 to step 307 of FIG. 3 and checks whether the transmission termination signal is transmitted. Sum) Check for errors. If an error does not occur as a result of the test, the transmission is terminated. If an error occurs, the process returns to step 302 to process. The transmission end signal checks the state register 221 by the control register 224. When the ROY_ signal transmitted from the external device 110 is converted from the active state to the inactive state, the external device 110 is checked. The DTACK signal transmitted from the encoder is transmitted through the encoder 250. When the transmission end signal is transmitted, the processor 101 completes the transmission process.

However, in this case, the data transmission clock is set to several MHz so that the processor 101 must continuously perform data transmission related work until the data transmission is completed.

In the early DTACK mode, the processor 101 writes information necessary for transmission to the internal register 220 in the matching circuit 102, and then reads the state register 221 of the matching circuit 102 so that the matching circuit 102 reads the external device. The method of completing the information transmission process through the process of confirming whether the information transmission is completed at 110. The process of performing the early DTACK mode is performed in the same manner as the Wait DTACX mode described above. However, the processor 101 directly reads the status bit into the status register 221 to determine the completion of information transmission. That is, the process proceeds from step 306 to step 308 to read the status bit of the state register 221, and if the transmission completion bit is set (step 309), proceeds to step 310 and processes as described above. At this time, the status bit of the state register 221 is determined by the control signal transmitted from the control signal transmitter 230. In this manner, data transfer from the auxiliary control apparatus 100 to the external apparatus 110 is performed as in the Wait mode described above.

However, even in this case, the processor reads the status register based on software to confirm that the transfer is completed. Therefore, the processor must continuously perform data transfer operations until the transfer is completed. It was a factor that lowered the overall performance.

Accordingly, an object of the present invention is to provide a subsidiary control for simplifying the processing of the processor by simplifying the information processing process after outputting the information required by the processor in the subsidiary control device when communicating between the subsidiary control device and the external device to solve the above problems. It is to provide a matching circuit between a device and an external device.

The matching circuit according to the present invention is a matching circuit for matching between a processor in an auxiliary control device and an external device during communication between an auxiliary control device of an electronic switch and an external device, and is controlled by a control signal transmitted from the processor. It consists of a latch and coding section, a status register, a mode / address register, a data register, and a control register for latching and coding a signal transmitted from the memory, and stores the signal transmitted from the latch and coding section. An internal register for transmitting information to the latch and coding unit, comprising: a control signal transmitter for transmitting a control signal transmitted from an external device to a state register; A signal transmission unit for selectively transmitting a signal output from the mode / address register and the data register to an external device, and transmitting a signal transmitted from the external device to the data register; A retransmission attempt unit requesting retransmission of a signal stored in a mode / address register and a data register when an error signal is transmitted from an external device; controlling the transmission operation of the signal transmission unit by the output signal of the retransmission attempt unit and the output signal of the control register Transmission control unit for: The normal data transmission state (DTACK) by the transmission assert signal (TAST) provided from the signal transmission unit and the received assert signal (RAST) and error signal (ERR) provided from the external device 510 Characterized in that it comprises a DTACK generator 670 for generating a signal.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

5 is a block diagram between an auxiliary control device and an external device according to the present invention, and replaces the auxiliary control device 500 configured to include the processor 501 and the matching circuit 502 and a Pseudo instead of a conventional EIA-422 cable. The external device 510 is connected using an ECL cable.

FIG. 6 is a detailed view of the matching circuit 502 shown in FIG. 5 and includes a latch and coding unit 600 and a state register for latching and coding information applied under the control signal transmitted from the processor 501. 611, an internal register 610 composed of a mode / address register 612, a data register 613, a control register 614, and a control signal transmitted from the external device 510 to the above-described status register 611. The control signal transmitting unit 620 transmits information selectively outputted from the mode / address register 612 and the data register 613 in the write mode, and the data transmitted from the external device 510 in the read mode. A multiplexer / demultiplexer 630 serving as a signal transmission to be transmitted to the data register 223, a retransmission attempting unit 650 which retries information transmission by an error signal (ERR) signal transmitted from an external device 510, retransmission city A multiplexer / demultiplexer controller 640 which controls signal transmission by controlling the operation of the multiplexer / demultiplexer 630 described above by a logical combination of a signal output from the unit 650 and a signal output from the control register 614. ), An error occurs due to an interrupt processor 660 for transmitting an interrupt signal to the processor 501 and a TAST (TXD ASSERT) signal and a RAST (RXD ASSERT) signal when the retransmission attempt unit 650 does not retry. If the check period is controlled to prevent an error, the DTACK generator 670 is configured to generate a DTACK signal.

By the matching circuit 502 configured as described above, the processor 501 performs a cycle as a write or read cycle of a memory. That is, when the chip select signal CS_ is transmitted from the processor 501 to the active state, the latch and coding unit 600 enters the enable state and latches all the input signals.

In this case, when the R / W_ signal transmitted from the processor 501 is in the write mode, the state register 611 in the internal register 610 is used to transfer data from the auxiliary control device 500 to the external device 510. Check if the bus is used. The use of the bus through the state register 611 is performed by checking the state bit set by the control signal transmitted from the external device 510 through the control signal transmitter 620.

If the bus can be used, the mode / address register 612 and the data register 613 are designated according to the address signals stored in the latch and coding unit 600, and the corresponding data is stored in the control register 614. By using the multiplexer / demultiplexer 630, the data stored in the mode / address register 612 and the data register 613 are changed into the COMMAND MODE (C / M) bit, the BANK bit, Controls serial transmission of address bits, data bits, and checksum bits. At this time, if an error does not occur in the transmission to the external device 510, the multiplexer / non-multiplexer control unit 640 is driven by a control signal output from the control register 614 to operate the mode / address register 612 and the data register 613. Selectively output the signal output from). However, when a transmission error occurs from the external device 510, the retry control unit 650 transmits a retry control signal to the multiplexer / demultiplexer controller 640 so that transmission from the C / M bit to the data bit is performed again. .

Accordingly, the multiplexer / demultiplexer control unit 640 controls the transmission of the multiplexer / demultiplexer 630 by giving priority to the data transmitted from the retransmission attempt unit 650. If an error occurs in spite of such transmission control, the retransmission attempting unit 650 retryes again. The retry process is performed a predetermined number of times, and when the predetermined number of times is exceeded, the interrupt request signal is transmitted to the interrupt processor 660. The interrupt processor 660 transmits an interrupt request signal IRQ to the processor 501 using a signal input from the retransmission attempt unit 650 and FC [2: 0] and ADDR [19:16].

Accordingly, the processor 501 processes the interrupt routine according to the transmission error.

The signal output from the multiplexer / demultiplexer 630 is serially transmitted to the external device 510 through the pseudo ECL cable.

In the write mode, the DTACK generator 670 receives an error signal ERR from the external device 501 when the TAST (TXD ASSERT) signal output from the multiplexer / demultiplexer 630 is converted from the active state to the inactive state. If not, the DTACK is transmitted to the processor 501 to inform the processor 501 that the information transmission is normally performed. As a result, the processor 501 terminates the information transmission process.

Meanwhile. In the read mode, as shown in FIG. 7, the C / M, BANK, and address signals are serially transmitted from the matching circuit 502 to the external device 510 as described above. With a delay time, it is checked whether an error has occurred from the external device 510. If no error occurs at this time, corresponding data and checksum values are transmitted from the external device 510 through the multiplexer / demultiplexer 630, as illustrated in the read timing diagram of FIG. The data is transmitted to the coding unit 600 and transmitted to the processor 501.

However, if an error occurs while the RAST signal generated from the external device 510 becomes active after transmitting the C / M, BANK, and address signals, the C / M bit that is currently transmitted by the retransmission attempt unit 650 starts. The address bit is transmitted again. However, if no error occurs, the DTACK generation unit 670 transmits a DTACK signal to the processor 501 at the time when the RAST signal is switched from the active state to the inactive state to inform that the information has been transmitted normally. Accordingly, the processor 501 completes the information transmission process.

When the processing is performed as described above, the processor 501 transmits the address and data in step 801 as shown in FIG. 8, and then proceeds to step 802 to determine whether the transmission ends by the DTACK signal applied. In the transmission termination state, the external device 510 may be processed only by the process of terminating the transmission process.

As described above, the matching circuit according to the present invention simplifies the processing of the processor by reliably processing the hardware as if the necessary information is generated from the processor when the auxiliary control device communicates with the external device as if the memory device is accessed. Not only does it reduce the load on the system, but it also has the effect of allowing the program to be written at a high level.

In addition, the transmission or reception clocks (TXCLK, RXCLX), which determines the data rate using the pseudo ECL cable between the auxiliary control device and the external device, have been increased from several MHz to several tens of MHz, and the number of transmission cables is increased. Increasing stabilization of the system, thereby improving the reliability of the product, and has contributed to reducing the price of the product.

Claims (6)

In the matching circuit for matching between the processor 501 and the external device 510 in the auxiliary control device 500 during communication between the auxiliary control device 500 and the external device 510 of the electronic switchboard, the processor A latch and coding unit (600) for latching and coding a signal transmitted from the processor (501) by being controlled by a control signal transmitted from the processor; It consists of a state register 611, a mode / address register 612, a data register 613 and a control register 614 to store a signal transmitted from the latch and the coding unit 600, the data in the read mode An internal register 610 for transmitting information stored in the register 613 to the latch and coding unit 600; A control signal transmitter 620 for transmitting a control signal transmitted from the external device 510 to the status register 611; The signal output from the mode / address register 612 and the data register 613 is selectively transmitted to the external device 510, and the signal transmitted from the external device 510 is transmitted to the data register 613. Signal transmission unit 630 for transmitting to; A retransmission attempt unit 650 for requesting retransmission of signals stored in the mode / address register 612 and the data register 613 when an error signal ERR is transmitted from the external device 510; Transmission control unit 640 for controlling the transmission operation of the signal transmission unit 630 according to the output signal of the retransmission attempt unit 650 and the control register 614: in the signal transmission unit 630 DTACK generation that generates a signal indicating a normal data transfer state DTACK by the provided transmit assert signal TAST, the received assert signal RAST provided by the external device 510, and the error signal ERR Matching circuit between the auxiliary control device and the external device, characterized in that it comprises a portion (670). The matching circuit according to claim 1, wherein the signal transmission unit (630) is configured to transmit and receive data in series with the external device (510). The multiplexer and the external device 510 of claim 2, wherein the transmission controller 630 selectively outputs information output from the mode / address register 612 and the data register 613 to the external device 510. And a demultiplexer which transmits data transmitted from the data to the data register (614). The DTACX generating unit 670 of claim 1, wherein the DTACX generation unit 670 is configured to perform a predetermined period of time after the transmission assert signal is converted from an active state to an inactive state in a write mode from the processor 501 to the external device 510. The generation of the DTACK signal is controlled by checking whether an error signal is generated, and the DTACK is checked by generating the error signal when the transmitting assert signal and the receiving assert signal are inactive at the same time in the read mode. A matching circuit between an auxiliary control device and an external device, characterized in that it controls the generation of a signal. The matching circuit of claim 1, wherein the retransmission attempt unit (650) requests an interrupt signal to the processor (501) when the number of retransmission attempt requests exceeds a predetermined number. The matching circuit according to claim 1 or 3, wherein the matching circuit (502) is configured to be connected to the external device (510) through a pseudo ECL cable.