JPS6410975B2 - - Google Patents

Description

[Detailed Description of the Invention] Industrial Application Field The present invention relates to a frame synchronization device for frame synchronization and synchronization protection in the demodulation of PCM broadcasting signals. It can be used for demodulating audio signals, etc.

Conventional configurations and their problems Plans are being considered in many countries to convert the audio of television broadcasts using direct broadcast satellites or dedicated audio broadcasts to PCM. In our country, 1982
It has already been decided that the PCM system will be used for audio in the television satellite broadcasts scheduled to begin in 2019.

By the way, in the transmission of such PCM signals, a frame structure consisting of a fixed number of bits is usually used, and a frame synchronization pattern is installed in this frame in order to synchronize the frames on the receiver side. . In order to detect the position of this frame synchronization pattern, the receiver side performs pattern matching with the true frame synchronization pattern, and outputs a pattern match signal if all bits match or even if some bit errors are tolerated. I will do it. If this frame synchronization is not accurate and stable, demodulation of the PCM signal will be completely impossible. Therefore, it is important for the frame synchronization circuit to firstly prevent synchronization from occurring in a location other than the synchronization pattern, and secondly to be able to maintain synchronization even if there are slight bit errors once synchronization has been achieved. be.

FIG. 1 is conventionally used for this purpose. 1 is a block diagram showing the configuration of a frame synchronization circuit having a synchronization protection function called a contention counter system. FIG. In the figure, reference numeral 1 denotes a frame synchronization pattern detection means, which detects a frame synchronization pattern from an input digital code sequence and outputs a match signal and a mismatch signal. A match or a mismatch is determined based on whether or not the number of bits that match the true synchronization pattern in the code length of the frame synchronization pattern is greater than or equal to a predetermined threshold. 2 and 3 are counting means,
When the counting results reach N and M, respectively, output signals are issued to set and reset the flip-flop 5, and to reset both counting means 2 and 3 via the OR circuit 4. The output of the flip-flop 5 is at a high level in a synchronous state and at a low level in an asynchronous state.

In this configuration, if the match signal is output N times before the mismatch signal is output M times from the pattern detecting means 1, the flip-flop 5 is set and enters a synchronized state. After the synchronization state is established, when mismatch signals are generated intensively, the output from the counting means 3 is outputted first and resets the flip-flop 5.
It becomes an asynchronous state. By the way, the counting means 2 and 3 do not operate with the function of a mere counter as described above, but in order to further improve the characteristics, for example, the counting means 2 outputs an output only when a coincidence signal is inputted N times in a row. It can be configured to emit. Using this method as an example to receive domestic satellite broadcasting, its characteristics will be explained.

The above-mentioned broadcast PCM audio is transmitted in frames each consisting of 2048 bits, of which 16 bits are given as a frame synchronization pattern. Now, if the threshold value of the number of matching bits in the pattern detection means 1 is A, then the probability of accidentally generating a matching signal at a location other than the frame synchronization pattern is
P ₁ is P ₁ = (1/2) ¹⁶ + (1/2) ¹⁵・₁₆ C ₁・(1/2)
+... +(1/2) ^A・₁₆ C _16-A (1/2) ^16-A =2 ^-16・(1+ ₁₆ C ₁ +...+ ₁₆ C _16-A ) ...(1) First In the frame, there is a possibility that the above situation will occur 2048 (=2 ¹¹ ) times in one frame, so P _1(I) = P _E・2 ¹¹ =2 ^-5・(1+ ₁₆ C ₁ +... + ₁₆ C _A ), but the probability of erroneously issuing a coincidence signal at the same location as the first frame from the second frame onwards is P _1(K) = P ₁ (K is an integer of 2 or more). Therefore, the probability P ₁ ′ of erroneously issuing a matching signal at the same location in the frame N times in succession is P ₁ ′ = P _1(I)・(P ₁ ) ^N-1 = 2 ^-(16N-11)・(1 + ₁₆ C ₁ +... ₁₆ C _16-A ) ^N ... (2) On the other hand, in this example, one frame is sent every 1 ms, so the average period T ₁ for producing an erroneous output from the counting means 2 is T ₁ = 1/P ₁ ′ (ms) = 2 ^16N-11・(1+ ₁₆ C ₁ +...+ ₁₆ C _16-A ) ^-N (ms) ...(3) It can be expressed as follows.

Next, once the frame synchronization state is entered, the probability that synchronization will be canceled by mistake due to a bit error is P ₂
If the bit error rate of the input signal is E, then P ₂ = 1-(1-E) ^16-16 _{C 1 ・}(1-E) ¹⁵・E-... ₁₆ C _16-A・(1-E) ^A・E ^16-A Therefore, the probability P ₂ ′ of issuing a mismatch signal M times consecutively at the position of the original frame synchronization pattern is P ₂ ′ = (P _2)M The average period of producing an incorrect output from the counting means 3 T _{2 is} T ₂ = 1/P ₂ ′ = {1-(1-E) ^16-16 C ₁・(1-E) ¹⁵・E …… ₁₆ C _16-A・(1-E) ^A・E ^16-A } ^-M (ns) ...(4). As is clear from equations (3) and (4), the larger the threshold value A is, the better in order to increase the average period of erroneous output T ₁ , and conversely, in order to increase the average period of erroneous output T ₂ The smaller the threshold value A, the better. Now, if N = 3 and M = 5, and the bit error rate E is the worst expected value of 10 ^-1 , then for the value of A,
The values of T ₁ and T ₂ are as shown in Figure 2. It is desirable that the value of A is 15 or more in order to obtain a T ₁ that causes no practical problems, but it can be seen that such a value makes T ₂ too short.

OBJECTS OF THE INVENTION An object of the present invention is to provide a frame synchronization device for a PCM broadcast receiver that can provide strong frame synchronization protection even when the bit error rate of an input digital signal deteriorates.

Structure of the Invention The frame synchronization device of the present invention includes pattern detection means that outputs a coincidence signal when the number of bits that match a true frame synchronization pattern is equal to or greater than a threshold value, and outputs a mismatch signal when it is less than a threshold value. The device enters a synchronized state with N consecutive match signals from this detection means, releases this synchronized state with M consecutive mismatch signals, and sets the above threshold for the number of matching bits to the synchronous state and the asynchronous state. It is configured to switch depending on the state. As a result, strong frame synchronization protection can be obtained without setting large values of N and M.

DESCRIPTION OF EMBODIMENTS Hereinafter, embodiments of the present invention will be described with reference to the drawings.

FIG. 3 is a block diagram showing one embodiment of the present invention. In the diagram, 1' is a pattern detection means capable of switching the threshold value of the number of matching bits in accordance with the output of the flip-flop 5. When the output of the flip-flop 5 is at a low level, that is, in an asynchronous state, the threshold value is A ₁ and in a synchronous state, the threshold value is A ₂ .The threshold value is normally set to A ₁ A ₂ .
FIG. 4 is a block diagram showing an example of the internal configuration of the pattern detection means 1'. The input digital code is read into a shift register 6 having the same number of stages as the code length of the frame synchronization pattern. The output of the shift register 6 is taken out in parallel and input to the pattern matching circuit 7. The matching circuit 7 detects the number of matching bits with the true frame synchronization pattern and has two outputs indicating whether the detected value is greater than or equal to _A1 and whether or not it is greater than or equal to _A2 . Next, the selection circuit 8 selects a signal indicating whether the switching signal is at least A ₁ when the switching signal is at a low level, and whether or not it is at least A ₂ when the switching signal is at a high level, and outputs it as a match signal. The mismatch signal can be obtained by inverting the match signal using an inverting circuit 9. By making it possible to independently set the threshold value for the number of matching bits depending on the synchronous state and asynchronous state, it is possible to realize a frame synchronization device that is extremely resistant to bit errors. In the case of Figure 3, if we set A ₁ = 16 and A ₂ = 12, we get
It is possible to obtain synchronization protection characteristics that pose no practical problems. FIG. 5 shows an example of the configuration of a pattern matching circuit that allows arbitrary threshold setting. In this example, the frame sync pattern is "0001001101011110".
It is 16 bits. 10 to 17 are inverting circuits, and the error-free frame synchronization pattern is the shift register 6.
appears at the output of the 1-bit full adder circuit 18~
All 25 inputs are arranged to be at high level. 26 to 29 are 2-bit full adders, 30 and 31 are 3-bit full adders, and 32 is a 4-bit full adder. With these adders, the number of bits that match the true frame synchronization pattern is Adder 3
2 outputs can be obtained. Comparison circuits 33 and 34 compare the magnitudes with A ₁ and A ₂ , respectively. Once the specific values of A ₁ and A ₂ are determined, the comparison circuit 33,
34 can be realized by a combination of simple logic gate circuits. FIG. 6 shows an example of the configuration of the counting means 2 which outputs an output signal when a matching signal is inputted N times in succession. The match signal is read into the shift register 35 connected in N stages one after another, and when it is inputted N times in succession,
Output signal (high level) by AND gate 36
is obtained. The configuration of the counting means 3 is the same as that shown in FIG. 6, except that the number of stages of the shift register is M.

In the above description of the embodiment, the pattern detection means and the counting means have been shown to be configured by logic circuits, but it is also possible to use a microprocessor programmed with a procedure for obtaining the same functions.

Effects of the Invention As described above, by using the present invention, extremely strong synchronization protection can be obtained with relatively small set values of N and M. Furthermore, by combining the values of N and M with the threshold values A ₁ and A ₂ , a highly flexible frame synchronization device can be designed according to the expected input error rate and the required synchronization protection. I can do it.

[Brief explanation of the drawing]

Fig. 1 is a block diagram showing a conventional frame synchronization device, Fig. 2 is a characteristic diagram showing the relationship between the threshold value of the number of matching bits and the average malfunction period, and Fig. 3 is an embodiment of the frame synchronization device according to the present invention. 4 is a block diagram showing the structure of the pattern detection means of the same device, FIG. 5 is a block diagram showing the structure of the pattern matching circuit of the same device, and FIG. 6 is the structure of the counting means of the same device. FIG. 1'...Frame synchronization pattern detection means, 2,
3... Counting means, 5... Flip-flop, 6...
...Shift register, 7...Pattern matching circuit, 1
8 to 32...Full adder.

Claims (1)

[Claims] 1 A frame synchronization device for a PCM broadcast receiver that receives a digital signal sent out having a frame structure including a frame synchronization pattern consisting of multiple bits, and which detects this frame synchronization pattern by detecting a true frame synchronization pattern. Outputs a match signal when the number of matching bits is greater than or equal to the threshold,
A frame synchronization state is entered by N consecutive match signals from the pattern detection means configured to output a mismatch signal when the value is less than a threshold value, and this synchronization state is entered by M consecutive match signals from the pattern detection means. 1. A frame synchronization device for a PCM broadcast receiver, characterized in that a determining means for canceling the above-mentioned matching bit number, and a switching means for switching the threshold value of the number of matching bits between a synchronous state and an asynchronous state.