JPS6360938B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to the transmission of pulse code modulated voice and control data between a common multiplex and control circuit on the one hand and multiple individual line interface circuits on the other hand. Concerning digital busbar systems which are particularly suitable for.

In telecommunication switching systems using digital communications, it is common practice to multiplex multiple PCM encoded analog voice signals onto a common data transmission path. The PCM encoded signals are coupled via a digital switching system in which the signals are distributed according to address control information. Due to the high reliability requirements of such systems,
All major networks of the system can be duplicated or if one section fails the other section can take over, the only disadvantage being that there is some loss of access to the system during busy periods. It is.

Traditionally, time division multiplexed PCM (Pulse Code Modulation) data is distributed from a switching system to multiple line circuits via a common bus system using address control to access each line circuit during its assigned time slot. . A major weakness of such systems is that if the input to one of the line circuits causes a short circuit, the bus containing the balance of the line circuits connected to the line circuit will be disconnected even if there are no extra components ( redundant
This means that even if a component) is provided, the service will not be available.

This drawback of the prior art is due to busbar systems in which a separate single data line is formed between each line circuit and a pair of multiplexers, any one of which can access each of the data lines alternately. can be overcome in the present invention by providing. The multiplexers are alternately activated by a single gate such that only the failure of this gate in a particular mode inhibits both multiplexers. All communications between the multiplexer and the line circuits are carried over these single data lines so that if one fails, only the associated line circuit is out of service. Furthermore, the single clock signal is distributed to all line circuits by a common bus with sufficient isolation so that a failure in a line circuit does not affect the clock signal coupled to the balance of that circuit. No other synchronization or timing leads are used.

Thus, according to the invention there is provided a digital communication bus system comprising first and second multiplexers. Each of the multiplexers is used for decoding the sequential time division multiplexed addresses received via the address bus as well as for decoding the corresponding iterated time slots of each frame.
and means for receiving and transmitting time division multiplexed data via receive and transmit signal data paths in respective time slots. This time-division multiplex address is generated based on a selection signal (i.e., a signal containing numerical information specifying the called party) generated by the operation of the calling party's terminal, such as a telephone, and is transmitted through the switching network, the address It is sent to the multiplexer via the signal path and line-module controller. This time division multiplex address functions to select a line circuit.
The system also includes a plurality of line circuits, each of which couples information from at least one individual telephone line onto a single bidirectional data line that is commonly connected to both multiplexers. Each of the multiplexers is responsive to each decoded address for steering data received via the receive data path to an associated line circuit via its single bidirectional data line. It includes means for steering data received from the associated line circuitry via the data line into the transmission data path in two time slots following the address.

For such systems, a single data line carries all control, PCM, monitoring and status information data sequentially in both directions between the multiplexer and the line circuitry. The system uses a minimal number of leads coupled between each line circuit and the multiplexer, which avoids the manufacturing problems of mounting multiple circuits in a small space. This system also has completely redundant other components for reliability. In this system, failure of one line circuit does not affect bus operation to other line circuits.

Specific examples of the present invention will be described with reference to the accompanying drawings.

Many of the elements shown in the accompanying drawings are duplicates of each other. Generally, only one such element is shown in detail, with all other elements shown in dashed lines. If multiple elements are used, each is given a base reference letter followed by a number. We follow the usual practice of assigning zero to the first unit of each series. Thus, if 40 units are used, they are designated as 0 to 39.

Referring to FIG. 1, the system includes 40 line group networks LG-0 to LG-39.
each comprising a pair of multiplexers M-0 and M-1 and a plurality of 32 line circuits L-0 to L
-31 included. Multiplexers M-0 and M-
1 to the respective line module controllers via common buses B-0 and B-1 and 40 individual group selection leads GS-0 and GS-39.
Connected to LMC-0 and LMC-1. The duplicated line module controllers LMC-0 and LMC-1 each have four duplicated input ports P0 via dual multiple date linksMDL.
-0 to P3-1 and P4-0 to P7-1 to a central switching network (not shown). Each input port P0-0 to P7-1
has a capacity of 30 input channels in 32 time slots allowing two time slots for monitoring and control. Under normal operation, each controller acts as the primary controller for half of the line group network, and therefore
Access half of the 1280 (32x40) line circuits. Therefore, typically 640 line circuits are connected to 120 (4×
30) Having access to channels. However, one primary controller LMC-0 or
If LMC-1 or any one of its associated operating multiplexers M-0 or M-1 becomes unavailable for service, the other controller acting as a secondary controller
Takes over control of the 1280 line circuit. all
Access to the switching system can be affected during peak traffic periods because the 1280 line circuits must share 120 available channels instead of 240.

The functions of each of the controllers LMC-0 and LMC-1 are to initiate calls, collect digits, assign channels to lines, control the application of ringing signals or audio to the lines, and use the two channels assigned for monitoring and control. scanning for communicating with a central control computer in a switching network via at least a portion of a message channel in two time slots.

Referring to FIGS. 1 and 2, each of the 40 line group networks connects to the primary controller via bus B-0 (in this embodiment).
In addition to the activity control signal ACTV, which is coupled only to LMC-0, the bus B
A multiplexer M- coupled to their respective controllers through -0 and B-1.
0 and M-1 pairs. Line circuit L-0
DL-0 through DL-31 each connect subscriber loop 24 to 32 separate bidirectional data lines DL-0 through DL-31.
DL-0 to DL-31 are commonly connected to both multiplexers M-0 and M-1.

The detailed structure of the line group network in FIG. 2 is detailed below in conjunction with the timing waveforms shown in FIG. 3, where its location on each busbar is indicated by a corresponding reference letter. It will be readily apparent from the description.

In FIG. 3, each boxed waveform represents 10 bits of binary information. As mentioned above, the two channel time slots 0 and 16 are used for monitoring and control purposes. During these periods, line circuits L-0 to L-32 are selectively connected to the controller.
Scanned by LMC-0 or LMC-1. The remaining channel slots 1-15 and 17-31 are
Can be used for PCM data. In this example, for the duration of each telephone call, line circuits 4, 8, 17 and 23 (channel time slots 5, 13, 1 and 12 assigned by the controller) are connected in one line group network. traffic, while line circuits 6, 14, 17 and 29
It is assumed that (time slots 8, 26, 20 and 27 assigned by the controller) are carrying traffic in one or more other line group networks. Furthermore, line circuits 8 and 9 of one line group network are scanned during time slots 0 and 16 of one frame, respectively, while channels 10 of the other line group network are scanned during time slots 0 and 16 of one frame, respectively.
is scanned during time slot 0 of the next frame. The channel balance for this port is idle at this time.

Typically the 10-bit address ADDR for the network from their primary controller is bus B.
-0 and B-1 to series/parallel converter 1
0. After a complete address is received, the parallel outputs of converter 10 are under control of group select signal G-S and channel pulse C-P (indicating the start of each 10-bit channel period) during subsequent time slots. is loaded into the receiving address register 11. The output of register 11 then enables demultiplexer 12, which then receives the received serial data RDAT, which is passed through AND gate 13 under the control of delay group selection signal GS. It is coupled to the signal input of the demultiplexer 12. The serial data RDA is steered through the demultiplexer 12 to the selected data line where it is routed to the selected line circuit L-0.
to the inputs of L-32. In this example, channel 8 at time slot 0
The address ADDR for is the group selection signal G
-S causes the received control data RCTL of the receive data path RDAT to be directed to the line circuit L-8 during time slot 1. Similarly, address ADDR during time slot 1 is G-
With S, the received PCM data RPCM of the receive data path RDAT is directed to line circuit L-17 during time slot 2, and so on. However, the address for channel 6 that occurs during time slot 8 is
The absence of the delayed group selection signal G-S at the input to (NB-RDATA in FIG. 3) does not prepare the demultiplexer 12 in the one group selection network. However, it provides an alternative group selection network if the signal G-S is applied to it via another group selection lead G-S as shown in FIG.

At the end of time slot 1, the address in register 11 is shifted for transmission into address register 14, which transfers the incoming information TDATA from the selected line circuit to the transmission data path TDAT, delayed by two time slots. Multiplexer 15 is prepared to steer through AND gate 16 which is opened by group selection signal GS. This is illustrated in FIG. 3, in which the scanning information XSCN from line circuit 8 is transmitted during time slot 2 via data line DL-8, and the XPCM information from line circuit 17 is transmitted via data line DL-8. is the data line DL-17 and the transmission data path during time slot 3.
Transmitted via TDAT.

Activity signal ACTV from primary controller LMC-0 primes both CLK and demultiplexer 12. During normal operation, different channel information is transmitted to each of multiplexers M-0 and M-1. This is because they are driven by controllers LMC-0 and LMC-1, respectively, each acting as a primary controller for a different half of the 1280 line circuits. However, since each ACTV signal activates only one multiplexer M-0 or M-1 at a time, channel data going to an inactive multiplexer is not transmitted to its associated line circuit. Controller LMC-0 or LMC
-1 or operating multiplexer M-0
or failure of any one of M-1 is sensed by the other controllers and the switching network. This connects the ACTV signal to Line Group Network LG
-0 through LG-39 from the affected multiplexer so that other multiplexers in the network can take over. At the same time, channel information for that line group network is routed from the switching network through the secondary controller to its associated multiplexer.
Therefore, line circuits L-0 to L-31 continue to function via the common data line DL. An inactive multiplexer is continuously monitored by its associated controller through test codes sent via the RDAT, TDAT using a specific address code. Detection of a fault will result in an alarm for repair, but will not result in a switchover of the system.

Referring again to FIG. 3, the group selection signal G
-S together with the serial address signal ADDR,
Determine the line to be accessed by the controller during two consecutive time slots during each channel. Actual data (PCM or control/
The scan) is transmitted serially to the line group via the receive data RDAT bus and to the controller via the transmit data TDAT bus. Each data exchange extends over a period of three channel time slots. In a first period, a line address is transmitted, in a second period, data is received by the line circuit from the controller, and in a third period, data is transmitted from the line circuit to the controller. Thus, during the second and third periods, the operating multiplexer M-0 or M-1
is transparent to the data to be transmitted or received from the selected line circuit.
Accesses to different line circuits during sequential transactions overlap in time allowing efficient use of all 32 channel time slots. The only restriction is that the same line is not accessed in successive channel time slots. Thus, in the specific example, PCM data information for channel 8 cannot be received or transmitted during timeslots 1 and 2. This is because the control and scanning information for that channel occupies these periods. To avoid overlap, even scan/control addresses are transmitted during timeslot 0, while those for PCM data for even address lines are never transmitted during timeslot 31 or 1. Odd scan/control addresses are transmitted during timeslot 16, while those for PCM data for odd address lines are never transmitted during timeslots 15 or 17.
Various other arrangements are also possible.

Referring again to the enlarged portions of FIGS. 2 and 3, data on data line DL-8 (not specifically shown in FIG. 2 - typical data line
(see DL-1 and line circuit L-1) is the clock
CLK is received by line control circuit 21 in line circuit L-1 under control of CLK. Each bit exchange between the line circuit and the controller is initiated by a start bit S=1 (see enlarged part of FIG. 3). This is followed by a mode bit M=1 indicating that control/scan information comes next or M=0 indicating that PCM information comes next. After receiving bit M=1, the 8-bit control data RCTL is transmitted from the controller to the line control circuit 21. This information, which provides control for ringing or operation of multiple test functions, is steered into a scan and control register 22 where it is used to operate a line interface circuit 23 connected to a subscriber loop 24. be done. This is followed by 8 bits of scanning information, XSCN, which transmits status and dialing information from the line circuit to the controller. Finally, the line status LS and on/hook supervisory SV bits are again transmitted from the line circuit during the last two bit exchange period.

Every line, whether it is carrying traffic or not, is accessed for scanning and control once every n x 5 msec, 5 msec being the basic cycle time of the controller. The value of n depends on the number of lines scanned and the state of the lines (monitoring or transmitting).

During the PCM information exchange period, start bit S=
1 and mode M=0 followed by an 8-bit RPCM transmitted from the switching network through the controller to the line circuit. These 8 bits are passed through the line control circuit 21 to the codec.
It is steered to 25. Codec 25 converts the RPCM signal to analog form for transmission through line interface circuit 23 to subscriber loop 24. Conversely, the encoded analog samples SPCM are transmitted from the codec 25 through the line circuit 21 and through the controller to the switching network. Again, the line status LS and supervisory SV are transmitted to the controller at the end of this data exchange. The S and T leads between circuits 21, 22 and 25 provide starting and timing information in a well known manner.

In another aspect, the channel information provided to the input ports through P0-0 through P3-1 may be a duplicate thereof to ports P4-0 through P7-1, respectively. In this arrangement, both multiplexers M-0 and M-1 transmit and receive the same information even if only one of any pair is activated by the ACTV signal at any time.

In yet another aspect, several telephone line circuits (e.g., 4) are serviced by a single bidirectional data line in which all lines in the line group network (e.g., 32) are accessed in a fixed sequence from a multiplexer. can be done. All line circuits of a single data line are accessed sequentially such that only a single synchronization pulse (one per frame) is needed in addition to the clock signal to identify the start of the sequence.

In this arrangement, failure of one line circuit may render the balance of line circuits (eg, the other three) coupled to its associated bidirectional data line unserviceable. However, the balance of lines in the line group network is not affected.

[Brief explanation of drawings]

FIG. 1 is a schematic block diagram of a complete bus system for a line module using a redundant controller with multiple line group networks;
2 is a detailed illustration of one of the line group networks of FIG. 1 showing the interconnection of a multiple line circuit with two multiplexers; FIG. FIG. 3 is a diagram showing timing signals of FIG. 11... Address register, 15... Multiplexer, 24... Subscriber loop, LG-0 to LG
-39……Line Group Network, LMC
-0 and LMC-1... Line module controller, M-0 and M-1... Multiplexer, L-0 to L-31... Line circuit, DL-0
~DL-31...Bidirectional data line.

Claims (1)

[Scope of Claims] 1. comprising first and second line-module controllers respectively controlling first and second multiplexers in each of a plurality of line group networks; transmits sequential time-division multiplexed addresses received via address signal paths to each of the multiplexers; receives time-division multiplexed data from each of the multiplexers via receive and transmit signal paths; In a digital communication bus system in which each of the first and second line-module controllers has means for transmitting time-division multiplexed data to each, each of the line group networks includes a plurality of line circuits, and each of the line group networks includes a plurality of line circuits; each coupling an individual telephone line to a separate bidirectional data line commonly connected to said first and second multiplexers, each of said multiplexers decoding each of said addresses. means for, in response to each decoded address, to associate data received from the controller via the receive signal path via the separate bidirectional data lines in two time slots following that address; and means for steering data received from the associated line circuit to a transmission signal path via the separate data lines, the first line module controller being responsive to a control signal from the first line module controller. A digital communications bus system, comprising means for activating one or the other of the first or second multiplexer. 2. Each line circuit receives control data from and transmits state data to the line module controller with a sequential bias in one of at least two selected time slots of each frame, so that each active line The circuit transmits the information data to the line module controller that receives the information data from the line module controller via the associated multiplexer in other selected time slots of every frame, and transmits the information data to the line circuit. 2. The bus system of claim 1, wherein the controlling address time slot does not immediately precede or immediately follow the controlling address for control and status data for that line circuit. 3. A separate group selection control signal is transmitted to each line group network simultaneously with the transmission of the address for that network, and each multiplexer delays the group selection control signal by one time slot and transmits the group selection control signal over the receiving signal path. and means for gating data transmitted over the transmission signal path by delaying the group selection control signal by another time slot. Busbar system described in Section 2.