JPS6316315A - Automatic power supply cut-off system - Google Patents
Automatic power supply cut-off systemInfo
- Publication number
- JPS6316315A JPS6316315A JP61161153A JP16115386A JPS6316315A JP S6316315 A JPS6316315 A JP S6316315A JP 61161153 A JP61161153 A JP 61161153A JP 16115386 A JP16115386 A JP 16115386A JP S6316315 A JPS6316315 A JP S6316315A
- Authority
- JP
- Japan
- Prior art keywords
- counter
- signal
- computer
- power supply
- cpu
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000001514 detection method Methods 0.000 claims description 5
- 238000000034 method Methods 0.000 claims description 5
- 238000010586 diagram Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000007796 conventional method Methods 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
Landscapes
- Power Sources (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明はマイクロコンピュータを内蔵した装置の電源を
自動的に切断する電源自動切断方式に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an automatic power cutoff method for automatically cutting off the power of a device incorporating a microcomputer.
従来、マイクロコンピュータを内蔵した装置（以下装置
と称す）の電源の切断は、人間が直接行うか、または遠
隔操作により間接的に行う等の方式があるが、いずれも
装置の使用者及びシステムが意識して切断する方式であ
り、外部にタイマー装置または自動電源切断装置等を接
続する、いわゆるホストシステムのコマンド解読による
ものであった。Conventionally, there are ways to turn off the power to a device with a built-in microcomputer (hereinafter referred to as the device), either directly by a human or indirectly by remote control, but in either case, the power is turned off by the user of the device and the system. This method involves consciously disconnecting the power supply, and is based on command interpretation by a so-called host system that connects an external timer device or automatic power-off device.
上述した従来の装置では、電源切り忘れにより、（１）
消費電力が増す。In the conventional device described above, if you forget to turn off the power, (1)
Power consumption increases.
（２）装置の寿命が縮む。(2) The life of the device is shortened.
（３ン装置の稼働音が騒音になる。(The operating sound of the 3-unit equipment becomes noisy.
という問題点がある。There is a problem.
また、従来の自動電源切断方式では、
（４）外部に自動電源切断装置またはタイマー装置を設
置する為、装置への接続が困難であった。Furthermore, in the conventional automatic power-off method, (4) an automatic power-off device or timer device is installed externally, making it difficult to connect to the device.
（５）装置とはコマンドによる接続となる為、装置を含
め大がかりなシステム構成となる。(5) Since the connection to the device is made by command, a large-scale system configuration including the device is required.
（６）従って装置操作が煩雑である。(6) Therefore, the device operation is complicated.
という問題点がある。There is a problem.
本発明の目的は、消費電力を低減し、寿命を延し容易に
、かつ安価に実現できる自動電源切断方式を提供するこ
とにある。SUMMARY OF THE INVENTION An object of the present invention is to provide an automatic power-off system that reduces power consumption, extends service life, and can be easily and inexpensively implemented.
本発明の自動電源切断方式の構成はコンピュータのステ
ータス信号、バス要求信号からこのコンピュータの作動
していないアイドル状態を検出するアイドル検出回路と
、この検出回路の出力信号によって所定時間の計数を開
始するカウンタと、前記所定時間経過した前記カウンタ
の出力信号を入力とする割込コントローラと、その割込
コントローラから前記コンピュータへの割込信号に従っ
た前記コンピュータの出力命令によって切断される前記
コンピュータを含む装置の電源ブロックとを含むことを
特徴とする。The automatic power-off system of the present invention has an idle detection circuit that detects an idle state in which the computer is not operating from the computer's status signal and bus request signal, and starts counting a predetermined time based on the output signal of this detection circuit. The computer includes a counter, an interrupt controller that receives an output signal of the counter after a predetermined period of time has elapsed, and the computer is disconnected by an output command of the computer in accordance with an interrupt signal from the interrupt controller to the computer. and a power supply block for the device.
し実施例〕
次に、本発明について、図面を参照して説明する。ｃｐ
ｕがインテル８０８６ （以下８０８６と称す）の最大
モード使用時を例に説明する。Embodiments Next, the present invention will be described with reference to the drawings. cp
An example will be explained in which u uses the maximum mode of Intel 8086 (hereinafter referred to as 8086).
第１図は本発明の一実施例のブロック図である。FIG. 1 is a block diagram of one embodiment of the present invention.
装置がアイドル状態のときは、条件として、（ＩＩ）Ｃ
Ｐ Ｕが、バス含使用して読出し、書込み、割込処理、
命令フェッチのどれも行っていない（１２）ＣＰ Ｕ以
外の周辺装置がバスを使用していない
（＋３）ＣＰ Ｕが内部演算を行っていない（１４）Ｃ
Ｐ Ｕがホルト状態でない
の４項目を全て満足するときといえる。ＣＰＵの出力信
号であるステータス信号Ｓｏ、Ｓｌ、Ｓ２が全て“１゛
のときに条件（１１）、 ＜１３）、 （１４）を満足
し、またバス要求信号であるＲ Ｑ ／ Ｇ Ｔ Ｏ、
ＲＱ、／ＧＴＩが共に°“ｉ′°であればバスを使って
いないので条件（１２）を満足する。従って、ステータ
ス信号Ｓｏ、Ｓ１．Ｓ２．バス要求信号「ぐ／′Ｃ−Ｔ
Ｏ及びＲＱ／ＧＴＩが全て１“であれば、コンピュータ
がアイドル状態である。このステータス信号Ｓｏ、Ｓ１
．Ｓ２．バス要求信号ｒ丁／丁ｆｆ、ＲＱ／ＧＴ１の論
理積のアイドル検出信号ＩＤＬをカウンタ３のリセット
に入力し、カウンタ３の出力を割込コントローラ４（ま
たはｃｐｕ）の割込信号とする。ＣＰＵがアイドル状態
となると、カウンタ３のリセットが解除されカウントを
始める。一定時間（例えば約３０分）をカウントすると
カウンタ３は信号ＴＭを割込コントローラ４（またはｃ
ｐｕ＞に対し割込を要求し、電源切断を行う割込処理ル
ーチンを実行する。この処理ルーチンにおいてファイル
、データの格納等の手続きを行った後にこのＣＰＵを含
む装置の電源ブロック５に対しＩ１０命令等でｖｏｐｐ
信号が送られて装置の電源は切断され、装置の電源は信
号■ＯＦＦにて切断を制御される。また、カウント途中
でＣＰＵがアイドル状態から抜は出ればカウンタ３はリ
セットされる。When the device is idle, (II)C
PU uses the bus for reading, writing, interrupt processing,
No instruction fetches are being performed (12) No peripheral devices other than the CPU are using the bus (+3) CPU is not performing internal operations (14) C
This can be said to be the case when all four items of PU are not in the halt state are satisfied. Conditions (11), <13), and (14) are satisfied when the status signals So, Sl, and S2, which are the output signals of the CPU, are all “1,” and the bus request signals RQ/GTO,
If RQ and /GTI are both °"i'°, the bus is not used, and condition (12) is satisfied. Therefore, the status signal So, S1.S2.Bus request signal "g/'C-T
If O and RQ/GTI are all 1", the computer is in the idle state. This status signal So, S1
．． S2. The idle detection signal IDL, which is the AND of the bus request signal r/dff and RQ/GT1, is input to reset the counter 3, and the output of the counter 3 is used as an interrupt signal for the interrupt controller 4 (or CPU). When the CPU becomes idle, the reset of the counter 3 is released and it starts counting. After counting a certain period of time (for example, about 30 minutes), the counter 3 sends the signal TM to the interrupt controller 4 (or c
pu>, and executes an interrupt processing routine to turn off the power. After performing procedures such as storing files and data in this processing routine, vopp is sent to the power supply block 5 of the device including this CPU using the I10 command, etc.
A signal is sent and the power to the device is cut off, and the power to the device is controlled to be cut off by the signal OFF. Furthermore, if the CPU leaves the idle state during counting, the counter 3 is reset.
以上説明した様に、本発明によれば、装置の消費電力を
低減し、装置の寿命を延ばす効果があり、また従来の方
式に比較して容易かつ安価に実現できる。As described above, the present invention has the effect of reducing the power consumption of the device and extending the life of the device, and can be realized more easily and inexpensively than conventional methods.
第１図は、本発明の一実施例のブロック図である。 FIG. 1 is a block diagram of one embodiment of the present invention.
Claims (1)
コンピュータの作動してないアイドル状態を検出するア
イドル検出回路と、この検出回路の出力信号によって所
定時間の計数を開始するカウンタと、前記所定時間経過
した前記カウンタの出力信号を入力とする割込コントロ
ーラと、その割込コントローラから前記コンピュータへ
の割込信号に従った前記コンピュータの出力命令によっ
て切断される前記コンピュータを含む装置の電源ブロッ
クとを含むことを特徴とする自動電源切断方式。an idle detection circuit that detects an inactive idle state of the computer from a computer status signal and a bus request signal; a counter that starts counting a predetermined time based on an output signal of the detection circuit; and a counter that starts counting a predetermined time after the predetermined time elapses. and a power supply block for a device including the computer that is disconnected by an output command from the computer in accordance with an interrupt signal from the interrupt controller to the computer. Automatic power cut-off method.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61161153A JPS6316315A (en) | 1986-07-08 | 1986-07-08 | Automatic power supply cut-off system |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61161153A JPS6316315A (en) | 1986-07-08 | 1986-07-08 | Automatic power supply cut-off system |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6316315A true JPS6316315A (en) | 1988-01-23 |
Family
ID=15729601
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP61161153A Pending JPS6316315A (en) | 1986-07-08 | 1986-07-08 | Automatic power supply cut-off system |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6316315A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO1993013480A1 (en) * | 1991-12-26 | 1993-07-08 | Dia Semicon Systems Incorporated | Condition monitor method for computer system and power saving controller |
| US5430881A (en) * | 1990-12-28 | 1995-07-04 | Dia Semicon Systems Incorporated | Supervisory control method and power saving control unit for computer system |
-
1986
- 1986-07-08 JP JP61161153A patent/JPS6316315A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5430881A (en) * | 1990-12-28 | 1995-07-04 | Dia Semicon Systems Incorporated | Supervisory control method and power saving control unit for computer system |
| WO1993013480A1 (en) * | 1991-12-26 | 1993-07-08 | Dia Semicon Systems Incorporated | Condition monitor method for computer system and power saving controller |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US4851987A (en) | System for reducing processor power consumption by stopping processor clock supply if a desired event does not occur | |
| US6981163B2 (en) | Method and apparatus for power mode transition in a multi-thread processor | |
| US6832311B2 (en) | Information processing system and resume processing method used in the system | |
| EP0908823A1 (en) | System management method and apparatus for supporting non-dedicated event detection | |
| JPS59200327A (en) | Control system of peripheral device | |
| JPH0833790B2 (en) | Power shutdown device for computer | |
| JPH04130510A (en) | Power saving system for information processor | |
| US5838982A (en) | Power switch method and apparatus for preventing a failure in the power controller | |
| JPS6316315A (en) | Automatic power supply cut-off system | |
| JP2002041189A (en) | Unintegruptible power supply device | |
| US5931930A (en) | Processor that indicates system bus ownership in an upgradable multiprocessor computer system | |
| JPH05189100A (en) | Information processor | |
| JPH0883133A (en) | Computer system and clock control method for the same | |
| JPH10333790A (en) | Information processor equipped with power-saving function and power saving releasing method for the information processor | |
| JPH04238517A (en) | Power-saving control system | |
| JPH11102238A (en) | Computer system and suspend control method therefor | |
| JP2577613Y2 (en) | Information processing device | |
| KR100490392B1 (en) | Computer system having the function of alarming power button override | |
| JP2003345474A (en) | Computer system and data transfer control method | |
| JPH0651880A (en) | Information processor | |
| JPS6158019A (en) | Power keeping device | |
| JPH04152413A (en) | Battery-driven electronic equipment | |
| JPS61145617A (en) | Power supply disconnection circuit | |
| CN111158765A (en) | Device and method for controlling running state of main control chip | |
| JPH04165515A (en) | Power source controller |