JPS6265427A - Flattening method - Google Patents
Flattening methodInfo
- Publication number
- JPS6265427A JPS6265427A JP20706585A JP20706585A JPS6265427A JP S6265427 A JPS6265427 A JP S6265427A JP 20706585 A JP20706585 A JP 20706585A JP 20706585 A JP20706585 A JP 20706585A JP S6265427 A JPS6265427 A JP S6265427A
- Authority
- JP
- Japan
- Prior art keywords
- film
- semiconductor device
- resin
- resin film
- etching
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Drying Of Semiconductors (AREA)
- Formation Of Insulating Films (AREA)
- Local Oxidation Of Silicon (AREA)
Abstract
Description
【発明の詳細な説明】
(産業上の利用分野)
本発明は、半導体装置の製造工程において、特に凹凸や
段差を表面に有する半導体装置表面の平坦化方法に関す
る。DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a method for flattening a surface of a semiconductor device having irregularities or steps on the surface in a manufacturing process of a semiconductor device.
(従来の技術)
従来、大規模集積回路(LSI )の製造工程において
、多層配線の眉間絶縁膜や積層形半導体装置の眉間絶縁
膜を平坦化するKは、リンガラスフロー、樹脂絶縁法、
樹脂塗布及びエツチングなど様様な方法が用いられてい
る。例えば、第1回次世代産業基盤技術シン4ゾワム、
昭和58年7月の192ページから195(−ジ掲載の
高浜圀彦による文献“■平坦化技術1においては、スピ
ンオンガラスを用い九塗布及びエツチングによる平坦化
方法が報告されている。(Prior art) Conventionally, in the manufacturing process of large-scale integrated circuits (LSI), K for flattening the glabellar insulating film of multilayer interconnections and the glabellar insulating film of stacked semiconductor devices has been applied using phosphor glass flow, resin insulation method,
Various methods have been used, including resin coating and etching. For example, the 1st Next Generation Industrial Infrastructure Technology Syn4zowam,
In the document "■ Flattening Technique 1" by Kunihiko Takahama published in July 1982, pages 192 to 195 (-), a flattening method using spin-on glass by coating and etching is reported.
上記平坦化方法で用いるスピンオンがラスとはシラノー
ル(5l(OH)4)を主成分とする溶液であり、半導
体基板にスピン塗布し次いで熱処理によシ固化すること
((よってSIO□膜を形成するものである。The spin-on lath used in the above planarization method is a solution containing silanol (5l(OH)4) as its main component, which is spin-coated onto a semiconductor substrate and then solidified by heat treatment (thus forming an SIO□ film. It is something to do.
以下、第2図(a) 、(b) −(c)に示した半導
体装置の模式的断面図によ〕この平坦化方法の一例を説
明する。図中、1は凹凸や段差を有する半導体装置、2
はCvDS102膜、3は塗布直後のスピンオンガラス
膜、4は5102化したスピンオンガラス膜である。An example of this planarization method will be described below with reference to schematic cross-sectional views of the semiconductor device shown in FIGS. 2(a) and 2(b)-(c). In the figure, 1 is a semiconductor device having unevenness or steps, 2
3 is a CvDS102 film, 3 is a spin-on glass film immediately after coating, and 4 is a 5102 spin-on glass film.
ます、第2図(a)に示すように1凹凸や段差を有する
半導体装111表面に層間絶縁膜に対応する5in2膜
2をCVD法によシ形成し、次いでスピンオンがラスを
スピン塗布法によシ塗布し凹凸や段差を塗布膜3で埋め
て表面を平坦化する。次に1第2図(b)に示すようK
、窒素雰囲気中で800′CI時間の熱処理によシスピ
ンオンガラス塗布M3を固化しS10□化した塗布膜4
にする。この時、スピンオンガラス塗布膜3の縮合反応
によシ膜厚が減少する。最後に1第2図(c)に示すよ
うに、 sto□化した塗布膜4のエツチング速度と
下地CVD 5in2膜2とのエツチング速度が等しい
エツチング条件の下で所望の厚さまで七nそれの膜を継
続してエツチング除去する。First, as shown in FIG. 2(a), a 5in2 film 2 corresponding to an interlayer insulating film is formed on the surface of the semiconductor device 111 having unevenness and steps by CVD method, and then a spin-on lath is applied by spin coating method. The coating film 3 is applied to fill in the unevenness and steps to flatten the surface. Next, as shown in Figure 2(b),
, Coating film 4 obtained by solidifying the cis pin-on glass coating M3 to S10□ by heat treatment for 800' CI time in a nitrogen atmosphere.
Make it. At this time, the thickness of the spin-on glass coating film 3 decreases due to a condensation reaction. Finally, as shown in FIG. 2(c), under etching conditions in which the etching rate of the coated film 4 and the underlying CVD 5in2 film 2 are equal, the film is etched to a desired thickness. Continue to remove by etching.
上記従来の平坦化方法の特徴は、スピンオンがラスがス
ピン塗布により半導体装置表面の凹凸や段差の平坦化が
可能であるような液状の材料である点と、また熱処理に
よってSlO□化することから不純物の汚染による悪影
響もなくS10□化したスピンオンガラスによる塗布膜
をそのま壜残すことも可能であるという点である。しか
し、一方ではスピンオンガラス塗布膜のSlO□化の反
応は基本的に下記に示すシラノールモノマーの縮合反応
によるものであり、体積の収縮率が大きくクラックが発
生しやすい欠点をもっている。The characteristics of the conventional planarization method described above are that spin-on lath is a liquid material that can flatten unevenness and steps on the surface of a semiconductor device by spin coating, and that it is converted into SlO□ by heat treatment. The advantage is that it is possible to leave the coated film of S10□ spin-on glass on the bottle without any adverse effects due to impurity contamination. However, on the other hand, the reaction of converting the spin-on glass coating film into SlO□ is basically due to the condensation reaction of silanol monomers as shown below, and has the disadvantage of a large volumetric shrinkage rate and a tendency to generate cracks.
また、上記のようにスピンオンがラスMはシラノールモ
ノマーが主成分であるため1回のスピン塗布で厚く塗布
することが困難である。例えば約1μmの段差を平坦化
するには、4回ないし5回程度重復してスピン塗布する
盛装がある。このように、上記従来の平坦化方法はクラ
ックが発生しやすいなど信頼性において問題があシかつ
工程数が多くなることから、LSIの製造方法としては
適した方法ではないと考えられていた。Further, as mentioned above, since the spin-on lath M is mainly composed of silanol monomer, it is difficult to apply it thickly in one spin coating. For example, in order to flatten a level difference of about 1 μm, there is a method of repeating spin coating about 4 to 5 times. As described above, the above-mentioned conventional planarization method has reliability problems such as easy occurrence of cracks, and requires a large number of steps, so it was considered not to be a suitable method for manufacturing LSIs.
本発明の目的は上記の問題点をM決した半導体装置表面
の平坦化方法を提供することにある。An object of the present invention is to provide a method for planarizing the surface of a semiconductor device that solves the above problems.
(問題点を解決するための手段)
本発明は凹凸や段差を有する半導体装置表面を平坦化す
る方法において、上記半導体装置表面に絶縁膜を堆積さ
せた後シロ中すン系−リマーを主成分とする樹脂を塗布
することによシ上記半導体装置表面を平坦化し、次いで
上記樹脂膜のエツチング速度と上記絶縁膜のエツチング
速度が等しいエツチング条件の下で上記樹脂膜と上記絶
縁膜とを継続してエツチング除去し、次いで残存した樹
脂膜を酸化することによ、p 5io2膜に変質させ、
凹凸や段差を有する上記半導体装lfN面に平坦化され
た絶縁膜を形成するものである。(Means for Solving the Problems) The present invention provides a method for planarizing the surface of a semiconductor device having unevenness or steps, in which an insulating film is deposited on the surface of the semiconductor device, and then a silicon-based remer as a main component is deposited on the surface of the semiconductor device. The surface of the semiconductor device is planarized by applying a resin, and then the resin film and the insulating film are etched continuously under etching conditions in which the etching rate of the resin film and the etching rate of the insulating film are equal. and then oxidize the remaining resin film to transform it into a p5io2 film,
A flattened insulating film is formed on the lfN surface of the semiconductor device having irregularities and steps.
本発明による平坦化方法の特徴は凹凸や段差を表面に有
する半導体表面を平坦化しさらに所望の厚さまでエツチ
ング除去するための塗布材料としてシロキサン系ポリマ
ーを主成分とする樹脂を用いた点と、その後残存した樹
脂膜を酸化することKよfi SIO□化した点である
。The flattening method according to the present invention is characterized by using a resin containing siloxane-based polymer as the main component as a coating material for flattening a semiconductor surface having unevenness or steps and etching it to a desired thickness; The point is that the remaining resin film is oxidized to become SIO□.
ここで、半導体装lit表面に堆積させる絶縁膜はCV
D法による5in2膜またFiSt、N4膜あるいはス
フ4ツタ法による5102膜また1jSi、N4膜いず
nの絶縁膜でありてもよい。Here, the insulating film deposited on the surface of the semiconductor device is CV
It may be a 5in2 film made by the D method, a FiSt, N4 film, a 5102 film made by the Sufu 4 Tsuta method, or an insulating film such as 1jSi, N4 film or nn.
また、上記樹脂膜の酸化による5i02化は、酸素雰囲
気中の熱処理または酸素グラズマ酸化またはオゾン雰囲
気中の熱処理いずnの方法でも達成される。Further, the oxidation of the resin film to 5i02 can be achieved by heat treatment in an oxygen atmosphere, oxygen glaze oxidation, or heat treatment in an ozone atmosphere.
(作用)
シロキサン系ポリマーは基本的に下記の(A)のような
2次元的ポリマーまた(B)のような3次元的ポリマー
を形成している。(Function) The siloxane polymer basically forms a two-dimensional polymer as shown in (A) below or a three-dimensional polymer as shown in (B) below.
(A) (B)
ここで、RFiH、OH、CH,、C2H5,フェニル
基等の置換基に対応している。このようなポリマー構造
はシラノールなどの七ツマ−に対して一回のスピン塗布
によシ厚<塗布することが可能である。(A) (B) Here, it corresponds to substituents such as RFiH, OH, CH,, C2H5, and phenyl group. Such a polymer structure can be coated to a thickness of less than 100 ml by one spin coating on a polymer such as silanol.
また、塗布後の熱処理による収縮率も置換基を選択する
ことによって低減させることができる。さらに、このよ
うなシロキサン系ポリマーは酸素雰囲気中での熱処理や
酸素プラズマ酸化やオゾン雰囲気中の熱処理によって酸
化しSiO2化させることが可能である。Further, the shrinkage rate due to heat treatment after coating can also be reduced by selecting substituents. Further, such a siloxane-based polymer can be oxidized and converted into SiO2 by heat treatment in an oxygen atmosphere, oxygen plasma oxidation, or heat treatment in an ozone atmosphere.
(実施例)
以下、第1図(a)Jb)=(c)の半導体装置の模式
的断面図により本発明による平坦化方法の実施例を説明
する。(Example) Hereinafter, an example of the planarization method according to the present invention will be described with reference to a schematic cross-sectional view of a semiconductor device shown in FIG. 1(a)Jb)=(c).
図中、lii凹凸や段差を有する半導体装置、2はCV
D5102膜、5はシロキサン系ポリマーを主成分とす
る樹脂膜、6tiSiO□化したシロキサン系ポリマー
を主成分とする樹脂膜である。まず、第1図(−に示す
ように、1μmの凹凸や段差を有する半導体装置1表面
に厚さ0.5 μm O5i02膜2 t−CVT)法
により形成し、次いで上記樹脂をスピン塗布法により2
.0μm塗布して樹脂膜5全形成し、窒素雰囲気中で2
00℃1時間熱処理する。ここで、樹脂としてFi置換
基にCH,基及びOH基を有し、かつ3次元的な構造を
もつシロキサン系ポリマー金用いている。このような樹
脂は一回のスピン塗布によシ厚く塗布することが可能で
あり、また縮合反応における収縮率も小さいのでクラッ
クが発生しにくいという特徴がある。次に1第1図(b
)に示すように、CF 及びH2がスによる反応性イオ
ン二ッチングにより半導体装置1の凸部上からCVD5
iO□膜2の厚さが0.3μmになるまで樹脂膜5のエ
ツチング速度とCVD SiO□a2のエツチング速度
が等しいエツチング条件の下でそれぞれのit継続して
エツチング除去する。この時のエツチング条件は、CF
4及びH2がス流量がそれぞれ100 aecm及び2
2IIccm、ガス圧力が80 Tf’L Torr、
高周波電力密度が0.18W/□2である。最後に、第
1図(c)に示すように、残存した樹脂膜5を酸素雰囲
気中で800℃1時間熱処理することによって酸化しs
10□化した崖布膜6に変質させた。In the figure, lii is a semiconductor device having unevenness and steps, 2 is a CV
D5102 film 5 is a resin film whose main component is a siloxane-based polymer, and a resin film whose main component is a siloxane-based polymer converted into 6tiSiO□. First, as shown in FIG. 1 (-), a 0.5 μm thick O5i02 film 2 was formed on the surface of the semiconductor device 1 having 1 μm unevenness and steps using the t-CVT method, and then the above resin was applied using the spin coating method. 2
.. The resin film 5 was completely formed by coating with a thickness of 0 μm, and the resin film 5 was coated for 2 hours in a nitrogen atmosphere.
Heat treatment at 00°C for 1 hour. Here, a siloxane-based polymer gold having a CH group and an OH group as Fi substituents and having a three-dimensional structure is used as the resin. Such a resin can be applied thickly by one spin coating, and also has a small shrinkage rate in a condensation reaction, so it is difficult to cause cracks. Next, Figure 1 (b
), CF and H2 are removed by CVD from above the convex portion of the semiconductor device 1 by reactive ion etching using gas.
Etching is continued until the iO□ film 2 has a thickness of 0.3 μm under etching conditions in which the etching rate of the resin film 5 and the etching rate of the CVD SiO□a2 are equal. The etching conditions at this time are CF
4 and H2 have a flow rate of 100 aecm and 2, respectively.
2IIccm, gas pressure is 80Tf'L Torr,
The high frequency power density is 0.18W/□2. Finally, as shown in FIG. 1(c), the remaining resin film 5 is oxidized by heat treatment at 800° C. for 1 hour in an oxygen atmosphere.
The material was transformed into a cliff cloth film 6 with a size of 10□.
上記実施例によればスピンオンガラス音用いた従来の平
坦化方法と同じ長所をもち、かつ−回のスピン塗布によ
シ厚<塗布できクラックの発生も低減できるので、従来
の平坦化方法の間ね点を解決した平坦化方法が得られた
。According to the above embodiment, it has the same advantages as the conventional planarization method using spin-on glass sound, and can apply a thickness less than 10 times by spin coating, and can reduce the occurrence of cracks. A flattening method that solved the problem was obtained.
尚、本実施例では塗布する樹脂としてCH,基とOH基
全全置換基する3次元的構造のシロキサン系ポリマー金
主成分とする樹脂を用いたが他のシロサン系ポリマーを
主成分とする樹脂でも可能である。また、半導体基板上
に堆積させる絶縁膜に配給縁膜の組み合わせを変えると
実施例で述べたエツチング条件では等エツチング速度が
得られない可能性があるが、それについてはエツチング
条件、例えは、エツチングガスの種類や流量等を選択す
ることによシ等エツチング速度になるようにFJtする
ことができる。In this example, a resin containing gold as a main component of a siloxane-based polymer with a three-dimensional structure in which CH and OH groups are fully substituted was used as the resin to be coated, but other resins containing siloxane-based polymer as a main component may also be used. But it is possible. In addition, if the combination of the distribution film and the insulating film deposited on the semiconductor substrate is changed, it is possible that the same etching speed cannot be obtained under the etching conditions described in the examples. By selecting the type of gas, flow rate, etc., it is possible to perform FJt to obtain a uniform etching speed.
以上のように、本発明によれば従来の半導体装e表面の
平坦化方法に比べてクラックの発生が低減し工程が簡単
であるなど極めて改善された半導体装置表面の平坦化方
法が得られる。As described above, according to the present invention, a method for planarizing the surface of a semiconductor device can be obtained which is significantly improved in that the generation of cracks is reduced and the process is simple compared to the conventional method for planarizing the surface of a semiconductor device.
したがって本発明によれば、信頼性が高く工程が簡単な
平坦化方法を提供でき、LSIの製造工程において平坦
化が必要な各種工程に広く利用できる効果を有する。Therefore, according to the present invention, it is possible to provide a planarization method that is highly reliable and has simple steps, and has the effect that it can be widely used in various processes that require planarization in the LSI manufacturing process.
第1図(a)、(b)、(e)は本発明による半導体装
置表面の平坦化方法の創造工程の一実施例を示した模式
的断面図、第2図(a)、(b)、(c)は従来の半導
体装置表面の平坦化方法の製造工程を示した模式的断面
図である。
1・・・凹凸や段差を有する半導体装置、2・・・CV
D510□膜、5・・・シロキサン系ポリマー金主成分
とする樹脂膜、6・・・5102化したシロキサン系ポ
リマーを主成分とする樹脂膜。FIGS. 1(a), (b), and (e) are schematic cross-sectional views showing one embodiment of the creation process of the method for planarizing the surface of a semiconductor device according to the present invention, and FIGS. 2(a), (b) , (c) are schematic cross-sectional views showing manufacturing steps of a conventional method for flattening the surface of a semiconductor device. 1... Semiconductor device having unevenness or steps, 2... CV
D510□ film, 5... Resin film containing siloxane-based polymer as main component of gold, 6... Resin film containing 5102 siloxane-based polymer as main component.
Claims (1)
おいて、上記半導体装置表面に絶縁膜を堆積させた後シ
ロキサン系ポリマーを主成分とする樹脂を塗布すること
により上記半導体装置表面を平坦化し、次いで上記樹脂
膜のエッチング速度と上記絶縁膜のエッチング速度とが
等しいエッチング条件の下で上記樹脂膜と上記絶縁膜と
を継続してエッチング除去し、残存した樹脂膜を酸化す
ることによりSiO_2膜に変質させ、凹凸や段差を有
する上記半導体装置表面に平坦化された絶縁膜を形成す
ることを特徴とする平坦化方法。In a method for planarizing a surface of a semiconductor device having unevenness or steps, the surface of the semiconductor device is planarized by depositing an insulating film on the surface of the semiconductor device, applying a resin containing a siloxane-based polymer as a main component, and then flattening the surface of the semiconductor device. Under etching conditions in which the etching rate of the resin film and the insulating film are equal, the resin film and the insulating film are continuously removed by etching, and the remaining resin film is oxidized to transform into a SiO_2 film. A planarization method comprising forming a planarized insulating film on the surface of the semiconductor device having unevenness or steps.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP20706585A JPS6265427A (en) | 1985-09-18 | 1985-09-18 | Flattening method |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP20706585A JPS6265427A (en) | 1985-09-18 | 1985-09-18 | Flattening method |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS6265427A true JPS6265427A (en) | 1987-03-24 |
Family
ID=16533620
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP20706585A Pending JPS6265427A (en) | 1985-09-18 | 1985-09-18 | Flattening method |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS6265427A (en) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS62183531A (en) * | 1986-02-07 | 1987-08-11 | Nippon Telegr & Teleph Corp <Ntt> | Formation of flattend film by etching |
JPH01181533A (en) * | 1988-01-12 | 1989-07-19 | Toshiba Corp | Manufacture of semiconductor device |
-
1985
- 1985-09-18 JP JP20706585A patent/JPS6265427A/en active Pending
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS62183531A (en) * | 1986-02-07 | 1987-08-11 | Nippon Telegr & Teleph Corp <Ntt> | Formation of flattend film by etching |
JPH01181533A (en) * | 1988-01-12 | 1989-07-19 | Toshiba Corp | Manufacture of semiconductor device |
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