JPS6251278U - - Google Patents

Info

Publication number
JPS6251278U
JPS6251278U JP14489885U JP14489885U JPS6251278U JP S6251278 U JPS6251278 U JP S6251278U JP 14489885 U JP14489885 U JP 14489885U JP 14489885 U JP14489885 U JP 14489885U JP S6251278 U JPS6251278 U JP S6251278U
Authority
JP
Japan
Prior art keywords
integrated circuit
semiconductor integrated
circuit package
board
stand
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP14489885U
Other languages
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP14489885U priority Critical patent/JPS6251278U/ja
Publication of JPS6251278U publication Critical patent/JPS6251278U/ja
Pending legal-status Critical Current

Links

Landscapes

  • Testing Of Individual Semiconductor Devices (AREA)
  • Testing Or Measuring Of Semiconductors Or The Like (AREA)

Description

【図面の簡単な説明】[Brief explanation of drawings]

第１図はこの考案による半導体集積回路試験用
及びバーンイン用ボードの一実施例の断面図、第
２図は第１図の実施例に使用するＩＣ固定台の拡
大斜視図、第３図は従来のフラツトパツケージ型
ＩＣ用ソケツトの一例の斜視図、第４図はこの考
案による半導体集積回路試験用及びバーンイン用
ボードの他の実施例の断面図である。 １……回路パターン、２……プリント配線板、
４……ＩＣ固定台、７……ＩＣパツケージ、９…
…陥凹部。 Fig. 1 is a sectional view of an embodiment of a board for semiconductor integrated circuit testing and burn-in according to this invention, Fig. 2 is an enlarged perspective view of an IC fixing stand used in the embodiment of Fig. 1, and Fig. 3 is a conventional one. FIG. 4 is a perspective view of an example of a flat package type IC socket, and FIG. 4 is a sectional view of another embodiment of the semiconductor integrated circuit test and burn-in board according to the invention. 1...Circuit pattern, 2...Printed wiring board,
4...IC fixing stand, 7...IC package cage, 9...
...concavity.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] プリント配線板上に半導体集積回路パツケージ
の下部に適合する陥凹部を形成した位置決め用の
ＩＣ固定台を固定し、これに半導体集積回路パツ
ケージを載置するようにしたことを特徴とする半
導体集積回路試験用及びバーンイン用ボード。 A semiconductor integrated circuit characterized in that an IC fixing stand for positioning, which has a recess formed in the lower part of the semiconductor integrated circuit package, is fixed on the printed wiring board, and the semiconductor integrated circuit package is placed on this stand. Test and burn-in board.
JP14489885U 1985-09-19 1985-09-19 Pending JPS6251278U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP14489885U JPS6251278U (en) 1985-09-19 1985-09-19

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP14489885U JPS6251278U (en) 1985-09-19 1985-09-19

Publications (1)

Publication Number Publication Date
JPS6251278U true JPS6251278U (en) 1987-03-30

Family

ID=31055932

Family Applications (1)

Application Number Title Priority Date Filing Date
JP14489885U Pending JPS6251278U (en) 1985-09-19 1985-09-19

Country Status (1)

Country Link
JP (1) JPS6251278U (en)

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5621781B2 (en) * 1973-04-13 1981-05-21
JPS5914074B2 (en) * 1976-08-04 1984-04-03 株式会社日立製作所 How to treat phosphors

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5621781B2 (en) * 1973-04-13 1981-05-21
JPS5914074B2 (en) * 1976-08-04 1984-04-03 株式会社日立製作所 How to treat phosphors

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