JPS6248073A - Semiconductor device - Google Patents

Abstract

PURPOSE:To extend a gate control range by partly forming the second conductivity type semiconductor region of high impurity region corresponding to the first conductivity type region on the other surface of a substrate, and spacing an interval between the bottom of the second conductivity type region and the first conductivity type drain semiconductor layer. CONSTITUTION:Since a P<+> type drain/collector region 70 is partly formed on the other surface of an N<+> type drain/collector layer 10 directly under N<+> type source/emitter region 4 and an N<+> type buffer layer 100 is formed on the bottom surface of the P<+> type drain/collector region 70, holes are partly implanted from the region 70 to a drain drift layer 6, and the implanting is suppressed by the layer 100. Thus, the DC current amplification factor hFE of a parasitic PNP transistor is decreased, voltage drops Vs of the P-type base region and P<+> type base central region 50 of the transistor reduce, thereby increasing a gate control range.

Description

[Detailed Description of the Invention] [Field of Application of Rakudo] The present invention relates to a semiconductor device, and particularly to a semiconductor device in which a high-power, high-speed, high-frequency switching element is monolithically realized.

[Prior Art] Several types of high-power, high-speed, high-frequency switching elements with low on-resistance have been used in the past, such as one shown in FIG. 3, for example.

FIG. 3 is a cross-sectional view showing the structure of a conventional conductivity modulated gold oxide semiconductor field effect transistor (hereinafter referred to as a CAT device) having a seven-dimensional structure. First this CA
The configuration of the T element will be explained. J5 in the diagram, CA
The structure of the T element is such that the n+ type drain substrate and the p+ type drain/collector layer of a metallurgical film semiconductor field effect transistor (hereinafter referred to as MO8FET) manufactured by conventional 2-1 expansion and modification are replaced. To explain in more detail, p
A train drift 111 made of, for example, an n-type epitaxial layer is formed on one surface of the +-type drain/collector 11.
6 is formed. A plurality of p-type base regions 5 are formed spaced apart from each other on the surface of the drain drift 116, and two n+ type source/emitter regions 4 are formed spaced apart from each other on the surface within the p-type base region 5. It is formed. Drain drift FIJ between p-type base regions 5
6 surface, the peripheral surface of p-type base region 5, and 0+
An oxide film 3 made of silicon dioxide, for example, is formed on a part of the surface of the shaped source/emitter region 4.

A metal gate electrode 2 is formed inside the oxide g13, and this gate electrode extends over the n' type source/emitter region 4. Further, a source/emitter electrode 1 is formed on the central surface of the p-type base region 5, another part of the surface of the n+ type source/emitter region 4, and the surface of the oxide film 3. Here, the 01 type source/emitter region 4, the p type base region 5, and the drain drift layer 6 are MOSFETs.
The p-type base region 5, the drain drift 116, and the p+ type drain/collector li7 constitute a pnp transistor parasitic to the MOSFET. A drain/collector electrode 8 is formed on the other surface of the p+ type drain collector layer 7.
ing. Furthermore, G is below the gate electrode 2, S/'E is a source/emitter electrode terminal, and D/C is a train/collector bridge terminal.

FIG. 4 is a diagram showing an equivalent circuit of the CAT element of FIG. 3. Considering the ideal current flow, the equivalent circuit of this CA Tm should be a series connection of a MOS FET and a p1n diode D2, but in reality it is ~IO8FET and this. It is a combination of an npn transistor parasitic to the thyristor and a thyristor made up of a pnp transistor.

Next, the operation of this CAT element will be explained.

When the gate electrode terminal G and the source/1 mitter electrode terminal S/E are short-circuited and a reverse bias voltage is applied between the drain 7' collector electrode terminal D/C and the source/emitter electrode terminal S/'E, the pin diode D2 becomes reverse biased and reverse bias blocking characteristics appear.

Also, drain/collector haze terminal D/C and source/'
When a forward bias voltage is applied between emitter electrode terminals S and E, diode D becomes reverse biased and forward bias blocking characteristics appear. In this state, if a voltage higher than the threshold voltage of the MOS FET is applied between the gate electrode terminal G and the source/emitter electrode terminal SZE, the p-type base l1
At the same time that a channel is formed in 15 and the MOS FET becomes operational, the pln diode D2 becomes p
io diode initial operation phenomenon occurs, holes are injected from the p+ type drain/collector layer 7 to the drain drift layer 6, and the conductivity of this drain drift layer increases, causing the CAT
The device turns on with low on-resistance. In addition, in order to turn off the CAT element, the gate electrode terminal G and the source/emitter electrode terminals S/E are shorted to reduce the voltage applied between these terminals to below the threshold voltage of the MOSFET. , the inverted region on the surface of the p-type base region 5 under the gate electrode 2 is returned to its original state, and a train drift layer 61 is formed.
Stop the supply of electrons at \. At the start of turn-off, a large amount of electrons injected up to that point are concentrated in the drain drift H6, but these electrons are injected into the p+ type drain/collector 11, and a corresponding current due to holes is generated in the p type drain/collector 11. It flows into the base region 5. If this state continues, the concentration of electrons in the train drift layer 6 will decrease, but in order for the CAT element to turn off, the remaining hole and electron plasma must cancel each other out through recombination.

The above is an explanation of the operation of a CAT device when the parasitic thyristor region of the MOSFET does not latch at turn-on, but the biggest problem with CAT devices is that the thyristor region causes a latching phenomenon at low current levels. If the thyristor region latches, it loses its ability to gate the CAT cable, making it difficult to turn it off. The reason for the latching phenomenon is that the npn transistor and pnp transistor in the thyristor region interact with each other in feedback action at high current density during turn-on. The condition for the silice region to latch at turn-on is the DC current amplification factor h of each of the npn transistor and pnp transistor.
The sum of rE is 〉1, and npn due to Holumi flow)
- This is the case when the voltage drop vS across the resistor R8 of the p-type base region 5 of the run lister becomes 0.4 to 0.8 V or more at 300°.

FIG. 5 is a cross-sectional view, not showing the structure, of Haku's CAT device, which has solved the above-mentioned problems to a certain level. In the figure, p" with high impurity concentration is located in the center of the p-type first region 5.
A shaped base central region 50 is formed, with a drain drift 116 and a p+ type drain/collector Ii? n between 7
+ type buffer WJ9 is inserted. Also, this CA
The equivalent circuit of the T element is the same as the circuit shown in FIG. p
J: is applied to the + type base central region 50 to lower the direct current amplification factor hFE of the parasitic npn transistor, and to suppress the injection of holes from the p + type drain/collector layer 7 to the drain drift layer 6 by the n + type buffer ff19, thereby reducing the parasitic pnp transistor.
By lowering the DC current amplification factor hrε of the T-run lister, the CAT element is prevented from latching at turn-on. That is, the latching current level is increased compared to the CAT element of FIG. 3.

[Problems to be solved by the invention] Conventional CAT used as a high-power, high-speed, high-frequency switching element! The current level at which the thyristor region parasitic to the lvl OS FET latches is low, and in order for the CAT element to operate normally, it must be used below the latching current level, and its gate control range is The problem was that it was narrow.

This invention was made to solve the above-mentioned problems, and an object of the present invention is to obtain a semiconductor device that can widen the gate control range by increasing the latching current level of the thyristor region parasitic to the MOSFET. .

Means for Solving Problem c] A semiconductor device according to the present invention includes a drain semiconductor substrate of a first conductivity type with a high impurity concentration, and a drain semiconductor of the first conductivity type with a low impurity concentration formed on one surface of the substrate. layer, and a first conductivity type source semiconductor w414 with a high impurity concentration formed on the surface of this first conductivity type drain semiconductor layer. and a gate region formed at a predetermined position on the surface of the first conductivity type drain semiconductor layer.
Corresponding to the jl region, a second +81 type semiconductor region with a high impurity concentration is partially formed, and the bottom of the second +81 type semiconductor region is spaced apart from the first rs type drain semiconductor region. It is lζ.

In this invention, a semiconductor region of a second conductivity type with a high impurity concentration is formed on the surface of a drain semiconductor substrate of a first conductivity type with a high impurity concentration of E4, corresponding to a source semiconductor region of a first conductivity type with a high impurity concentration. Since the bottom of the second conductivity type semiconductor region j is separated from the first conductivity type drain semiconductor layer, the first conductivity type drain semiconductor layer is separated from the 281st conductivity type cliff conductor region. The injection of carriers into M is suppressed.
Direct current of transistor parasitic to OSFET? H'a11
Width ratio b.

ε decreases. Moreover, since carriers are injected from the second conductivity type semiconductor region into the first conductivity type drain semiconductor layer in a dino-efficient manner, the conductivity of the first conductivity type drain semiconductor layer is modulated to the same degree as in the prior art.

[Example code] An embodiment of the present invention will be described below with reference to the drawings.

In addition, in the description of this embodiment, the description of parts that are redundant with the description of the conventional technology will be omitted.

FIG. 1 is a sectional view showing the structure of a monolithically constructed CAT element according to an embodiment of the present invention. The structure of this embodiment is the same as that of FIG. 3 except for the following points: a, that is, the drain/'collector voltage I! An n1 type drain/collector &t10 is formed on the surface of ii8 instead of the p4 type drain/'collector layer 7, and a train drift layer 6 is formed on the -h:S plane of this n+ drain/collector layer. Further, a p+ type drain/collector region 70 is partially formed on the other surface of the n+ type drain/collector N10 immediately below each 111 type source/emitter region 4, and the bottom of this p4 type drain/collector region is a drain/collector region 70. It is spaced apart from the surface of the drift 86, and this space forms an n+ type buffer layer 100.

Also, as in FIG. 5, p +
Shape base center tin b/i 50 is formed.

0+ type source/emitter region 4 p-type base region 5.1
)+form l\-s central region 50drain drift @6.
The n+ type drain/collector [10] constitutes an npn transistor parasitic to the MOSFET, and the p type base region [5
, p+ type base central region 50 and drain drift 116
．． The 1+ type drain, 73199 layer 10 and the p+ type drain/collector region 70 constitute a pnρ transistor parasitic to the MOS FET, and both transistors form a parasitic thyristor region 4! I'm ff1L.

2M is a diagram showing an equivalent circuit of the CATA child of FIG. 1. In the figure, the equivalent circuit of this CAIA device is an n-channel M with a parasitic pin diode 02 between the gate terminal G and the drain/collector electrode terminal D/'C.
It is OS FET.

Next, the operation of this CAT element will be explained.

A p+ type drain/collector region 70 is partially formed on the other surface of the n+ type drain/collector l1iiIO directly below each n+ type source/emitter region 4, and on the bottom surface of this p+ type drain/collector 1M. Since the n+ type buffer layer 100 is formed, p" type train/collector #4b170<p+ of Onp transistor.
When holes are partially injected from the emitter into the drain drift layer 6, this injection
This can be suppressed by 00. Therefore, the parasitic pnp Ir−
The transport efficiency of the base region of the runlister is reduced, and its DC current amplification factor hyε is significantly reduced compared to the conventional CATA element. In addition, the holes in the p+ type drain/collector region 70 flow straight upward with the train drift F#6 being narrowed, and most of the holes are in the periphery of the p+ type base region 5, and some of them are in the p+ type base region 5. Shape base middle center [
50 and exits to the 01 type source/emitter region 4.

Therefore, the voltage drop (2) at Rs in the base region due to the Hall current is smaller than in the conventional CATA element. In this way, in this CΔ clove, the DC current amplification factor hrE of the strange ρnp transistor decreases, and the strange
Since the voltage drop V in the ρ-type base region and the p-type base central region 50 of the pn transistor becomes smaller, the conventional C
At the current level that causes latching in the ATA terminal, the parasitic thyristor region does not latch.

That is, the latching current level is increased compared to the conventional CATA element. Therefore, turn-off of the CATA element becomes easy and high-speed high-frequency switching characteristics are improved. In addition, in this CATA device, the latching current level increases as described above, so compared to the conventional CAT
The gate control range is wider than that of A, and C
It becomes possible to increase the current density of the AT element, and by reducing the chip size, it is possible to reduce the size and cost of the CA block. Furthermore, it is effective to generate conductivity modulation of the drain drift 6 directly under the n+ type source/emitter region 4, and conductivity modulation directly under the p+ type base central region 50 is unnecessary. be. For this reason, p
The +-type drain/collector region 70 is partially formed only directly under the n+-type source/emitter region 4 to efficiently inject holes from the p+-type train collector region 70 into the drain drift layer 6. As a result, it is possible to obtain a transmission fourth degree modulation effect equivalent to that of a conventional CATA element, and it is possible to lower the on-state voltage. Also,
In the conventional CATl element, the p+ type drain/collector layer 7 is formed over the entire region of the drain drift layer 6. Therefore, during turn-off, N holes accumulated in the drain drift H6 during turn-on are transferred to the p+ type drain/collector layer 7. It was difficult to escape because it was blocked by
In this CATA child, holes are blocked only in a narrow range at the bottom of the p+ type drain/collector region 70,
The surrounding n+ type drain/'collector layer 10 can be easily handled, which also facilitates the turn-off operation of the CATA element and improves high-speed high-frequency switching characteristics.

In the above embodiment, the CATA element is p-type, but it goes without saying that the present invention can also be applied to a p-type CATA element in which the conductivity types of each layer and each region in FIG. 1 are reversed.

[Effects of the Invention] As described above, according to the present invention, a first conductivity type drain semiconductor substrate with a high impurity concentration, a first conductivity type drain semiconductor layer with a low impurity concentration formed on one surface of this substrate, An MO8 type electric field that moves between a highly impurity-concentrated first conductivity type source semiconductor fr4 region formed on the surface of the first conductivity type drain semiconductor layer and a gate region formed at a predetermined position on the first conductivity type drain semiconductor layer surface. In the effect transistor, a second conductivity type semiconductor region having a high impurity concentration is partially formed on the other surface of the substrate corresponding to the first conductivity type source semiconductor region A, and a bottom part of the second conductivity type semiconductor region is formed as a second conductivity type semiconductor region. Since the 1 conductivity type drain semiconductor layer is separated from the MOS
It is possible to obtain a semiconductor device in which the gate control range can be expanded by increasing the level of current latching in the thyristor region parasitic to the FET.

[Brief explanation of the drawing]

FIG. 1 is a sectional view showing the structure of a monolithically constructed CAT element which is a practical example of the present invention. FIG. 2 is a diagram showing an equivalent circuit of the CAT element shown in FIG. 1. FIG. 3 is a sectional view taken along the line '8j' and shows the structure of a conventional CAT element having a seven-dimensional structure. FIG. 4 is a diagram showing an equivalent circuit of a conventional CAT element. Figure 5 shows another conventional monolithically configured CAT
FIG. 3 is a cross-sectional view showing the structure of the element. In the figure, 1 is a source/emitter electrode, 2 is a gate electrode, 3 is an oxide film, 4 is an n+ type source/'emitter region,
5 is a p-type base region, 50 is a p + type base central region, 6
70 is a p+ type drain/collector region 8 is a drain/collector electrode, 10 is an n4 type drain/collector layer, and 100 is an n+ type buffer layer. Note that the same reference numerals in each figure indicate the same or corresponding parts. Agent Masuo Oiwa 1st session 2 Figure 3 Figure 4 (¥1 Figure 5 Procedure corrector (spontaneous) 20 Name of the invention Semiconductor device 3, Person making the amendment 5, Specification subject to amendment Column 6 of Detailed Description of the Invention, Contents of Amendment (1) Operation of rcAT element on page 4, line 12 of Memorandum M”
is corrected to the characteristics and operation J of the rcAT element. (2) "Mostly" on page 12, lines 13 to 14 of the specification is corrected to "partly." (3) "Partly" on page 12, line 14 of the specification is corrected to "mostly." (4) “n” on page 12, line 13 to line 16 of the specification
"+-type source 7/emitter region 4" is corrected to "source,/emitter electrode 1". that's all

Claims (1)

[Scope of Claims] A first conductivity type semiconductor substrate having a high impurity concentration and serving as a drain layer; a first conductivity type semiconductor layer having a low impurity concentration formed on one surface of the substrate and serving as a drain layer; A MOS field effect transistor comprising: a first conductivity type semiconductor region formed on a surface of a conductivity type semiconductor layer and having a high impurity concentration and serving as a source region; and a gate region formed at a predetermined position on the surface of the first conductivity type semiconductor layer. A second conductivity type semiconductor region having a high impurity concentration is partially formed on the other surface of the substrate corresponding to the first conductivity type semiconductor region, and a bottom portion of the second conductivity type semiconductor region is formed in the first conductivity type semiconductor region. 1. A semiconductor device characterized in that the shaped semiconductor layer is spaced apart from the semiconductor layer.