JPS62247522A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPS62247522A
JPS62247522A JP9028286A JP9028286A JPS62247522A JP S62247522 A JPS62247522 A JP S62247522A JP 9028286 A JP9028286 A JP 9028286A JP 9028286 A JP9028286 A JP 9028286A JP S62247522 A JPS62247522 A JP S62247522A
Authority
JP
Japan
Prior art keywords
resist film
film
pattern
aluminum alloy
sog
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP9028286A
Other languages
Japanese (ja)
Inventor
Eiichi Kawamura
栄一 河村
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP9028286A priority Critical patent/JPS62247522A/en
Publication of JPS62247522A publication Critical patent/JPS62247522A/en
Pending legal-status Critical Current

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  • Drying Of Semiconductors (AREA)
  • Exposure Of Semiconductors, Excluding Electron Or Ion Beam Exposure (AREA)

Abstract

PURPOSE:To construct a resist film capable of high-precision patterning by a method wherein an organic silicon resin film attached as an intermediate layer is subjected to an oxygen-plasma treatment. CONSTITUTION:An aluminum alloy film 13 is attached to a semiconductor substrate 11 that includes a step, a flattening resist film 14 (thickness: 1-3mum) is applied to the aluminum alloy film 13, and an SOG film 15 (thickness: several thousand Angstrom ) is formed by application on the resist film 14. The SOG film 15 is exposed to oxygen plasma for the solidification of its surface, whereon a resist film 16 (thickness: 1mum) is provided by application, to be exposed and then developed for the formation of a pattern. Next, with the resist film 16 serving as a mask, etching is accomplished by using a fluorine-based gas for the patterning of the SOG film 15. The SOG film 15 serves as a mask in a process wherein the resist film 14 is exposed to an oxygen gas reactive ion etching treatment for the transfer of the pattern. The patterned resist film then serves as a mask in a process of patterning the aluminum alloy 13 that is accomplished by using a chlorine-based gas as an etching gas.

Description

【発明の詳細な説明】 [概要] 多層レジスト膜パターンの中間層とした有機シリコン樹
脂膜を、酸素プラズマ処理して、その上にレジスト膜パ
ターンを形成する。そうすると、加熱してキュアさせる
必要がなく、加熱による他材料の変質が防止される。
DETAILED DESCRIPTION OF THE INVENTION [Summary] An organic silicon resin film serving as an intermediate layer of a multilayer resist film pattern is treated with oxygen plasma to form a resist film pattern thereon. In this case, there is no need to heat and cure the material, and deterioration of other materials due to heating is prevented.

[産業上の利用分野] 本発明は半導体装置の製造方法に係り、特に、多層レジ
スト膜パターンの形成方法に関する。
[Industrial Field of Application] The present invention relates to a method for manufacturing a semiconductor device, and particularly to a method for forming a multilayer resist film pattern.

ICなど、半導体装置の製造方法において、重要なプロ
セスにリソグラフィ技術があり、ICの高微細化・高集
積化の背景にはりソグラフィ技術の進歩が大きく貢献し
ている。
Lithography technology is an important process in the manufacturing method of semiconductor devices such as ICs, and progress in lithography technology has greatly contributed to the miniaturization and high integration of ICs.

しかし、リソグラフィ技術を用いたパターン形成には、
容易にエツチングできて、高精度にパターンニングでき
ることが望まれている。
However, pattern formation using lithography technology requires
It is desired that the material can be easily etched and patterned with high precision.

[従来の技術と発明が解決しようとする問題点]さて、
従来、段差部にレジスト膜パターンを形成すると、凹部
と凸部とではレジスト膜の膜厚が異なり、これを露光・
現像すれば凹部と凸部とのパターン幅が違ってくる等、
高精度にパターンニングできない問題があった。即ち、
両方を同時に露光すると、凹部上の膜厚の厚いレジスト
膜部分は露光不足になって、現像すればレジスト膜パタ
ーンの幅が狭くなり、凸部上の膜厚の薄いレジスト膜部
分は露光過度になって、現像すればレジスト膜パターン
の幅が広くなる。第2図(a)および(b)はそれを示
す平面図と断面図で、段差のある半導体基板1上に形成
したネガレジスト膜パターン2を例示している。
[Problems to be solved by conventional technology and invention] Now,
Conventionally, when a resist film pattern is formed on a stepped part, the thickness of the resist film differs between the concave part and the convex part.
If you develop it, the pattern width of the concave and convex parts will be different, etc.
There was a problem that it was not possible to pattern with high precision. That is,
If both are exposed at the same time, the thicker resist film parts on the concave parts will be underexposed, and when developed, the width of the resist film pattern will become narrower, and the thinner resist film parts on the convex parts will be overexposed. Therefore, when developed, the width of the resist film pattern becomes wider. FIGS. 2(a) and 2(b) are a plan view and a cross-sectional view illustrating a negative resist film pattern 2 formed on a semiconductor substrate 1 having steps.

詳しくは、露光波長とレジスト膜厚とが関連して、パタ
ーン幅は一定しないが、概念的には上記に説明したよう
に、レジスト膜パターンの幅がその膜厚に比例して変わ
るものである。
Specifically, the pattern width is not constant due to the relationship between the exposure wavelength and the resist film thickness, but conceptually, as explained above, the width of the resist film pattern changes in proportion to its film thickness. .

従って、段差のある部分には、例えば、3層のレジスト
膜パターンを形成するパターンニング方法が考案された
。第3図は段差のある半導体基板1上にアルミニウム合
金膜3を被着し、その上に3層レジスト膜4.5.6の
パターンを形成した工程断面を示している。即ち、段差
ある半導体基板1上のアルミニウム合金膜3をパターン
ニングするため、その直上に、平坦化するためのレジス
ト膜4を平坦になるまで厚(塗布し、更に、その上にレ
ジスト膜5を被着している。そのレジスト膜5は、レジ
スト膜4とはエツチング比が大きく異なる材質の膜、例
えば、有機シリコン樹脂(スピンオングラス:5OG)
膜を被着する。次いで、最上層のレジスト膜6は微細パ
ターンの形成できる高感度・高解像度のレジストを塗布
する。
Therefore, a patterning method has been devised in which, for example, a three-layer resist film pattern is formed on the stepped portion. FIG. 3 shows a cross section of a step in which an aluminum alloy film 3 is deposited on a semiconductor substrate 1 having a step, and a pattern of three-layer resist films 4, 5, and 6 is formed thereon. That is, in order to pattern the aluminum alloy film 3 on the semiconductor substrate 1 with steps, a resist film 4 for planarization is coated on the aluminum alloy film 3 until it becomes flat. The resist film 5 is made of a material whose etching ratio is significantly different from that of the resist film 4, for example, an organic silicon resin (spin-on glass: 5OG).
Deposit the membrane. Next, the uppermost resist film 6 is coated with a high-sensitivity, high-resolution resist capable of forming fine patterns.

そして、まず、レジスト膜6のパターンを形成した後、
そのレジスト膜6のパターンをマスクにして、SOG膜
をエツチングし、更に、SOG膜をマスクにしてレジス
ト膜4をエツチングしてパターンを転写する。SOG膜
は弗素系ガスでエツチングされ、そのSOG膜をマスク
としてレジスト膜4は酸素ガスでエツチングされてパタ
ーンが転写されるが、下層のレジスト膜4がパターンニ
ングされると、最上層のレジスト膜6は殆ど消滅してな
くなることが多い。
Then, first, after forming a pattern of the resist film 6,
Using the pattern of the resist film 6 as a mask, the SOG film is etched, and further, the resist film 4 is etched using the SOG film as a mask to transfer the pattern. The SOG film is etched with fluorine-based gas, and using the SOG film as a mask, the resist film 4 is etched with oxygen gas to transfer the pattern. When the lower resist film 4 is patterned, the uppermost resist film 6 often disappears.

このように、多層レジスト膜パターンを形成する場合に
は、エツチング比の異なる材質のものを介在させており
、その中間層として有機シリコン樹脂が用いられている
In this manner, when forming a multilayer resist film pattern, materials having different etching ratios are interposed, and an organic silicone resin is used as the intermediate layer.

ところが、このようなSOG膜を中間層に用いる場合、
SOG膜を被着(塗布)した後、200〜300℃で加
熱処理してキュア(固化)させているが、この加熱処理
をおこなうと、他の材料、例えば、アルミニウム合金膜
が変質してエツチングされ難くなり、高精度にパターン
ニングできないと云う問題がある。
However, when using such an SOG film as an intermediate layer,
After the SOG film is deposited (coated), it is cured (solidified) by heat treatment at 200 to 300°C, but when this heat treatment is performed, other materials, such as aluminum alloy films, are altered and etched. There is a problem that patterning becomes difficult and highly accurate patterning cannot be performed.

本発明は、このような問題点を解消させて、高精度にパ
ターンニングできるレジスト膜パターンの形成方法を提
案するものである。
The present invention solves these problems and proposes a method for forming a resist film pattern that enables highly accurate patterning.

[問題点を解決するための手段] その目的は、中間層として被着した有機シリコン樹脂膜
を、酸素プラズマ処理する工程が含まれる半導体装置の
製造方法によって達成される。
[Means for Solving the Problems] The object is achieved by a method for manufacturing a semiconductor device that includes a step of treating an organic silicon resin film deposited as an intermediate layer with oxygen plasma.

[作用コ 即ち、本発明は、中間層とした有殻シリコン樹脂膜を、
酸素プラズマ処理して、その上にレジスト膜パターンを
形成する。そうすると、加熱処理することなく、上層の
レジスト膜パターンが形成できて、加熱による他材料の
変質が防止される。
[Operation: In other words, the present invention uses a shelled silicone resin film as an intermediate layer,
Oxygen plasma treatment is performed to form a resist film pattern thereon. In this way, the upper resist film pattern can be formed without heat treatment, and other materials are prevented from deteriorating in quality due to heating.

[実施例] 以下、図面を参照して実施例によって詳細に説明する。[Example] Hereinafter, embodiments will be described in detail with reference to the drawings.

第1図(al〜(d)は本発明にかかる3層レジスト膜
パターンによる形成方法の工程順断面図を示している。
FIGS. 1A to 1D show step-by-step cross-sectional views of a method for forming a three-layer resist film pattern according to the present invention.

まず、同図(alに示すように、段差のある半4体基板
11上にアルミニウム合金膜13を被着し、その上に平
坦化用のレジスト膜14(膜厚」〜3μm)を塗布して
、更に、その上にSOG膜15(膜厚数千人程度)を塗
布する。そして、このSOG膜14を酸素プラズマに曝
して、その表面を固化させる。このような酸素プラズマ
処理すると、その上にレジスト膜16を塗布しても、レ
ジスト膜16に含まれた溶剤で、SOG膜15が溶解さ
れることはなくなる。
First, as shown in the same figure (al), an aluminum alloy film 13 is deposited on a semi-quad substrate 11 with steps, and a flattening resist film 14 (film thickness of ~3 μm) is applied thereon. Then, an SOG film 15 (with a film thickness of about several thousand layers) is applied thereon.Then, this SOG film 14 is exposed to oxygen plasma to solidify its surface. Even if the resist film 16 is applied thereon, the SOG film 15 will not be dissolved by the solvent contained in the resist film 16.

従って、第1図(′b)に示すように、その上に微細バ
クーン形成用のレジスト膜16(膜厚1μm)を塗布し
、露光、現像して、パターンを形成する。
Therefore, as shown in FIG. 1('b), a resist film 16 (thickness: 1 μm) for forming fine bubbles is applied thereon, exposed and developed to form a pattern.

次いで、同図(C)に示すように、レジスト膜16をマ
スクにして、SOG膜15を弗素系ガスでエツチングし
てパターンニングし、そのSOG膜15をマスクにして
レジスト膜14を酸素ガスでリアクティブイオンエツチ
ングしてパターンを転写する。この時、レジスト膜16
はエツチングで消滅してしまうことが多い。
Next, as shown in FIG. 2C, using the resist film 16 as a mask, the SOG film 15 is etched and patterned with fluorine gas, and using the SOG film 15 as a mask, the resist film 14 is etched with oxygen gas. Transfer the pattern using reactive ion etching. At this time, the resist film 16
are often eliminated by etching.

次いで、第1図(dlに示すように、そのレジスト膜パ
ターンをマスクにして、アルミニウム合金膜を塩素系ガ
スでエツチングしてパターンニングする。そうすれば、
アルミニウム合金膜は熱処理されていないために、容易
にエツチングされて高精度なアルミニウム合金膜パター
ンが得られる。
Next, as shown in FIG. 1 (dl), using the resist film pattern as a mask, the aluminum alloy film is patterned by etching with chlorine gas.
Since the aluminum alloy film is not heat-treated, it can be easily etched to obtain a highly accurate aluminum alloy film pattern.

従って、このような多層レジスト膜パターンの形成方法
によれば、エツチングが容易になって、高精度にパター
ンニングすることができる。
Therefore, according to this method of forming a multilayer resist film pattern, etching becomes easy and patterning can be performed with high precision.

上記はアルミニウム合金膜を例として説明したが、熱処
理で変質し易い他の材料膜にも適用できることは云うま
でもない。
Although the above description has been made using an aluminum alloy film as an example, it goes without saying that the present invention can also be applied to films made of other materials that are easily altered by heat treatment.

[発明の効果] 以上の説明から明らかなように、本発明によれば多層レ
ジスト膜パターンを用いて、高精度にパターンを形成で
きる利点がある。
[Effects of the Invention] As is clear from the above description, the present invention has the advantage of being able to form a pattern with high precision using a multilayer resist film pattern.

【図面の簡単な説明】[Brief explanation of drawings]

第1図(al〜(d)は本発明にかかる形成方法の形成
工程順断面図、 第2図(a)、 (b)は従来の1層のレジスト膜パタ
ーン形成の平面図と断面図、 第3図は従来の3層のレジスト膜パターン形成の断面図
である。 図において、 1.11は半導体基板、 2.4,5.6はレジスト膜、 3.13はアルミニウム合金膜、 14、16はレジスト膜、 ジはSOG膜、 を示している。 44B月1−g・ひ)セf(太りとり形へ′1孝デ悶第
1閃 犯+、−■、/’l、2+ Lし゛・又ト膜へ・7−ン
めtす叉1コ第2図 05十の 3)tシレミ−Zl−iそバ7−ンの形賎図
第3図
FIGS. 1(al to d) are cross-sectional views in the order of formation steps of the forming method according to the present invention; FIGS. 2(a) and (b) are plan views and cross-sectional views of conventional single-layer resist film pattern formation; Fig. 3 is a cross-sectional view of conventional three-layer resist film pattern formation. In the figure, 1.11 is a semiconductor substrate, 2.4, 5.6 are resist films, 3.13 is an aluminum alloy film, 14, 16 indicates the resist film, ji indicates the SOG film, Figure 2 050-3) Figure 3 Shape of the 7-ring to the membrane

Claims (1)

【特許請求の範囲】[Claims] 多層レジスト膜パターンの形成方法において、中間層と
して有機シリコン樹脂膜を被着し、該有機シリコン樹脂
膜を酸素プラズマ処理する工程が含まれてなることを特
徴とする半導体装置の製造方法。
1. A method for manufacturing a semiconductor device, comprising a step of depositing an organic silicone resin film as an intermediate layer and treating the organic silicone resin film with oxygen plasma in the method of forming a multilayer resist film pattern.
JP9028286A 1986-04-18 1986-04-18 Manufacture of semiconductor device Pending JPS62247522A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP9028286A JPS62247522A (en) 1986-04-18 1986-04-18 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP9028286A JPS62247522A (en) 1986-04-18 1986-04-18 Manufacture of semiconductor device

Publications (1)

Publication Number Publication Date
JPS62247522A true JPS62247522A (en) 1987-10-28

Family

ID=13994159

Family Applications (1)

Application Number Title Priority Date Filing Date
JP9028286A Pending JPS62247522A (en) 1986-04-18 1986-04-18 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPS62247522A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5023204A (en) * 1988-01-21 1991-06-11 Mitsubishi Denki Kabushiki Kaisha Method of manufacturing semiconductor device using silicone protective layer
US7488429B2 (en) 2004-06-28 2009-02-10 Tdk Corporation Method of dry etching, method of manufacturing magnetic recording medium, and magnetic recording medium

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5023204A (en) * 1988-01-21 1991-06-11 Mitsubishi Denki Kabushiki Kaisha Method of manufacturing semiconductor device using silicone protective layer
US7488429B2 (en) 2004-06-28 2009-02-10 Tdk Corporation Method of dry etching, method of manufacturing magnetic recording medium, and magnetic recording medium

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