JPS62213173A - Semiconductor device and manufacture thereof - Google Patents

Abstract

PURPOSE:To form a distance between a source and a gate with excellent controllability in 0.15mum or less by shaping a source or drain electrode and a gate electrode in a self-alignment manner. CONSTITUTION:A P<-> layer 11, an N<-> type undoped layer 12, an N-type layer 13 containing Si and an undoped N<-> type layer 18 are grown on a semi- insulating GaAs substrate 100 in succession through MBE, an undoped N<-> type layer 19 and an N<+> Ge layer 2 containing As are grown, and an Al layer 10 is formed. An element between transistors is isolated, SiO2 20 is shaped, photoresist 40 processing is conducted, SiO2 20 is removed through dry etching, using the photoresist 40 as a mask, and a taper is formed through wet etching. The source electrode 10 and the N<-> Ge layer 2 are removed selectively through dry etching, and SiN 21, 22 are applied through a photo-CVD method. SiN 22, 41 are removed, leaving the side wall 21 through an anisotropic dry etching method, and Al is deposited as a gate metal 30, thus forming an enhancement type FET through lift-off.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to improving the performance of field-effect transistors in a broad sense, and particularly relates to a semiconductor device suitable for forming source-drain electrodes and gate electrodes and a method for manufacturing the same. It is related to.

[Conventional technology]

In recent years, MBE (molecular beam epitaxy) technology.

With the development of ultra-high-precision crystal growth techniques such as MOCVD (metal-organic pyrolysis), ultra-high-speed devices using gallium arsenide (GaAs)/aluminum gallium arsenide (AQ GaAs) (for example, 55-1320
74) is being realized. GaAs/ML
Since good insulating materials have not been found for GaAs, Schottky junctions between metals and compound semiconductors are used in gate structures of various field effect transistors (FETs).

For example, FIG. 8 shows a cross-sectional view of a selectively doped heterojunction FET. In the figure, 100 is a semi-insulating GaAs substrate;
11 is undoped GaAs, and 12 is an undoped spacer called a spacer (no impurity is intentionally included, resulting in 10"
(Often a single layer of n of the order of am-”) AllGaA
If the thickness of the s layer is e, the number of participants is usually about 60. 13
is an n-type All Ga As layer, and 14 is an n-type GaA layer.
It is the s layer. Letting d be the total thickness of the All Ga As layers 12 and 13, d is usually about 500. Further, 31 is an enhancement type FET (threshold voltage vt
h~0. IV), and 30 is the gate metal of a depletion type FET (threshold voltage Vth ~ 0.8 V +, channel is open at gate voltage Vo = OV).

From a simple calculation, if the doping level of the n-type AaGaAs layer is NO, the main term can be written as the threshold voltage Vth. Here, φan is the Schottky barrier height between the gate metal and AfL Ga As, and ΔEc is Ga As 11 and Alla
It represents the magnitude of the discontinuity of the conduction band edge with the As layer 2, q is the unit charge, and ε is the dielectric constant of All Ga As. When improving the performance of such a FET, the parasitic resistance R1 in the gap between the source 32.34 and the gate 30.31
The biggest challenge is to reduce this. The above parasitic resistance Rs
s is generally written as. However. is the source-gate distance, W is the transistor width, and γ. is the contact resistance of the source electrode,
ρ5 is the carrier sheet resistance between the source and gate. The minimum L* that can normally be formed using photolithography or electron beam lithography is at the level of 0.5 to 0.8 μm. Sheet resistance ρ is 1 to Ω/ro to 100Ω/
It is about B. A characteristic feature of FETs using compound semiconductors is that the sheet resistance ρ9 is extremely large (approximately 1 to 5 Ω/port for Si-MOSFETs). This is mainly due to the fact that the upper limit of carrier density in compound semiconductors is as low as 2
) High frequency GaAsM E S F E T (For example, IEE, E D27 (198G
), p. 1029) are shown in FIGS. 9(a) and 9(b).
), in FIG. 9(a), 9 is n-type Ga A
s active layer, 15 is n+(~2XIO"am-")G
The gate electrode 30 is formed of an aAs layer by etching the material by about 3,000 to 4,000 steps. 32.
Reference numerals 33 indicate source and drain electrodes, respectively. In this case as well, although the n+ layer is formed to be thick, the sheet resistance ρ1 between the source and the gate is about 100Ω/gate, respectively. This situation also applies to the structure shown in FIG. 9(b) in which the n + semiconductor layer 15 and the gate metal 30 are separated by the side walls of the insulating film.

On the other hand, the contact resistance γ of the electrode. is about 0.2Ω, and the doping level of the n"GaAs layer where the source and drain electrode metals are in contact is 2X10"C! l-' gave a lower limit. In this way, ρ8 is reduced to several 07 units or less, or γ. If it is set to 0.02ΩI or less, a dramatic improvement in performance can be expected.

[Problem that the invention seeks to solve]

In the above conventional technology, the distance between the source and gate is small.

The main reason for the large parasitic resistance is that the sheet resistance of the semiconductor that forms the gap between the source and gate is about 100Ω/hole, with the source and gate separated by more than 0.5μ. An object of the present invention is to form a source (or drain) electrode and a gate electrode in a self-aligned manner so that the distance between the source and the gate is L8. 0.15μ■ or less with good controllability, and the semiconductor with which the source electrode is in direct contact is 10"am-'
The purpose is to reduce the electrode contact resistance γC to 0.02Ω or less by forming the electrode at a high concentration.

[Means for solving problems]

The cross-sectional structure of a field-effect transistor in a broad sense according to the present invention is shown in FIGS. 2 x 10"as-"
A semiconductor layer 2 (up to about 10" am-3) is formed, and a source/drain metal 10 is further formed. At this time, a gate electrode is formed using a lift-off process in a self-aligned manner with respect to the source/drain metal. The above object can be achieved by forming the metal 30. That is, the lift-off insulator 201 is made of, for example, CVD Sin,
After forming the photoresist 40 on the entire surface, a photoresist 40 is applied to form the gate electrode, and then the insulator 20 and source/drain metal 1 are etched using dry etching or chemical etching.
0. High concentration semiconductor layer 2 is selectively removed to expose semiconductor layer 1 with which the gate metal contacts. Next, the insulators 21 and 2 are processed using a low-temperature process such as photo-CVD (which does not have to cause large deformation or other effects on the photoresist 40).
Apply 2. In this case, the key point is to form the insulators 21 and 22 on the side walls of the recess space 40 where the gate metal is formed. Next, using methods such as dry etching,
Insulator 21 at the bottom 41 of the gate recess. After removing the insulator 42 on the photoresist and removing etching residue, a gate metal 30 was deposited on the entire surface and lifted off. At this time, the spacer for lift-off is photoresist 4
0 and a spacer insulating film 20. That is, one feature of the present invention is that after sidewall insulating films 21 and 22 are formed on the source and drain metals 10 and gate photoresist 40 by a low-temperature process, the gate metal is deposited by etching while leaving the sidewalls 21, and then the gate metal is deposited by lift-off. The purpose is to form a gate.

The source (drain) metal 10 and gate metal 30 are separated by one gate photoresist process.

In addition to using the low-temperature insulating film formation method, other manufacturing methods are also possible. The final finished shape is as shown in Figure 7(b),
It is important that the source (drain) metal 10 and the gate metal 30 are separated via the sidewall insulating film 21.

It can be said that the structure in which the distance between the source and gate is reduced to the limit as described above is essentially different from the conventional structure (FIGS. 8 and 9). In the conventional method, the distance between the source and gate is small. in a self-consistent manner.

Alternatively, even if it is formed by mask alignment, the lower limit is L8 at the 0.5 μm level. The structure described above has become possible because a low-temperature insulator formation method that allows formation of good coverage at about room temperature has become possible.

[Operation] As described above, the source is formed by forming a self-aligned sidewall insulator.
By forming the gate electrode, the distance L0 between the source 10 and the gate 30 can be made 0.15 μm or less, and the source electrode metal 10
is connected to the high concentration layer 2, so the contact resistance γ. 0.
It is now possible to reduce the resistance to 02Ω1 or less.

Furthermore, since the sidewall insulator 21 exists to separate the source metal 10 and the gate metal 30, as shown in FIG.
After removing the photoresist 40 in this state, the insulator 21 may be removed. In this case, it is necessary to form a passivation film after that.

Extremely low deposition speed of photoCVD (~30 people/n
+in), it is possible to control Ls with very good controllability.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

FIGS. 1(a) to 1(c) are diagrams showing a first embodiment of a semiconductor device and its manufacturing method according to the present invention, and show the manufacturing process of a so-called selectively doped heterojunction structure FET using a two-dimensional electron gas in the channel layer. Cross section.

FIGS. 2(a) and (b) are cross-sectional views showing the manufacturing process of a second embodiment of the present invention, FIG. 3 is a cross-sectional view of a third embodiment of the present invention, and FIG. FIGS. 5(a) and 5(b) are sectional views showing the manufacturing process of the fifth embodiment of the present invention; FIGS.

FIGS. 6(a) to (c) are diagrams showing the manufacturing process of the sixth embodiment of the present invention, and FIGS. 10(a) to (Q) are diagrams showing the manufacturing process of the seventh embodiment of the invention. be.

First Embodiment In FIG. 1(a), a semi-insulating GaAs substrate 1
00 using the MBE (molecular beam epitaxy) method, p
-(~5 XIO"Ql-3) GaAs layer 11 is 1μ
m grow. Next, n-type undoped Ajlx G
The layer 12 of al-x A s (usually X is selected to be 0.3 or more) was grown by 60 people. Next, an n-type Ally G containing 2X10"aI"" SL as an n-type impurity
at -)' A S (usually y is 0.05 to 0.
150 layers (used in the range of 25) were grown, and undoped n-type MzGa1 was used as a separation layer.
-zAs (usually 2 is used at about 0.3) layer 18
grew by 100 people. Furthermore, undoped n-type G
a Grow 100 s layers 19 and grow 2x10 As
The "n" Ge layer 2 containing Rho 3 was grown by 300 people, moved to a separate room in an ultra-high vacuum, and the A1 layer 10 was formed by 3000 people.

Next, the elements between the transistors are separated by etching.
CVD Si as gate metal lift-off spacer
n, 20 was formed by 4,000 people. Furthermore, after processing the gate photoresist 40, using the photoresist 40 as a mask, Si0.20 is removed by dry etching, and then an inverted trapezoidal taper is formed by wet etching to facilitate lift-off.

Next, using dry etching, the source electrodes 10, n
- selectively etching away the Ge layer 2; Etching residues are then removed by chemical treatment. PhotoCVD at room temperature
5iN21.22 was damaged by 1000 people using the method. In this case, the insulators 21 and 22 do not need to be limited to SiN,
Sio, amorphous Si, etc. may be used. Also, E C
R(Electron Cyclotron Re5o
-nance) may be formed using a plasma CVD method.

Next, the side wall insulator 2 is etched using an anisotropic dry etching method.
5iN 22 and 41 are removed while leaving 1, 6,000 layers of aluminum are vacuum-deposited as gate metal 30 (see FIG. 1(c)), and lift-off is performed. At this time, the threshold voltage Vth was −0.8 V due to device design. Next, to form an enhancement type FET, a similar photoresist process and etching process are performed.The difference from the former is CC.
The undoped GaAs layer 19 is also selectively etched by nz F x /He mixed gas RIE (reactive ion etching). As above, Vt
An enhancement FET of h~0.1v was obtained. The gate metal 31 at this time was a thorn as in the depression type (FIG. 1(C)). Further, in order to form the source and drain electrodes in the usual manner, it is sufficient to selectively remove the Sin 20 through a photoresist process and form them connected to the source metal 10. In this embodiment, an example is shown in which aluminum is used as the source metal 10, but any metal such as Au, Pt, Mo, etc. that can be subjected to dry etching process and that can be ohmically connected to the high concentration layer 2 may be used.

Further, although n''Ge is illustrated as an example of the high concentration layer 2, this is not necessarily necessary, and the source metal 1o and the active layer 18.
Any material may be used as long as it acts as a barrier semiconductor for making ohmic contact with 19.13.12.

Second Embodiment The second embodiment shown in FIGS. 2(a) and 2(b) is an application of the present invention to a low-noise ultra-high frequency GaAs MESFET. MOM on semi-insulating GaAs substrate 100
Using BE (gas sourced MBE), undoped GaAs 11 was deposited at 1 pm, GaAs/AjLG
5000 layers of aAs superlattice buffer layers 8 and 9, and further undoped AQxGax-xAs (x ~ 0.3) 1
1000 g, and further 500 n-type GaAs (doping level 5
n"Ge2' and further Ti/PtAu1O 3
An insulating film CVD5iO□20 was formed to reduce the fringing capacitance of the source-gate capacitance C8s. Next, photolithography of the gate φ is performed, and dry etching is used to process the S
i0.20. Each layer of Ti/Pt/Au1O1n"Ge2' was removed by dry etching. Subsequently, the gate recess portion was coated with Si, N, and 2A by the usual CVD method as shown in FIG. 2(a), and the layers were removed by dry etching. Si, N, and 23 on the bottom and flat surface of the gate were removed, Mo/Au was vacuum-deposited as a gate metal by 8,000 vacuum evaporators, and a gate electrode was formed using dry etching as shown in FIG. 2(b). The above FET is the result of trial production, source,
The distance Ls between the gates is 0.15 μm, and the ohmic contact resistance γ. could be reduced to 0.02Ω.

Third Embodiment The third embodiment shown in FIG. 3 is an example in which the present invention is applied to a P-channel selectively doped heterojunction FET. M.O.
- doping level of n- (~10'4cn-" or less) on semi-insulating GaAs substrate 100 using MBE.
A GaAs layer 11' is grown to a thickness of 1 μm, and Be is 2×1
M, Ga, -yAs (y-0
, 4) Form 500 60 and 2X
A p"Ge layer 61 containing 10"■-3 was formed by 3000 people, a Ti layer 62 was formed by 3000 people in another ultra-high vacuum chamber, and a Si02 layer 20 for a spacer was formed by 4000 people (Figure 3).
.

Thereafter, through the same process as in the second embodiment, a Schottky connection was made to the p-type layer 60 using Mo/Au as the gate metal.

Fourth Embodiment An example in which the present invention is applied to a complementary selectively doped heterojunction FET is shown in FIG. 4. After forming an n-channel FET (FIG. 4A) in the same manner as in the first embodiment, Using a selective epitaxial growth method, an FET using a two-dimensional hole gas as a carrier is formed as shown in FIG. Unlike the third embodiment, in order to improve hole mobility, n-Mx
Thirty Gal-xAs layers 12 are inserted. In addition, in order to increase the breakdown voltage of the Schottky junction, undoped u, G
a1-. 150 people form the As layer 18. Source/drain metal 1 for both n-channel/p-channel
The SiN layer 21 is formed in the recessed portion by photo-CVD so as not to contact the gate metals 30 and 30' with the gate metals 30 and 30'.

Fifth Example A fifth example in which an n'' GaAs layer is used as the highly doped semiconductor layer is shown in FIGS. 5(a) and 5(b).Semi-insulating GaAs
O2 doped Ga is formed on the s substrate 100 using MOCVD.
A 1 μm thick As layer 11 (semi-insulating) is formed, and 4
X1017am-” Si-doped GaAs layer 1'
Formed 700 people, 2X10"C10-3 Si-doped G
After forming 3,000 layers of aAs layer 2', AuGe/Ni/Auto' was deposited using vacuum evaporation method as shown in Fig. 5(a).
Apply it like this. Thereafter, device isolation is performed by mesa etching, and the gate electrode 3 is removed in the same manner as in the first embodiment.
0' was formed using Mo/Au as shown in FIG. 5(b).

Sixth Example The electrode forming method of the present invention was applied to HBT (Hetero-j
unction Bipolar Transistor
An example of application to the base electrode formation of r) is shown in Figure 6 (
Semi-insulating Ga As shown in a), (b), and (c)
4 x 10” Si is deposited on the substrate 100 using the MBE method.
5,000 layers of n-GaAs layer 101 containing SL, 4,000 layers of n-GaAs 102 containing SL, and 2× Be.
2000 p-type GaAs103 (base layer) containing 10"cm-', 2 x 1017cxn SL
-'containing n-type AIIX G az -X A S
(X ~0.3) 104 for 4000 people, Si for 5X1
40% of n-type Ga A 5105 containing 0"am-'
00 people formed. After that, CVD Sin, film 200
was applied as shown in FIG. 6(a). Next, the implementation process of only the base electrode forming part is shown in Fig. 6(b) and (Q).
Shown below. The emitter electrode can be formed using a commonly used method, and the collector electrode can be formed using a method similar to that for forming the base electrode. After 1.14 coats of photoresist 201 for forming the base electrode and processing, anisotropic dry etching and chemical etching were used to form a 200mm photoresist.
, n-type GaAs 104, and n-type AuGaAs 103 were removed. SiN film 2 was formed using the photo-CVD method at a substrate temperature of 120°C.
03 and 204 as shown in Figure 6(b).
Formed a person.

Next, the photo-CVD SiN film 204 formed on the side wall by anisotropic dry etching is left, the other parts are removed, and the base electrode metal 205 is deposited, as shown in FIG.
Lift-off was performed as in c). An AuZn alloy was used as the base electrode metal.

An ohmic electrode was formed under the conditions that the alloy temperature was 450° C. for 2 minutes.

As mentioned above, the photo-CVD 5iN204 left on the side wall has poor electrical insulation, so after electrode formation, it is removed using hydrofluoric acid diluted to 1/100, and then a new passivation film is formed using plasma CVD, etc. may be formed. Furthermore, in the case of the present invention, if all the gaps between the forming electrode and the semiconductor layer electrically separated by the insulating film are filled with an insulating material, a problem arises in that parasitic capacitance increases. Therefore, if a gap is formed between the formed electrode and the sidewall insulating film, an increase in parasitic capacitance can be suppressed.

Seventh Embodiment FIG. 10 shows an embodiment in which the present invention was used to fabricate a GaAsM ESFET by ion implantation. n-type G
aAs region 71. After forming the n+ source/drain region 70, source/drain electrodes 32, 33, and spacer insulating film 72.

A photoresist 73 for forming a gate is formed as shown in FIG. 10(a). Next, 3,000 layers of 5iN22 were deposited by photo-CVD at a substrate temperature of 120°C. (Figure 10(b)
). Using an anisotropic dry etching method, the gate electrode 30 is formed by lift-off, leaving the sidewall insulating film 22 as in the present invention. Photo-CVD film has a slow deposition speed (2n
m/min to 10 nII/min), the sidewall insulating film can be controlled with very good controllability.

In the case of this example, the opening distance of the gate photoresist in FIG. 10(a) is 0.8t1m, and the Si
Since the thickness of the N film was 3000, the finished gate length (FIG. 10(C)) was 0.44.

Thus, the present invention can be said to be a process that is extremely suitable for manufacturing submicron FETs.

〔Effect of the invention〕

As described above, the semiconductor device and the manufacturing method thereof according to the present invention provide a single step of electronically connecting at least one type of active layer or an active layer located below an electrically active layer, or a layer similar thereto. The electrode metal formed by the photoresist process is separated from the at least one type of active layer or electrically active layer via the sidewall insulator, so that the first electrode metal and the second electrode Distance from metal 0.15. The contact resistance γ can be controlled with extremely good controllability, and since a barrier semiconductor layer with an extremely high concentration is inserted between the active layer and the electrode metal, the contact resistance γ. 0.02Ω at the end
am or less. As described above, according to the present invention, the resistance between the source and gate of the FET can be lowered to the utmost limit, and therefore, the transistor performance can be significantly improved. Moreover, the side walls of the recessed gate can be formed using a low temperature process of room temperature to 100° C. using photo-CVD or the like.

Only one photoresist process is required, and there is no problem of fringing capacitance due to gate overhang.

[Brief explanation of drawings]

FIGS. 1(a) to (Q) show the first part of the semiconductor device according to the present invention.
2(a) and (b) are manufacturing process diagrams showing the second embodiment of the present invention. FIG. 3 is a sectional view showing the third embodiment of the present invention. 4 is a cross-sectional view showing the fourth embodiment of the present invention, FIGS. 5(a) and (b) are cross-sectional views showing the manufacturing process of the fifth embodiment of the present invention, and FIG.
a) to (c) are cross-sectional views showing the manufacturing process of the sixth embodiment of the present invention, FIGS. 7(a) and (b) are cross-sectional views explaining details of the present invention, and FIGS. 8 and 9. Figures (a), (b)
) are diagrams for explaining the source and gate of a conventional field effect transistor, respectively, and FIGS. 10(a) to (c) are diagrams showing a seventh embodiment of the present invention. 2.2', 2', 61...high concentration semiconductor layer 10.62
...Source/drain electrode metal 12.13.18.1
9...Active layer 21.22.23...Side wall insulator 30.30', 31...Recess gate metal agent Junnosuke Nakamura 1 Figure and 2 (Q) t3 diagram? 6 faces (a) (b) (C)? Figure 7

Claims (1)

[Claims] 1. An electrode formed in a single photoresist step that is electronically connected to at least one active layer or an active layer located below the electrically active layer, or a layer similar thereto; A semiconductor device in which a metal is formed separately from the at least one type of active layer or electrically active layer via a sidewall insulator. 2. A semiconductor layer with a high concentration (2×10^1^8 cm^3 or more) is inserted between the electrode metal and the active layer or a layer similar thereto. A semiconductor device described in scope 1. 3. Perform only one photoresist process for forming the second electrode on the first electrode metal or high concentration semiconductor layer formed on the active layer or a layer similar thereto, and remove the first electrode metal or high concentration semiconductor layer. After selectively removing the layer, a sidewall insulator is deposited using a low temperature process such as photo-CVD that does not significantly deform the photoresist, and the sidewall insulator is recessed by anisotropic etching or the like. A method for manufacturing a semiconductor device, comprising the step of removing the insulator on the photoresist and lifting off the second electrode metal by vapor deposition.