JPS62140292A - Semiconductor memory - Google Patents

Abstract

PURPOSE:To prevent a through current from flowing between a sense amplifier and a sense output latch circuit by providing a gate circuit to the input stage of the latch circuit and latching its output in an FF which operates complementarily to the gate circuit. CONSTITUTION:When a clock phi for sense amplifier control goes up to '1', the clocked CMOS inverter 12 of the sense output latch circuit 10 operates to read out the sense output of the sense amplifier 1 in operation. At this time, the clocked CMOS inverter 18 of the FF of the circuit 10 is off, and put in operation when the clock phi goes down to '0' to turn off the inverter 12 and amplifier 1, so that the FF latches the output of the inverter 12. No through current, therefore, flows between the amplifier 1 and inverter 12 which are off in a data holding state to reduce the current consumption; and the input level of the latch circuit is affected by only the sense output of the sense amplifier and the dimension determination of the transistor of the inverter 12 is facilitated, so that designing is facilitated.

Description

Detailed Description of the Invention [Technical Field of the Invention] The present invention relates to a complementary insulated gate type (CMO) semiconductor memory, particularly a semiconductor memory equipped with an address change detection circuit.
This invention relates to an S-type sense output latch circuit.

[Technical background of the invention]

Most recent read/write RAMs (random access memories) are internally synchronous (externally asynchronous).
system. The internal synchronous system is a system that detects changes in asynchronously input addresses, etc., creates a single pulse, and uses this pulse as a clock to control the internal operation of the RAM. On the other hand, in order to speed up the access time in the RAM read mode, a sense amplifier is connected to the pit line of the memory cell array to quickly amplify data read from the memory cell to the bit line. However, since sense amplifiers generally consume a lot of power, the current situation is to take some kind of measure to the sense amplifiers to reduce power consumption.

For example, conventionally, a transistor that is switch-controlled by the sense amplifier control clock is connected to the sense amplifier, and the sense amplifier's operation is stopped during periods when the sense amplifier's operation is not required, thereby reducing the power consumption of the sense amplifier. ing.

In this case, a sense output latch circuit for latching the output of the sense amplifier is connected to the sense amplifier.

FIG. 6 shows a sense amplifier 1 and a sense output latch circuit 60 in a conventional RAM. The address change detection circuit 2 and the sense amplifier control clock generation circuit 3 are extracted and shown. That is, each sense amplifier I is an N-channel M transistor for sense amplification whose source and back gate are connected to each other.
O8) It has a current mirror circuit consisting of P-channel MO8) transistors Q3, Q as a load for transistors Q+, Q, 2, and has an N-channel MO8) transistor Q for switching for sensing operation control, and A bit line pair BL is provided at each gate of the amplification transistors Q1-Q2.

BL are correspondingly connected, and the switching transistors Q5. A sense amplifier control clock φ is applied to the gate of Q2, and a sense output is taken out from the drain of the sense amplification transistor Q2. In addition, VDD.

VSS is a power supply potential. The sense output circuit 60 is a flip-flop formed by connecting the input and output terminals of two CMOS inverters 64 each consisting of a P-channel MO8 transistor 61 and an N-channel MO8 transistor 2. The sense output is latched by a circuit, and this latch output is led to the data output circuit side. On the other hand, the address change detection circuit 2 includes a delay circuit 4 that delays address signal input from the outside by a predetermined period of time, and performs exclusive OR processing on the output of this delay circuit 4 and the address signal input. and an exclusive OR circuit 5 which outputs an address change detection pulse consisting of a single pulse having a width corresponding to the delay time of . The sense amplifier control clock generation circuit 3 includes:
A delay circuit 6 is provided to delay the single pulse input from the address conversion circuit 2 by a predetermined time and extend the pulse width, and performs a NOR process on the output of this delay circuit 6 and the single pulse input to obtain a predetermined timing. It consists of a NOR circuit 7 that receives a sense amplifier control clock φ.

Next, an outline of the operation of the RAM in the read mode will be explained with reference to the timing chart of FIG. When the address signal input changes, an address change detection pulse ATD is generated, and from the trailing edge of this pulse ATD, a sense amplifier control clock φ having a constant pulse width is generated. When amplifier 1 is not in operation, the bit line pair BL, B
The potential difference between L and L (corresponding to read data from the memory cell) is sensed and amplified, and the latch circuit 60 latches this sense output. In this case, when the pit line BLl1 is higher than the bit line BL'lij, the sense output is 10" and the latch output is 1", and when the BL potential is lower than the BL potential, the sense output is 1" and the latch output is O".
It is. Next, the sense amplifier control clock φ is set to ″′0
” level and the operation of sense amplifier 1 stops, but
At this time, data is held by the latch circuit 60.

[Problems with background technology]

By the way, in the data holding state after the sense output "0" is latched by the latch circuit 60 and the sensing operation is completed, the latch output "1" causes the second CMOS inverter 6 to
The N-channel transistor 62 of sense amplifier 1 is in the saturation region (completely on state), and the load transistor Q of sense amplifier 1 is in the saturation region (completely on state).
4 is in the non-saturation region because a gate bias of VDD-VTHP3 (threshold voltage of load transistor Q3) is applied. This prevents a through current I from flowing from the <V'pD power supply to the ground terminal via the load transistor Q4 and the N-channel transistor 62 of the second CMOS inverter 64 as shown by the arrow in the figure, which reduces power consumption. It becomes a hindrance. Also, the latch circuit input node at this time (
The potential of the sense amplifier output node) is determined by dividing the resistance of the two transistors Q, . . . , 62 through which the through current i flows. Inverter 63
To prevent the transistor 61 from being accidentally reversed,
．． The complexity of the design is also added by having to determine 62 dimensions.

[Purpose of the invention]

The present invention has been made in view of the above circumstances, and allows no through current to flow between the sense amplifier and the sense output latch circuit when sense output data is held, thereby facilitating the design of the input stage transistor of the sense output latch circuit. This provides a semiconductor memory with low power consumption.

[Summary of the invention]

That is, the present invention provides a semiconductor memory in which the operation of a sense amplifier is controlled by a sense amplifier control clock generated based on a detection pulse of an address change detection circuit, and the sense output of this sense amplifier is latched by a latch circuit. , the input means of the latch circuit is provided with a gate circuit whose operation is controlled by a clock having the same or almost the same timing as the sense amplifier control clock and its inverted clock, and the output of this gate circuit is connected to the gate circuit. is characterized in that it is latched by flip-flop circuits whose operations are controlled in a complementary manner.

Therefore, when the sense output data is held, the gate circuit at the input stage of the sense output latch circuit becomes inactive, so no current flows between the sense amplifier and the sense output latch circuit, resulting in lower power consumption. In addition, the gate circuit can be easily designed by focusing on the input level during the sense output latch operation.

[Embodiments of the invention]

Hereinafter, one embodiment of the present invention will be described in detail with reference to the drawings.

FIG. 1 shows a part of the RAM. Compared to the sense latch system of the RAM described above with reference to FIG. 6, the structure of the sense output latch circuit 10 and the sense amplifier control The difference is that a clock φ and an inverted clock φ obtained by inverting the clock φ by a CMOS inverter 1 are provided; the other points are the same, so the explanation thereof will be omitted by adding the numerals `` and '' in FIG. 6. do.

The sense output latch circuit 10 inputs a sense output to a clocked CMOS inverter 12, and latches the output of the clocked CMOS inverter 12 by a flip-flop circuit FF to provide a latch output.

The clocked CMOS inverter 12 has a P-channel transistor 13.1 between the VDD power supply node and the ground terminal.
4 and Nf Yarnel transistors 15, 16 are connected in series, each gate of each transistor 13, 16 is interconnected to form an input terminal of a sense output, and the clock φ corresponds to each gate of each transistor 14, 15. , φ are given. Further, the flip-flop circuit FF is
The input and output terminals of the CMOS inverter 17 and the clocked CMOS inverter 18 are not connected to each other, and the clocked CMOS inverter 18 is in an operating state complementary to the clocked CMOS impark 12 in the input stage. The way clock 6 and φ are given is partially reversed so that

FIG. 2 shows the operation timing of the RAM in the read mode, which differs from the operation described above with reference to FIG. 7 in the following points. That is, the sense output latch circuit 10
In this case, when the sense amplifier control clock φ is at the '1'' level, the clocked CMOS inverter 12 is not in the operating state, and the sense output of the sense amplifier 1 which is in the operating state at this time is read. The clocked CMOS inverter 18 of the pull circuit FF is in a non-operating state.

Next, when the clock φ reaches the 10" level (the clock φ reaches the 1" level), the clocked CMOS inverter 18 of the flip-flop circuit FF becomes operational, and the flip-flop circuit FF switches between the clocked CM and the OS inverter 12. The output of is latched and the data is held.

During this data holding state, the clocked CMOS inverter 12 and the sense amplifier 1 at the input stage of the latch circuit 10 are both inactive.

Therefore, in the data retention state, sense amplifier 1
Even if the load transistor Q4 is in the non-saturation region, the clocked CMOS inverter 12 to which the sense output is input is in a non-operating state, so that the through current between the sense amplifier 1 and the latch circuit 10 as in the conventional example is reduced. There is no flow, and power consumption can be reduced. At the same time, since the input level of the latch circuit 10 is affected only by the sense output of the sense amplifier 1, the clocked CMOS input stage
The dimensions of each transistor of the inverter 12 can be easily determined and the design can be facilitated.

Moreover, the structure of the latch circuit 10 as described above is relatively simple, and the increase in the occupied area on the memory chip and even the increase in the chip area is small, and an inexpensive memory chip can be provided.

It should be noted that the present invention is not limited to the above embodiments.
Clocked CMOS inverter 12.18 of the above embodiment
Instead of CMO8, like the latch circuit 30 shown in FIG.
) Transfer gates 31 and 32 are used, and a flip-flop circuit FF is configured by two CMOS inverters 33 and 34 and the above CMO8) Transfer gate 32, and the input stage CMO8) The output of the transfer gate 31 is connected to the flip-flop circuit. It may be latched by an FF and also inverted and output.

In this case as well, the same operation and effect as in the embodiment described above can be obtained.

In addition, the clocks φ, φ applied to the latch circuit 10 in FIG.
Instead, as shown in FIG. 4, the delay signal obtained from the intermediate stage of the delay circuit 6 of the sense amplifier control clock generation circuit 3 and the address change detection pulse ATD are inverted and obtained exclusively for the two-person circuit 41. Clock φ′ and this as CM
The clock φ' inverted by the OS inverter 42 may be used, and the operation timing in the read mode in this case is shown in FIG.

Further, the present invention is not limited to the RAM of the above embodiment, but also ROM (
It is also applicable to read-only memory).

〔Effect of the invention〕

As described above, according to the semiconductor memory of the present invention, no through current flows between the sense amplifier and the sense output latch circuit in the state where sense output data is held, so that the input stage gate circuit of the sense output latch circuit This makes it easier to design the transistor and realizes lower power consumption.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram showing a main part of an embodiment of the semiconductor memory of the present invention, FIG. 2 is a timing diagram showing the operation of the memory in FIG. 1 in read mode, and FIGS. FIG. 5 is a timing diagram showing the operation of the memory in the read mode of FIG. 4; FIG. 6 is a circuit diagram showing a part of the conventional semiconductor memory; FIG. , FIG. 7 is a timing diagram showing the operation of the memory of FIG. 6 in read mode. DESCRIPTION OF SYMBOLS 1...Sense amplifier, 2...Address change detection circuit, 3...Sense amplifier control clock generation circuit, 10
．． 30...Sense output latch circuit, 11°17.33
, 34.42...CMOS inverter, 12.18.
・・Clocked CMOS inverter, 31.32...
0MO8) Transfer gate, FF...flip-flop circuit.

Claims (4)

[Claims] (1) In a semiconductor memory having a sense amplifier whose operation is controlled by a sense amplifier control clock generated based on a detection pulse of an address change detection circuit and a sense output latch circuit that latches the output of this sense amplifier, the sense output The latch circuit has a gate circuit whose operation is controlled by a clock having the same or almost the same timing as the sense amplifier control clock and its inverted clock at the input stage, and outputs the output of this gate circuit in a manner complementary to the gate circuit. A semiconductor memory characterized in that it is latched by a flip-flop circuit whose operation is controlled. (2) The sense amplifier has two N-channel transistors connected in a current mirror as a load for two driving N-channel transistors.
The semiconductor memory according to claim 1, characterized in that it has P channel transistors. (3) The gate circuit is a clocked CMOS inverter, and the clocked CMOS inverter is used as a part of the flip-flop circuit. semiconductor memory. (4) The semiconductor memory according to claim 1 or 2, wherein the gate circuit is a CMOS transfer gate, and the CMOS transfer gate is used as a part of the flip-flop circuit. .