JPS6138559B2 - - Google Patents

Abstract

PURPOSE:To program CMOS.LSI by setting up the potential of a fuse element terminal through an electrostatic capacity element in accordance with the state of the fuse element to be connected/disconnected in accordance with the program state and generating a program output in proportion to said potential. CONSTITUTION:As an example of a circuit to program a CMOS.LSI circuit, a programmable circuit consisting of a defective address storing circuit 10 which is a part of a peripheral circuit of a CMOS memory, an address buffer circuit 20 and a programming circuit 30 is prepared. In the defective address storing circuit 10, one end of a fuse element F is connected to the 1st electric power supply Vss (an earth terminal as reference potential) and the other terminal Q is connected to one end of the electrostatic capacity element CE. The potential of the point Q is set up by a signal applying circuit 11 connected to the other end of the element CE in accordance with the state of the fuse element connected/disconnected in accordance with the program state, and an program output is generated in proportion to the set-up potential.

Description

DETAILED DESCRIPTION OF THE INVENTION <Technical Field of the Invention> The present invention relates to a programmable circuit for repairing defects in CMOS memories and the like and for programming CMOS LSI circuits.

<Technical background of the invention and its problems> As the integration density of MOS-LSI increases and the chip size increases, it is becoming difficult for all the elements integrated on one chip to operate without defects.
For example, memory LSI has a density of 64K bits,
As the capacity increases to 256K bits and 1M bits, it is expected that the yield of chips that operate on all bits will continue to decline, and this is being highlighted as a problem that hinders capacity increases. A defect recovery means equipped with a defective address storage circuit has emerged as a means to solve this problem, and has already begun to be put into practical use in N-channel MOS memory LSIs. This defect relief means is provided with spare memory rows and row decoders or memory columns and column decoders in the matrix memory array of the MOS memory LSI, and when there is a defective bit in the matrix memory array, the row containing the defective bit or The column is replaced with the spare memory row, row decoder, or memory column, column decoder for relief. In this case, a fuse element is used in the defective address storage circuit, and the address of the defective bit is stored depending on the disconnection state (connected state and disconnected state) of this fuse element, and the address of the defective bit is selected. At this time, the spare row decoder or column decoder is selected to use the spare row or column, and the selection of the row or column containing the defective bit is prohibited.

FIG. 1 shows this type of conventional defective address storage circuit, where Xi and Xi are address signal inputs, P is a program (write) input, and Xpi is an address signal selection output. When the fuse element F is not disconnected, the node Q is at the power supply Vcc potential (for example, 5V), the transistor _T1 is on, the output of the inverter I is 0V, and the transistor
_T2 is off and the address signal input Xi is derived as the address signal selection output Xpi.

On the other hand, when program input P is set to 0V during programming in advance, transistor T ₃ is turned off and transistor T ₄ is input as an address signal input.
If Xi is 0V, it will be off, and if Xi is at Vcc potential, it will be on. When this transistor _T4 is off,
The transistor T ₆ to which the potential of the program power supply Vpp (for example, +10 V) is applied through the transistor T ₅ is turned on, and a blowing current flows through the fuse element F, cutting off the fuse element F. Therefore, when fuse element F is disconnected, node Q becomes 0V, transistor _T1 is turned off and transistor _T2 is turned on, so that address signal input is not possible.
Xi is derived as the address signal selection output Xpi.

That is, the defective address storage circuit receives an address signal input depending on whether a defective address is written in the fuse element F, that is, whether the fuse element F is disconnected or connected.
Xi or Xi is derived as the address signal output Xpi.

However, in the above-described defective address storage circuit of FIG. A depletion type transistor _T7 is connected as an element, and therefore, when the fuse element F is in a connected state, a direct current consumption occurs through the series circuit of the fuse element F and the transistor _T7 .

This current consumption is N
Although this is not a problem in the case of channel MOS memory, it cannot be ignored in the case of CMOS memory, where standby current consumption must be suppressed to several hundred μA or less. In particular, battery backup type
For CMOS memory, standby current consumption is 1μ
It is necessary to suppress A to several tens of microamperes, and in this respect, it has been difficult to provide a defect relief means.

In addition, the CMOS LSI outputs the program output for the purpose of programming the CMOS LSI function switching.
Similarly, for programmable circuits in general, it has been difficult to reduce the standby current to a small and negligible value.

<Objective of the Invention> The present invention has been made in view of the above circumstances, and includes a programming fuse element for relieving a defective circuit part in a CMOS circuit or switching the functions and characteristics of a CMOS LSI, and a standby current. The objective is to provide a programmable circuit that can be made small and negligible.

<Summary of the Invention> For the above purpose, the present invention includes a fuse element to which a first potential is applied to one end and is connected or disconnected according to a program state, and a capacitive element connected to the other end of the fuse element. Means for setting the potential at the other end of the fuse element by applying a signal to a terminal different from the terminal connected to the fuse element of this capacitive element, and a potential generator for generating a program output according to the set potential. By comprising means, the current consumption for detecting the programmed state of the fuse element can be significantly reduced to a negligible level,
The present invention provides a programmable circuit that enables battery backup of a CMOS LSI equipped with a programmable circuit, and makes it possible to realize a CMOS VLSI with high yield or high functionality.

<Embodiment of the Invention> An embodiment of the invention will be described in detail below with reference to the drawings. FIG. 2 shows a defective address storage circuit 10, an address buffer circuit 20, and a program circuit 30, which are part of the peripheral circuits of a CMOS memory. In the defective address storage circuit 10, one end of the fuse element F is connected to the first power supply Vss (in this example, the ground terminal as a reference potential), and the other end (node Q in the figure) is connected to the fuse element F in series with an electrostatic capacitor. One end of capacitive element C _E is connected. Reference numeral 11 applies a pulse signal to the other end of the capacitive element C _E , for example, in synchronization with a change in the power supply Vcc (for example, a 5V power supply) when it is turned on, to give electrical energy through the capacitive element C _E ; The potential at the connection node Q between the capacitive element _C and the fuse element F is set to the fuse element F.
This is a signal application circuit that is set according to two states: connected or open. The node Q is connected to the input terminal of the inverter I ₁ and the drain of the P channel transistor T ₂ , whose source is connected to the power supply Vcc, and whose gate is connected to the input terminal of the inverter I ₁ and the drain of the P channel transistor T ₂ .
connected to the output end of the That is, the inverter I ₁ and the transistor T ₂ hold the potential set at the node Q and generate an output at the OUT node according to the two states of the fuse element F, connected or disconnected, to the address buffer circuit. It constitutes a potential holding circuit 12 that supplies the potential to 20.

On the other hand, in the address buffer circuit 20, the potential holding output supplied from the defective address storage circuit 10 is guided to the inverter _I2 and the gates of the P channel transistor _T3 and the N channel transistor _T4 . An N-channel transistor _T5 is connected in parallel to the P-channel transistor _T3 , and a P-channel transistor _T6 is connected in parallel to the N-channel transistor _T4 . The output of the inverter I ₂ is supplied to each gate of the transistors T ₅ and T ₆ , and the parallel transistors T ₃ and T ₅ and the parallel transistors T ₄ and T ₆ are connected in series. Ori,
An address signal Ai is input to one end of this series circuit, and an address signal Ai is input to the other end. That is, the inverter I ₂ and the four transistors T ₃ , T ₄ , T ₅ , T ₆ select one of the address signals Ai and Ai depending on the output potential of the defective address storage circuit 10. , constitutes a switch circuit 21 that outputs a defect relief address signal selection output Xi from a connection node between parallel transistors T ₃ and T ₅ and parallel transistors T ₄ and T ₆ . Note that the inverters I ₃ , I ₄ , I ₅ , and I ₆ are connected in cascade, and the address input signal PAi (i=0 to n)
constitutes an address drive circuit 22 which inputs the address signals Ai and outputs the address signals Ai and Ai.

On the other hand, in the program circuit 30, a P channel transistor for program control
_T7 and the defective addressing P-channel transistor _T8 are connected in parallel, and their source is connected to the power supply Vcc.
The drain thereof is connected to the programming power supply Vpp via the load element 31. The program control input signal PR is applied to the gate of the transistor _T7 , and the address buffer circuit 2 is applied to the gate of the transistor _T8 .
The output of inverter _I4 of 0 is applied. The gate of a P channel transistor T ₉ for programming is connected to the connection node P between the drains of these transistors T ₇ and T ₈ and the load element 31, and the source of this transistor T ₉ is connected to the power supply Vcc. The drain is connected to the node Q of the defective address storage circuit 10.

Next, the operation of FIG. 2 in the above configuration will be explained with reference to the timing diagram of FIG. 3.

First, in the program mode, an address including a defective bit is designated by a high (H) level (for example, +5V) or a low (L) level (for example, 0V) as the address input signal PAi. In this state, at time _t1 , the program power supply Vpp is changed from the high level to the negative voltage program level Vp (for example -
10V). Next, at time t(2), the program control input signal PR is changed from low level to high level and the program control transistor _T7
Turn off. At this time, since a signal of the same logic level as the address input signal PAi is applied to the gate of the defective addressing transistor _T8 from the inverter _I4 , it is turned off when the above-mentioned PAi is at a high level, and turned on when it is at a low level. There is. Therefore, the potential at node P will be at the negative voltage program level Vp if the transistor _T8 is off (PAi is at a high level), and will be at a high level (power supply Vcc level) if the transistor _T8 is on (PAi is at a low level). It will be maintained as is. When the potential of this node P is at the negative voltage program level Vp, the programming transistor _T9 drives a large current of about 10 mA to blow out the fuse element F, thereby performing programming. Conversely, when the potential at the node P is at a high level, the programming transistor _T9 is off, the fuse element F is not blown out, and no programming is performed.

Next, by returning the program control input signal PR from high level to low level at time _t3 , the program control transistor _T7
is turned back on, and the potential at the node P is forced to a high level via the transistor _T7 . Therefore, the programming transistor _T9 returns to the OFF state, and then the programming mode ends by returning the programming power supply Vpp to the Vcc level (high level).

Next, the operation of generating the defect relief address signal selection output Xi will be explained. After the program mode described above, in the circuit shown in FIG. 2, the power supply Vcc is generally cut off for a period of time. This is because programming for defect relief is generally performed when chips are selected on a wafer, and then the chips are cut out from the wafer and mounted on a package. Of course, in rare cases, it is possible to write a program after mounting to repair defective bits, but even in this case, the power supply Vcc may be cut off.

It is now assumed that the power supply Vcc is cut off at time _t5 , and the power supply Vcc is turned on again at time _t6 . Further, the signal application circuit 11 in FIG. 2 is, for example, a power-on detection circuit as shown in FIG. 4a, and generates a signal R in synchronization with power-on. During the period from time t ₆ when the power is turned on to time t ₇ when signal R is generated, the potential at point Q is unstable. That is, for example, if fuse element F is in an open state, Q is Vss
It can be at either level (ie 0V) or Vcc level (5V). This is because if the P-channel transistor _T9 is kept non-conducting, and if the Q point accidentally becomes 0V as the initial state, the output of the inverter _I1 becomes 5V, the P-channel transistor _T2 also becomes non-conductive, and the Q point becomes This is because it becomes a floating voltage level.

Now, when the signal R changes from 0V to 5V at time _t7 , the voltage increases △V at point Q due to the capacitance division between capacitance element C _E and stray capacitance element C _S at point Q through capacitance element C _E. =C _E /C _E +C _S ×5V is generated. Now, since C _S << C _E , △V5V, and if the fuse element is open, the potential at point Q is about 5V.
or higher potential. Inverter _I2 brings the potential of node OUT to Vss, that is, 0V, and P channel transistor _T2 becomes conductive, changing the potential of point Q.
It is then latched and held at Vcc potential (5V). Now, if the fuse element is in a connected state, the voltage increase that should occur at point Q is canceled out by the current flowing to Vss through the fuse element, and the potential at point Q becomes 0V. At this time, the output potential of the inverter _I1 becomes the Vcc potential (5V), and the P channel transistor _T2 becomes non-conductive, so when the charging and discharging of the capacitance element _CE is completed, the Q point is then grounded to the Vss potential. However, no static current will flow. In this way, it is possible to read binary information consisting of two states of the fuse element F, that is, the connected state or the open state (disconnected state), by the signal R through the capacitive element C _E.

As a result of the readout described above, when the node Q is at a high level, the output node OUT of the inverter _I1 becomes a low level, and in the switch circuit 21, transistors _T3 and _T5 become conductive, and transistors T4 and _T6 become _conductive . Since it becomes non-conductive, the defect relief address signal selection output
Address signal Ai is derived as Xi. On the other hand, when the node Q is at a low level, the output node OUT of the inverter I ₁ is at a high level, and in the switch circuit 21, transistors T ₄ and T ₆ are conductive, and transistors T ₃ and T ₅ are non-conductive. So,
An address signal Ai is derived as the output Xi.

As described above, the defective address storage circuit 10 of FIG. 2 connects one end of the capacitive element C _E for memory readout in series with the fuse element F, and connects the other end of the capacitive element C _E to the fuse element F for power-on detection. It is driven by the output of a signal application circuit such as a circuit, and voltages corresponding to two states of the fuse element F, connected or opened, are obtained. Therefore, when the output signal R of the signal application circuit 11 changes, a current flows through the capacitive element C _E. When the output signal R remains unchanged and the address input signal remains unchanged, that is, in the standby state, the fuse element Even if the fuse element is connected, no current flows and the characteristics of the CMOS circuit are not lost. Note that no current flows through the inverters I ₃ , I ₄ , I ₅ , and I ₆ of the address buffer circuit 20 in the standby state, similarly to the above. Therefore, by adopting the circuit shown in FIG. 2, it becomes possible to use battery backup as a CMOS defect relief means, and it becomes possible to realize a CMOS super LSI with a defect relief circuit at a high yield.

In the above embodiment, even if the blown fuse element F causes leakage current, the fuse can be removed by appropriately selecting the relationship between the capacitance element C _E for reading memory and the slope of the rise change of the signal R. The potential of node Q can be uniquely set depending on the magnitude of the current flowing through element F, and this
Since it can be held by the action of T ₂ , it is possible to realize a defective address storage circuit with extremely high reliability.

Note that the signal application circuit 11 in FIG. 2 is not limited to the circuit shown in FIG. The output of the circuit shown in FIG. 4 and the output of the circuit synchronized with the chip selection signal may be subjected to AND processing or OR processing. Furthermore, the same effect can be obtained by inserting a transistor between the fuse element F and the first power supply Vss or between the fuse element F and the capacitive element _CE . In this case, the gate of the transistor to be inserted is applied with, for example, a chip selection signal, a pulse signal synchronized with the chip selection signal, or a signal obtained by AND or OR processing of the circuit output in Figure 4 and the circuit output synchronized with the chip selection signal. do it. Note that the power-on detection circuit shown in FIG. 4a is well known. In Figure 4a,
P ₁ and P ₂ are P channel transistors, N ₁ to _{N 3} are N channel transistors, I ₁₁ to I ₁₄ are inverters, and C ₁ and C ₂ are capacitors.

As shown in Figures 4a and 4b, the power supply voltage Vcc rises from 0V to 5V at the same time as the power is turned on, and this signal applies 5V to the gate of the N-channel transistor _N3 , turning on the transistor _N3 . ₁
The stored charge is discharged, and the signal R rises from 0V to 5V. Note that the delay time τ is approximately determined by the discharge time of the capacitor _C1 and the delay time of the inverters _I11 to _I14 .

Further, the program writing to the fuse element is not limited to the current blowing of the above embodiment, but may also utilize laser beam cutting as shown in FIG. 5.

Further, as shown in FIG. 5, the purpose of the present invention can be similarly realized by directly applying the power supply V _DD to the terminal of the capacitive element C _E that is not electrically connected to the fuse element. The power supply V _DD may be the same power supply as the power supply V _CC or may be a separate power supply. An example of the operation timing at that time is shown in the sixth section.
As shown in the figure.

Furthermore, the capacitive element C _E can be constructed as shown in FIGS. 7 to 9. FIG. 7 shows an example in which a gate oxide film is used as a capacitance element. 7th
Figures a and b show a structural diagram and a circuit diagram, respectively, in which a gate 70 is applied with V _DD or an R signal, and a source terminal 72 is connected to a node Q. Next, Figure 8 shows
This is a case where the junction capacitance of p ⁺ -n is used as the capacitance. In FIG. 8, node Q is connected to p ⁺ region 80 and V _DD is connected to n ⁺ region 82. In FIG. FIG. 9 shows the case where the n ⁺ -p junction capacitance is also used as the electrostatic capacitance, but in this case, the p well region 90
Apply the V _DD or R signal to the n ⁺ region 92 formed in p ⁺
A Q signal is connected to region 94. Here, the substrate n-
Si96 is biased to _Vcc .

Furthermore, the present invention is not limited to the above embodiments, but is generally applicable to cases where a fuse element is used to repair a defective circuit part in a CMOS circuit (including cases of logic conversion, etc.).
Furthermore, it can be generally applied to general programmable circuits in which the functions and performance of CMOS LSI are switched by fuse elements.

<Effects of the Invention> As described above, according to the present invention, a capacitive element C _E is connected in series with a fuse element of a programmable circuit, and energy is electrically applied to the fuse element through this capacitive element C _E. Since the circuit is configured to read and hold the voltage according to the two states of the fuse element, connected or open, the current consumption for detecting the disconnected state of the fuse element can be reduced to a negligible level, making it possible to reduce the current consumption to a negligible level, making it possible to reduce It becomes possible to perform current backup, etc., and to provide a CMOS defect relief circuit means that makes it possible to realize a CMOS ultra-LSI with a high yield, and a programmable circuit that provides a means for switching the function and performance of a CMOS LSI.

[Brief explanation of the drawing]

Fig. 1 is a circuit diagram showing a conventional CMOS defect relief circuit, Fig. 2 is a circuit diagram showing an embodiment of the programmable circuit of the present invention, and Fig. 3 is a timing diagram shown to explain the operation of Fig. 2. , FIG. 4a is a circuit diagram showing an example of the signal application circuit of FIG. 2, FIG. 4b is a timing diagram shown to explain the operation of FIG. 6 is a timing diagram for explaining the operation of the programmable circuit of FIG. 5, and FIGS. 7 to 9 are diagrams showing other embodiments of the capacitive element. be. 10... Defective address storage circuit, 11... Signal application circuit, 12... Potential holding circuit, F... Fuse element,
C _E ...Capacitance element.

Claims (1)

[Claims] 1. A fuse element to which a first potential is applied to one end and connected or disconnected according to a program state, and a capacitance element connected to the other end of the fuse element.
Means for setting the potential at the other end of the fuse element by applying a signal to a terminal of the capacitive element different from the terminal connected to the fuse element, and a potential generator for generating a program output according to the set potential. A programmable circuit comprising means. 2. Claim 1, wherein the potential generating means has a potential holding circuit that holds the set potential and generates a program output according to the held set potential. Programmable circuit as described. 3. The programmable circuit according to claim 1 or 2, wherein the signal is at a second potential different from the first potential. 4. The programmable circuit according to claim 1 or 2, wherein the signal is a pulse signal synchronized with changes in address signal input. 5. Claim 1, wherein the signal is a pulse signal synchronized when the power is turned on.
The programmable circuit according to item 1 or 2. 6. Claim 1, wherein the signal is a pulse signal synchronized with a chip selection signal.
The programmable circuit according to item 1 or 2.