JPS6111993A - Semiconductor memory device - Google Patents

Abstract

PURPOSE:To make it unnecessary to consider the refresh timing and to shorten sufficiently the access time by providing two types of lines, that is, bit line and word line, with respect to one memory cell. CONSTITUTION:A capacitor CS is to store data of ''1'' and ''0'' as the charge accumulation, and its end, namely, a data storage node M, is connected to a data access bit line BL through a transfer gate MOS transistor Q1. Its gate is connected to a data access word line WL. Moreover, the storage node M is connected to a data refresh bit line RBL through other transfer gate MOS transistor Q2. Its gate is connected to a data refresh word line RWL, while other end of the capacitor CS is connected to a prescribed potential supply point, for instance, a power supply voltage impression point. Thus the capacitor CS can be refreshed with use of the bit line RBL and word line RWL at an arbitrary point.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a semiconductor memory device, and particularly to a dynamic readable/writable memory device that requires a refresh operation.

[Technical Background of the Invention and Problems thereof] FIG. 8 is a circuit diagram showing the configuration of a typical conventional dynamic read/write memory (dynamic RAM). In the figure, MC1, MC2-... are memory cells, DCl, DC2 are dummy cells, BL, BL are bit lines, CB is bit line BL, capacitance existing in BL, WL
1, WL2... are word lines, DWLI, DWL2 are dummy word lines, SA is a sense, amplifier, SE-bound sense amplifier enable line, T1. T2 is a column selection MOS transistor D controlled by the column selection signal CD.
L and DL are data lines, and OUT is an output circuit that outputs data.

Each memory cell MC has one capacitor C.

and one transfer gate MOS transistor Q
Each dummy cell DC has one capacitor CD and one transfer gate cell. M.O.
and an S transistor QD.

However, the charge accumulated in the capacitor CB in the memory cell MC usually decreases over time due to leakage or the like. Therefore, it is necessary to read out this charge once and rewrite it before the charge completely disappears, thereby accumulating the charge again. This operation is called refresh, and generally dynamic RAM always requires this refresh operation. For example, 256
Dynamic RAM with 2 bits has a limitation in that all cells must be refreshed once every 4 milliseconds.

FIG. 9 shows a timing chart when this refresh is performed periodically. In other words, set the normal period ■ and refresh period ■ for data access,
A refresh period (2) is inserted at regular intervals to perform a refresh operation, and normal data access operations cannot be performed during this refresh period (2). This is because, for example, when the capacitor Ca in the dead memory cell MC1 is being refreshed, the bit lines BL and BL are the data of this capacitor C8, and it is impossible to read data from other capacitors at this time. , C exists because it is possible. Therefore, when refreshing is performed periodically, even if an access request to this RAM occurs during the period when refreshing is performed, it must be held until the refreshing is completed, resulting in the inconvenience that the access time becomes equivalently longer. . This is a problem because it is incompatible with increasing the speed of RAM.

FIG. 10 is a timing chart showing the operation of the conventional RAM shown in FIG. 6 above. , in this RAM, address A
One cycle begins when dd changes or a chip enable signal (not shown) is input. Next, for example, the signal on the word line WL1 is set to 1'' and the corresponding memory cell MCI is activated. After that, cell data is output from the activated memory cell MCI to one bit line BL. At this time, the signal of the dummy word line DWL1 is also set to "1", and the signal from the dummy cell DC1 to the other bit line B
Cell data is output to L. In the capacitor CD in this dummy cell DC1, an amount of charge approximately intermediate between the charge corresponding to the data "'1" stored in the capacitor C8 in the memory cell MC and the charge corresponding to the data "0" is stored in advance. ing.

Next, the signal on the sense amplifier enable line SE is set to "1", the sense amplifier SA is activated, and the bit lines BL, B
The potential difference between L is amplified by this sense amplifier SA. At this point, the signal on the word line WL1 is still set to 1'', so the amplified data is written again into the memory cell MC from which the data was read, and refreshing is performed.

On the other hand, when outputting data instead of refreshing, after outputting the data in the memory cell MC to the bit line BL as described above, the MOS transistor for column selection and the register T1. T2 is made conductive by column selection signal C[), and bit line BL is made conductive.

The data of BL is transmitted to data l1lDL and D. After this, the output circuit 0LIT outputs the data Dout.

At this time, since the output circuit OUT performs waveform shaping, etc., the data [) out is output with a considerable delay after the data is output to the bit lines 8m and BL.

Unlike the case where refresh is performed at regular intervals as described above, refresh in this case imposes a burden on the RAM user, such as constantly finding the timing, making dynamic RAM difficult to use.

However, dynamic RAM usually has a cell area 1/2 that of static RAM, which does not require refreshing.
Since only 4 is required, it is essential for achieving high density, that is, high integration.

[Objective of the Invention] The present invention has been made in consideration of the above-mentioned matters, and its purpose is to provide a semiconductor memory that does not require consideration of refresh timing and can also sufficiently shorten access time. The goal is to provide equipment.

[Summary of the Invention] In order to achieve the above object, the present invention provides a first bit line and word line for normal data access and a second bit line and word line for data refresh. , a first MC8 transistor for a transfer gate is inserted between one end of the information storage capacitor and the first bit line, and the gate of the first MOS transistor is connected to the first word line, A second MOS transistor for a transfer gate is inserted between one end of the capacitor and a second bit line, and the gate of this second MoS transistor is connected to a second word line to form one memory cell. That's what I do.

[Embodiments of the invention] Hereinafter, one embodiment of the present invention will be described with reference to the drawings.

FIG. 1 is a circuit diagram showing the configuration of one memory cell of a semiconductor memory device according to the present invention. Capacitor CB is “1”
It stores data ", 0" in the form of charge accumulation, and one end of the data storage node M is connected to a data access bit line BL via a transfer gate MOS transistor Q1. Above transistor Q
The gate of No. 1 is connected to the word line WL for data storage. Further, the storage node M is connected to a data refresh bit line R8L via another transfer gate MOS transistor Q2. The gate of the transistor Q2 is connected to a data refresh word line RWL. In addition, the above capacitor C
The other end of B is connected to a predetermined potential supply point, for example, a power supply voltage application point.

By providing two types of bit lines and word lines for one memory cell in this way, one bit line BL can access data in another memory cell.

even if the other bit line RB
L can be used to access the capacitor Cs. Therefore, at any time when the capacitor Cs in the memory cell is not being accessed, the capacitor Ca can be refreshed using the bit line RBL and the word line RWL. Also, if the capacitor Ce itself is being accessed, 1. There is no problem since there is no need to refresh this capacitor c8.

FIG. 2 is a circuit diagram showing the structure of one dynamic RAM using a plurality of memory cells having the above structure. In the figure, MC1, MC2... are respectively capacitors C for data storage as shown in FIG.
B. Two transfer 1-gate MOS transistors Q
1. Q2. Two types of bit lines BL, RBL (BL, R
BL) and two types of word lines, namely word lines WLI, WL2 . . . for data access, word lines RWL1 . RWL2...The memory cells provided respectively, DCI and DC2 are dummy cells for data access, RDCl and RDC2 are dummy cells for data refresh, CB is the bit line BL, the capacitance present in 8L, CRB is the bit line RBL, Capacitance existing in RBL, DWLl, 0WL2 are dummy word lines used during data access, RDWLl, RDWL2 are dummy word lines used during data refresh, SA is a sense amplifier for data access, R8A is for data refresh. sense amplifier, SE is the sense amplifier enable line of the sense amplifier SA for data access, PS
E is the sense amplifier enable line of the data refresh sense amplifier R8A, T1 and T2 are column selection signals C
A MOS transistor for column i selection is controlled by D, DL and OL" are data lines, and 0LIT is an output circuit that outputs data.

The sense amplifier SA for data access includes P channel MOS transistors 11 and 12 and N channel MOS transistors 13 and 14, respectively, as shown in FIG.
Fritzkepflop 17 is connected alternately between the input and output terminals of CMOS inverters IS and IE, respectively, and the above-mentioned sense amplifier enable line SE is easily inserted between this flip 70 knob 17 and the power supply voltage application point.
A P-channel MOS transistor 18 and flip-flop 17 to which an inverted signal of is supplied is inserted between the ground potential point and the gate thereof is connected to the sense amplifier enable line SE.
An N-channel MOS transistor 19 is supplied with a signal of
It consists of Furthermore, the sense amplifier R8A for data refresh is configured similarly to the sense amplifier SA described above, and the transistors 18 and 19 are controlled by the signal of the sense amplifier enable line R8E instead of the signal of the sense amplifier enable line SE. It has become.

FIG. 4 is a timing chart showing the operation of the RAM as shown in FIG. 2 above. Also in the case of this RAM, a data access cycle is started when the address Add changes or the chip enable signal is input. After the cycle starts, the signal on the word line WL1 is set to 1'', for example, and the corresponding memory cell MCI is activated.After that, the signal from the activated memory cell MC1 passes through the transistor Q1 to the bit lines at, . Cell data is output to one bit line BL of TT.At this time, the signal of dummy word IDWL1 is also set to "1", and cell data is output from dummy cell DCI to the other bit line I!iBL. Capacitor C in dummy cell DC1
DO stores in advance an amount of charge approximately intermediate between the charge corresponding to data "1" and the charge corresponding to data "0" stored in the capacitor Cs in the memory cell MC.

Therefore, the potentials of the bit lines BL and BL'' change sequentially in accordance with the amount of charge of the output cell data.Next, the signal on the sense amplifier enable line SE is set to 1°', and the sense amplifier SA is activated, bit lines BL, BL
The potential difference is amplified by this sense amplifier SA. After that, the output data Q is transmitted to the data lines DL and OL.
It is output from the output circuit 0LIT as out.

On the other hand, while the memory cell MC1 is accessing data (reading data in this case), other memory cells in this column, such as memory cell MC2,
When it becomes necessary to refresh data, the word line RW for data refresh of this memory cell MC2 is
The L2 signal is set to 1'', and the cell data is transferred to one of the refresh bit lines RBL and RBL.
Output to 8L. At this time, the signal of the dummy word line RDWLI for data refresh is also set to "1", and the cell data of the dummy cell ROC1 is transferred to the other bit line RBL.
is output to. The capacitor CRO in this dummy cell RDCI also stores in advance an amount of charge that is approximately intermediate between the charge corresponding to the data "1" and the charge corresponding to the data "0" stored in the capacitor CB in the memory cell MC. There is. this.

Therefore, the potentials of the bit lines RBL and RBL sequentially change in accordance with the amount of charge of the output cell data. Then, when the potential difference between both bit lines becomes large to a certain extent, the signal on the sense amplifier enable signal line R8E is set to "1", and the refresh sense amplifier R8A is activated. When this sense amplifier R8A is activated, the bit line RBL.

The potential difference of RBL is amplified. At this point, the word line R-
Since the WLI signal is still set to "1", the data amplified by the sense amplifier R8A is written again into the original memory cell MC2 from which the data was read, thereby performing a refresh operation. Furthermore, the rise of the signal on the word line RWL to "1", which is the start timing of this refresh operation, can be made completely unrelated to the timing during data access. The case shown in FIG. 4 is an example in which refresh is performed before normal data access.

FIG. 5 is a pattern plan view of a memory cell MC when the RAM shown in FIG. 2 is actually integrated into an integrated circuit. In the figure, 21a, 21b, and 21c are N+ type semiconductor regions containing N type impurities, which are formed on a semiconductor substrate containing P type impurities, and serve as the source and drain regions of the transistors Q1 and Q2 and the regions of the capacitor CB. be. On the surface of one of the N+ type semiconductor regions 21C, the capacitor plate 22 of the capacitor C8 is formed of the first polycrystalline silicon layer via a relatively thin insulation II (not shown). It is formed. This capacitor plate 22 is connected to a constant potential point, for example a ground potential point. Further, between the N+ type semiconductor region 21a and 2IC, the word l11WL is formed by a second layer of polycrystalline silicon layer, and similarly the N+ type semiconductor region 2
The word line RWL made of a second polycrystalline silicon layer is formed between 1G and 21b. Both word lines WL and RWE extend in parallel in the same direction. Further, the bit lines BL and RBL made of aluminum or the like are formed parallel to each other in a direction perpendicular to the direction in which the word lines WL and RWL extend.

This bit line BL and the above N" of each memory cell MC
The type semiconductor region 21a is connected to the bit line RBL and the above N+ of each memory cell MC through a contact hole 23.
The type semiconductor regions 21b are connected through contact holes 24.

By the way, as described above, data refresh may be performed once for each cell in a certain fixed period.

For example, in a 256-bit dynamic RAM, the processing may be performed every 4 milliseconds. FIG. 6 is a block diagram showing the configuration of a RAM according to an applied example of the present invention, which automatically performs such a data refresh operation. This R
In AM, memory cells are divided into multiple memory blocks 1ooa.
, 1oob..., and a column sense amplifier 110 is provided for each memory block 100.
One row decoder for each two adjacent memory blocks 100
There are 20. Therefore, in this RAM, the bit line (B
L.

RBL) is divided into multiple parts, and the bit lines within each memory block 109 are connected to individual column sense amplifiers 1.
10 and is selectively driven.

Further, 130 is an address buffer, and the output address signal of this address buffer 130 is supplied to each row decoder 120 mentioned above. Further, 140 is a refresh controller, and this refresh controller 1
40 generates a refresh address corresponding to a cell to be refreshed and a signal for a sense amplifier enable line R8E that controls the sense amplifier R8A. Among these, the refresh address is for each row decoder 1 mentioned above.
The sense amplifier enable line R8E is supplied to each column sense amplifier 110. In this RAM, a memory cell group is divided into a plurality of memory blocks 100a, 100b, . . . , and thereby bits It (BL, RBL) are divided into a plurality of parts.

By the way, the power required for refreshing is mainly due to the charging and discharging current of charges in the bit line. Therefore, if the length of the bit line is reduced to 1/n, the capacitances CB and CRB existing on the bit line will also be 1'
/ n. Therefore, the charging/discharging charge of the bit line is CB
-■ or CRB・V (where ■ is the power supply voltage), so
Each - is also 1/n. Therefore, the refresh current is also reduced to 1/n, and for example, when this RAM is backed up by a battery, the battery life can be increased by n times.

In this way, a RAM using cells having the configuration shown in FIG. 1 can be used without worrying about refresh timing at all, and is dynamic.

It can be used as static RAM even though it is small. Furthermore, since data refresh can be performed in parallel in other cells when data is accessed, the access time can be sufficiently shortened compared to the conventional method.

Moreover, compared to the conventional dynamic type, it is necessary to provide one transistor and two extra wires (bit line and word line) within the cell, so the cell area is somewhat larger (although compared to the static type) In this case, the cell area can be made smaller, and a storage capacity more than twice that of a normal static RAM can be realized.

It goes without saying that this invention is not limited to the above-mentioned embodiment, and that various modifications are possible. For example, in the embodiment described above, one memory cell MC includes a chavash capacitor C8 and two transfer gate MoS transistors Q1. Although the case has been described in which the device is equipped with Q2, this may also be configured as shown in FIG. This cell is made up of four Mos transistors Qll to Ql4, and has a memory cell with a four-transistor configuration that stores complementary data, and a bit line RBL for data refresh at points Ml and M2, which serve as information storage points. , RBL, and a transfer gate MoS transistor Q15.016 for data refresh is newly inserted between them.

Further, in the above embodiment, only data reading was explained as an example of data access, but it goes without saying that data writing can be performed using a data writing circuit (not shown).

Furthermore, in the memory cell shown in FIG. 1 above, one transistor Q1 and the bit line 8m are used for data access,
Although the case where the other transistor Q2 and bit line RBL are used for data refresh has been described, the transistor Q2 and bit line RBL may also be used for data access.

[Effects of the Invention] As described above, according to the present invention, it is possible to provide a semiconductor memory device that does not require consideration of refresh timing and can also sufficiently shorten access time.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram showing the configuration of one memory cell of a semiconductor memory device according to the present invention, FIG. 2 is a diagram showing a dynamic RAM configured using a plurality of memory cells having the configuration shown in FIG. 1, and FIG. Figure 3 is a circuit diagram showing the configuration of the sense amplifier of the dynamic RAM described above, Figure 4 is a timing chart showing the operation of the RAM in Figure 2, and Figure 5 is a diagram showing how the RAM in Figure 2 is actually integrated into an integrated circuit. FIG. 6 is a block diagram showing the structure of a RAM according to an application example of the present invention; FIG. 7 is a circuit diagram showing the structure of another memory cell of the semiconductor memory device according to the present invention; FIG. Figure 8 is a circuit diagram showing the configuration of a conventional dynamic RAM, the ninth factor is a timing chart when refreshing is performed periodically in this conventional RAM, and Figure 10 is a timing chart showing the operation of the conventional RAM described above. . MC...Memory cell, CB...Capacitor, M...
・Data storage node, Ql... MO for data access
S transistor, Q2...M for data refresh
oS transistor, BL, RBL...bit line, WL
, JgRJ9L...Word line, SA, R8A...Sense amplifier, OUT...Output circuit. Applicant's agent Patent attorney Takehiko Suzue Figure 1 Figure 2 CD uut B SE Figure 4 Figure 5 Figure 7 Figure 8 CD DL 0LJT Figure 9 Figure 10 il! I out

Claims (4)

[Claims] (1) between an information storage node that dynamically stores information, first and second bit lines, first and second selection lines, and between the information storage node and the first bit line; A first MOS for a transfer gate, which is inserted between the source and the drain, and whose gate is connected to the first selection line.
and a second MOS transistor for a transfer gate, the source and the drain of which are inserted between the information storage node and the second bit line, and the gate of which is connected to the second selection line. A semiconductor memory device characterized by: (2) Information storage nodes that dynamically accumulate information;
first and second bit lines, first and second selection lines,
a first MOS transistor for a transfer gate whose source and drain are inserted between the information storage node and the first bit line, and whose gate is connected to the first selection line; A second MO for a transfer gate, which has a source and a drain inserted between the second bit line and a gate connected to the second selection line.
a memory cell composed of an S transistor; a sense amplifier for data access coupled to the first bit line;
A semiconductor memory device comprising: a sense amplifier for data refresh coupled to the second bit line. (3) The first bit line and selection line are configured to be used during normal information access operations, and the second bit line and selection line are used during information refresh operations of the information storage node. A semiconductor memory device according to claim 1 or 2. (4) The semiconductor memory device according to claim 1 or 2, wherein each of the first and second bit lines is divided into a plurality of parts.