JPS60165742A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPS60165742A
JPS60165742A JP59020002A JP2000284A JPS60165742A JP S60165742 A JPS60165742 A JP S60165742A JP 59020002 A JP59020002 A JP 59020002A JP 2000284 A JP2000284 A JP 2000284A JP S60165742 A JPS60165742 A JP S60165742A
Authority
JP
Japan
Prior art keywords
dam
base
resin
pellet
semiconductor device
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP59020002A
Other languages
Japanese (ja)
Inventor
Junichi Suzuki
順一 鈴木
Atsushi Honda
厚 本多
Takashi Miwa
孝志 三輪
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Renesas Eastern Japan Semiconductor Inc
Original Assignee
Hitachi Tokyo Electronics Co Ltd
Hitachi Ltd
Hitachi Ome Electronic Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Tokyo Electronics Co Ltd, Hitachi Ltd, Hitachi Ome Electronic Co Ltd filed Critical Hitachi Tokyo Electronics Co Ltd
Priority to JP59020002A priority Critical patent/JPS60165742A/en
Publication of JPS60165742A publication Critical patent/JPS60165742A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/16—Fillings or auxiliary members in containers or encapsulations, e.g. centering rings
    • H01L23/18—Fillings characterised by the material, its physical or chemical properties, or its arrangement within the complete device
    • H01L23/24—Fillings characterised by the material, its physical or chemical properties, or its arrangement within the complete device solid or gel at the normal operating temperature of the device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/74—Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies
    • H01L24/78—Apparatus for connecting with wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45117—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/45124—Aluminium (Al) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H01L2224/49175—Parallel arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/74—Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies and for methods related thereto
    • H01L2224/78—Apparatus for connecting with wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/74—Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies and for methods related thereto
    • H01L2224/78—Apparatus for connecting with wire connectors
    • H01L2224/7825—Means for applying energy, e.g. heating means
    • H01L2224/783—Means for applying energy, e.g. heating means by means of pressure
    • H01L2224/78313—Wedge
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01013—Aluminum [Al]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01014—Silicon [Si]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01047—Silver [Ag]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/1015—Shape
    • H01L2924/1016—Shape being a cuboid
    • H01L2924/10162—Shape being a cuboid with a square active surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/161—Cap
    • H01L2924/1615—Shape
    • H01L2924/16152—Cap comprising a cavity for hosting the device, e.g. U-shaped cap

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Chemical & Material Sciences (AREA)
  • Dispersion Chemistry (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Wire Bonding (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)

Abstract

PURPOSE:To facilitate supersonic bonding and to prevend a sealing resin form overriding a dam by providing a step or a slope inside the dam when securing a semiconductor pellet onto an insulating base, surrounding it with a dam. CONSTITUTION:A wiring pattern 10A is coated while facing a semiconductor pellet 11 secured onto a base 10 made of glass epoxy resin, and the end is extended to the end of the back surface of the base 10. Then, the pellet 11 is secured onto the base with a silver brazing material 11A, and wiring electrodes provided at the element are connected with a pattern 10A by aluminum wirings 11B. Then, when a dam 12 which contains gel silicon resin 14 is provided while surrounding the pellet 11 and the wirings 11B, a step or a slope is formed inside the dam 12. Thus, supersonic bonding can be facilitated, and the resin does not override the dam. Then, the dam 12 and the cavity 15A of the inside of the dam are coated with a cap 15.

Description

【発明の詳細な説明】 〔技術分野〕 本発明は、半導体装置に適用して有効な技術に関するも
のであり、特に、封止部材で封止する半導体装置に適用
して有効な技術に関するものである。[Detailed Description of the Invention] [Technical Field] The present invention relates to a technique that is effective when applied to a semiconductor device, and particularly to a technique that is effective when applied to a semiconductor device that is sealed with a sealing member. be.

〔背景技術〕[Background technology]

封止部材（以下、レジンという）で封止する半導体装置
（以下、封止型半導体！ＪＪ［という）の−例として、
第１図の一部切欠き平面図および第１図のＩ−１切断線
における断面図である第２図に示す構造のものが考えら
れ、る。すなわち１、配線パターンＩ　Ａ　ｌ）＜施さ
れ、かつ、それとボンディングワイヤ２を介して電気的
に接続された半導体素子（以下、ペレットという）３が
装着された基板（以下、ベースという）ｌと、ペレット
３およびボンディングワイヤ２を封止する１ノジン４を
保持するために、ペレット３の部分を囲むように配線パ
ターン１Ａを介し、てベースｌ上に設けられたダム５と
、そのダム５を収納するためにザグリによってキャビテ
ィ部６を構成し・、ベース１の端部周辺において接合し
て設けられたキャップ７とによって構成している。そし
てベースｌとダム５およびベースｌとキャップ７は有機
物系等の接着剤によって、配線パターンＩＡにより生じ
る段差部を埋込み、かつ、気密性を保持するように接合
している。As an example of a semiconductor device (hereinafter referred to as a sealed semiconductor!JJ) that is sealed with a sealing member (hereinafter referred to as resin),
A structure shown in FIG. 2, which is a partially cutaway plan view of FIG. 1 and a cross-sectional view taken along the line I-1 in FIG. 1, can be considered. In other words, 1. A substrate (hereinafter referred to as base) l on which a semiconductor element (hereinafter referred to as pellet) 3 is mounted, which is electrically connected to the wiring pattern IA1) through bonding wire 2. In order to hold the nozzle 4 that seals the pellet 3 and the bonding wire 2, a dam 5 provided on the base 1 is connected via the wiring pattern 1A so as to surround the pellet 3. A cavity portion 6 is formed by a counterbore for storage, and a cap 7 is formed by joining around the end of the base 1. The base 1 and the dam 5, and the base 1 and the cap 7 are bonded using an organic adhesive or the like so as to bury the stepped portion caused by the wiring pattern IA and maintain airtightness.

本発明者は、かかる技術における封止型半導体装口の；
ノジンポソ子イングー■−程において、レジン４がレジ
ンポツティング後の搬送時のゆれ等によｌｌダム５を越
えてしまい、所定の１ノジン４鼠より減少し、ペレット
３およびボンディングワイヤ２がキャビティ部６内に機
部に存在する空気と接触するため、それらが腐食し、半
導体装置の信頼性を低下させるという問題点を発見した
。The present inventor has developed a sealed semiconductor package using such technology;
During the nozzle insertion process, the resin 4 exceeds the dam 5 due to shaking during transportation after resin potting, and the resin 4 is reduced to less than the predetermined number of 1 nozzle 4, and the pellet 3 and bonding wire 2 fall into the cavity. The inventor discovered a problem in that the semiconductor devices 6 come into contact with the air present in the machine, causing corrosion and reducing the reliability of the semiconductor device.

また、前記レジン４のダム５越えによりキャップ７の取
り付は不良が発生するという問題点を発見した。In addition, a problem was discovered in that the cap 7 was improperly attached due to the resin 4 exceeding the dam 5.

〔発明の目的〕[Purpose of the invention]

本発明の目的は、封止型半導体装置において、レジンボ
ッティング工程時等における１ノジンのダム越えを防止
することが可能な技術を提供することにある。An object of the present invention is to provide a technique that can prevent one nozzle from exceeding a dam during a resin botting process in a sealed semiconductor device.

本発明の他の目的は、超音波ボンディングが可能であり
、かつ、レジンポツティング工程時等におけるレジンの
ダム越えを防止することが可能な技術を提供することに
ある。Another object of the present invention is to provide a technique that enables ultrasonic bonding and prevents the resin from crossing over the dam during the resin potting process.

本発明の前記ならびにその他の目的と新規な特徴は、本
明細書の記述及び添付図面によって明ら３− かになるであろう。The above and other objects and novel features of the present invention will become clear from the description of this specification and the accompanying drawings.

「発明の（１１（要〕 本願に１昌）で開示される発明のうち、代表的なものの
概要を簡ｍに説明すれば、下記のとおりである。Among the inventions disclosed in Section 11 (Required) of the present application, a brief summary of typical inventions is as follows.

すなわち、封止型半導体装置において、ベーストにＩノ
ジンの流出を防止するために設けられたダムの内側に、
段差又は傾斜を形成することにより、超音波ボンディン
グが可能であり、かつ、レジンポツティング工程時等に
おけるレジンのダム越えを防止し、その半導体装置の信
頼性の向上とレジンボッティング工程時における歩留を
向上するものである。That is, in a sealed semiconductor device, inside a dam provided to prevent I-nozzle from flowing out to the base,
By forming steps or slopes, ultrasonic bonding is possible, and it also prevents the resin from going over the dam during the resin potting process, improving the reliability of the semiconductor device and reducing steps during the resin potting process. It improves retention.

〔実施例〕〔Example〕

以下、本発明の構成について、実施例とともに説明する
。Hereinafter, the configuration of the present invention will be explained along with examples.

第３図は、本発明の詳細な説明するための封１に型半導
体装置の一部明欠き平面図、第４図は、第３図のＩＩ　
−ｍ切断線における断面図である。FIG. 3 is a partially cut-out plan view of a seal 1 type semiconductor device for explaining the present invention in detail, and FIG.
It is a sectional view taken along the -m cutting line.

なよ？、実施例を示す全図において、同一機能を　Ｌ 有するものは同一符号を付け、その繰り返しの説明は省
略する。No yo? , In all the figures showing the embodiments, parts having the same functions are denoted by the same reference numerals, and repeated explanations thereof will be omitted.

第３図及び第４図において、ｌＯはベースであり、例え
ば、ガラスエポキシ樹脂、セラミック等の材料からなっ
ている。ＩＯＡはベースｌＯの表面に設けられた配線パ
ターンであり、後述するペレットと封止型半導体装置の
外部装置とを電気的に接続するためのものである。この
配線パターン１０Ａは、例えば、５０乃至１００［ｚｔ
ｒｎ］程度の膜厚で蒸着形成し導電性材料を用いればよ
い。In FIGS. 3 and 4, IO is a base, which is made of a material such as glass epoxy resin or ceramic. The IOA is a wiring pattern provided on the surface of the base IO, and is used to electrically connect the pellet described later to an external device of the sealed semiconductor device. This wiring pattern 10A has, for example, 50 to 100 [zt
The conductive material may be formed by vapor deposition to a film thickness of about rn].

または、導電性材料をｔｉｔに付着して形成してもよい
。１１は銀ろう等の接着部材１１Ａを介してベースｌＯ
の中央部に設けられたペレットである。Alternatively, a conductive material may be attached to the tit. 11 is a base lO via an adhesive member 11A such as silver solder.
It is a pellet provided in the center of the.

１１Ｂはボンディングワイヤであり、アルミニウムＣＡ
Ｑ）又はアルミニウム合金を用いればよい。11B is a bonding wire, made of aluminum CA
Q) Or an aluminum alloy may be used.

このボンディングワイヤＩＩＢは、配線パターン１０Ａ
の所定部分とペレット１１の所定部分とを電気的に接続
するものである。１２はダムであり、ペレット１１部お
よびボンディングワイヤ１１１３部を囲むように、配線
パターンＩＯＡを介してベースｌＯの表面に有機物系等
の接着剤１３によって気密に接着されている。このダム
１２の内側は、第５図に示すように、段差１２Ａを付け
である。This bonding wire IIB is connected to wiring pattern 10A.
A predetermined portion of the pellet 11 is electrically connected to a predetermined portion of the pellet 11. A dam 12 is hermetically bonded to the surface of the base IO via the wiring pattern IOA with an organic adhesive 13 so as to surround the pellet 11 and the bonding wire 1113. The inside of this dam 12 is provided with a step 12A, as shown in FIG.

また、第６図に示すように、傾斜面１２Ｂを付けてもよ
い。該ダム１２の高さは、アルミニウムのボンディング
ワイヤＩＩＢの供給経路が超音波ボンディングするため
のウェッジｌｌＣの被供給穴に挿入する角度で制限され
るため、所定の高さより高くすることができない。そこ
で、ダム１２の囲む面積を拡大してダム１２の高さを高
くすることにより後述するレジンのダム越えを防止する
ことはできるが、レジンを多く使用することになる。Further, as shown in FIG. 6, an inclined surface 12B may be provided. The height of the dam 12 cannot be made higher than a predetermined height because it is limited by the angle at which the aluminum bonding wire IIB is inserted into the supply hole of the wedge IIIC for ultrasonic bonding. Therefore, by enlarging the area surrounded by the dam 12 and increasing the height of the dam 12, it is possible to prevent the resin from exceeding the dam, which will be described later, but a large amount of resin will be used.

そこで、前述のように、ダム１２の内側を段差１２Ａ又
は傾斜面１２Ｂにすることによってレジンを節約するこ
とができる。また、前記段差１２Ａの高さ、又は傾斜面
１２Ｂの傾きは、前記ボンディングワイヤ１１　Ｂの経
路によって制限される。Therefore, as described above, resin can be saved by making the inside of the dam 12 a step 12A or an inclined surface 12B. Further, the height of the step 12A or the inclination of the inclined surface 12B is limited by the path of the bonding wire 11B.

また、レジンのダム越えの防止によって後述するキャッ
プ付は不良を防止することができる。Further, by preventing the resin from crossing over the dam, it is possible to prevent defects when attaching a cap, which will be described later.

１４はベースｌＯ及びダム１２によって構成されるキャ
ビティ内に注入されたゲル状シリコン樹脂等のであり、
前述のようにダム１２とベースＩＯとは接着剤１３によ
って気密性が保持されているので、その里が変動するこ
とがない。また、熱サイクルによりボンディングワイヤ
と剥離することがなく、アルミニウムワイヤの腐食を防
止する。14 is a gel-like silicone resin or the like injected into the cavity formed by the base lO and the dam 12;
As mentioned above, since the dam 12 and the base IO are kept airtight by the adhesive 13, the distance between the dam 12 and the base IO will not change. Furthermore, it does not separate from the bonding wire due to thermal cycles, and prevents corrosion of the aluminum wire.

すなわち、その歩留は向−ヒされ、信頼性の高い封止型
半導体装置を得ることができる。１５はキャップであり
、ダム１２を収納するためにザグリによってキャビティ
部１５Ａを構成し、ベースｌＯの端部周辺において有機
物系接着剤１３によって接合されている。That is, the yield is improved and a highly reliable sealed semiconductor device can be obtained. A cap 15 forms a cavity 15A with a counterbore to accommodate the dam 12, and is bonded around the end of the base 10 with an organic adhesive 13.

〔効果〕〔effect〕

封止型半導体装置において、ダムの内側を所定の高さの
段差又は傾斜面にすることにより、超音波ボンディング
が可能で、かつ、レジンのダム越えを防止することがで
きる。In a sealed semiconductor device, by forming a step or an inclined surface of a predetermined height on the inside of the dam, ultrasonic bonding is possible and resin can be prevented from going over the dam.

この結果、次のような効果を得ることができる。As a result, the following effects can be obtained.

（１）レジンボッティング工程の歩留が向−ヒする。(1) The yield of the resin botting process is improved.

（２）レジンの節約ができる。(2) You can save on resin.

（３）キャップ取り付は不良の防止ができる。(3) Cap installation can prevent defects.

（４）信頼性が向上する。(4) Reliability is improved.

以」二、本発明を実施例にもとづき具体的に説明したが
、本発明は前記実施例に限定されるものでなく、その要
旨を逸脱しない範囲で種々変更可能であることはいうま
でもない、Hereinafter, the present invention has been specifically explained based on examples, but it goes without saying that the present invention is not limited to the above-mentioned examples and can be modified in various ways without departing from the gist thereof. ,

【図面の簡単な説明】[Brief explanation of drawings]

第１図及び第２図は１本発明の詳細な説明するための封
止型半導体装置を示す図であり、第１図は、その一部切
欠き平面図、第２図は第１図のＩ−１切断線における断
面図、 第：３図は、本発明の一実施例を説明するための’Ｊ’
ｌ　＋Ｉ−型半導体装置の一部切欠き平面図、第４図は
、第３図のＩＩＩ　−ＩＩＩ　ｇＪ断線における断面図
、 第５図及び第６図は、本発明のダムの実施例を示す図で
ある。 図中、１（）・・・ベース、ＩＯＡ・・・配線パターン
。 １１・・・ペレット、ＩＩＡ・・・接着部材、ＩＩＢ・
・・ボンディングワイヤ、１２・・・ダム、１２Ａ・・
・ダ７− ムの内側段差、１２Ｂ・・・ダムの内側傾斜面、１３・
・・接着剤、１４・・・ゲル状シリコン樹脂等、１５・
・・キャップ、１５Ａ・・・キャビティ部、である。 ８− 第　１　図 第　２　図 第　３　図 第　４　図 □６ 第　５　図1 and 2 are diagrams showing a sealed semiconductor device for explaining the present invention in detail. FIG. 1 is a partially cutaway plan view of the device, and FIG. A sectional view taken along the I-1 cutting line, Figure 3 is 'J' for explaining one embodiment of the present invention.
FIG. 4 is a cross-sectional view taken along the line III-III gJ in FIG. 3; FIGS. 5 and 6 show embodiments of the dam of the present invention. It is a diagram. In the figure, 1()...Base, IOA...Wiring pattern. 11... Pellet, IIA... Adhesive member, IIB.
...Bonding wire, 12...Dam, 12A...
・Dam 7- Inner step of dam, 12B... Inner slope of dam, 13.
...Adhesive, 14...Gel-like silicone resin, etc., 15.
... Cap, 15A... Cavity part. 8- Figure 1 Figure 2 Figure 3 Figure 4 Figure □6 Figure 5

Claims (1)

【特許請求の範囲】 ■、基板］二にダムを設置し、半導体素子とボンディン
グワイヤを封止部材で封止した半導体装置において、前
記ダムの内側を所定の段差又は傾斜面にしたことを特徴
とする半導体装置。 ２、ボンディングワイヤをアルミニウム又はアルミニウ
ム合金で形成したことを特徴とする特許請求の範囲第１
項記載の半導体装置。[Scope of Claims] (1) A semiconductor device in which a dam is installed on the substrate and the semiconductor element and the bonding wire are sealed with a sealing member, characterized in that the inside of the dam has a predetermined step or slope. semiconductor device. 2. Claim 1, characterized in that the bonding wire is made of aluminum or aluminum alloy.
1. Semiconductor device described in Section 1.
JP59020002A 1984-02-08 1984-02-08 Semiconductor device Pending JPS60165742A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP59020002A JPS60165742A (en) 1984-02-08 1984-02-08 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP59020002A JPS60165742A (en) 1984-02-08 1984-02-08 Semiconductor device

Publications (1)

Publication Number Publication Date
JPS60165742A true JPS60165742A (en) 1985-08-28

Family

ID=12014934

Family Applications (1)

Application Number Title Priority Date Filing Date
JP59020002A Pending JPS60165742A (en) 1984-02-08 1984-02-08 Semiconductor device

Country Status (1)

Country Link
JP (1) JPS60165742A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0372640A (en) * 1989-08-11 1991-03-27 Fujitsu Ltd Semiconductor device
US5834830A (en) * 1995-12-18 1998-11-10 Lg Semicon Co., Ltd. LOC (lead on chip) package and fabricating method thereof
WO2005001929A1 (en) * 2003-06-30 2005-01-06 Robert Bosch Gmbh Structural unit comprising a tub-type housing part and casting material arranged therein

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0372640A (en) * 1989-08-11 1991-03-27 Fujitsu Ltd Semiconductor device
US5834830A (en) * 1995-12-18 1998-11-10 Lg Semicon Co., Ltd. LOC (lead on chip) package and fabricating method thereof
WO2005001929A1 (en) * 2003-06-30 2005-01-06 Robert Bosch Gmbh Structural unit comprising a tub-type housing part and casting material arranged therein

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