JPS60107121A - Semiconductor integrated circuit device - Google Patents
Semiconductor integrated circuit deviceInfo
- Publication number
- JPS60107121A JPS60107121A JP58216771A JP21677183A JPS60107121A JP S60107121 A JPS60107121 A JP S60107121A JP 58216771 A JP58216771 A JP 58216771A JP 21677183 A JP21677183 A JP 21677183A JP S60107121 A JPS60107121 A JP S60107121A
- Authority
- JP
- Japan
- Prior art keywords
- power supply
- integrated circuit
- voltage
- control signal
- circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
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- Direct Current Feeding And Distribution (AREA)
- Logic Circuits (AREA)
- Power Sources (AREA)
Abstract
Description
【発明の詳細な説明】
〔発明の技術分野〕
この発明は、高電圧動作と低電圧動作の２つの動作モー
ドを有するＣ−ＭＯＳマイクロコンピュータ等の半導体
集積回路において、低電圧動作から高電圧動作への遷移
時における半導体集積回路の論理誤動作をなくするよう
にした半導体集積回路装置に関するものである。Detailed Description of the Invention [Technical Field of the Invention] The present invention relates to a semiconductor integrated circuit such as a C-MOS microcomputer that has two operating modes, high-voltage operation and low-voltage operation. The present invention relates to a semiconductor integrated circuit device that eliminates logical malfunctions of a semiconductor integrated circuit during transition to .
マイクロコンピュータ等の半導体集積回路において、低
電圧動作（いわゆるＨＡＬＴｔ７３１能）と高電圧動作
の２種類の動作を実行する装置として、従来第１図に示
すものがあった。図において、１は集積回路（ＬＳＩ）
、２はＤＣ−ＤＣコンバータ、３は電池、４，５ばダイ
オード、６は電源制御信号、１４はインバータ、７ばＤ
（、−ＤＣコンバータ２の制御信号、８はＤＣ−ＤＣコ
ンバータ２の出力、９は集積回路１の電源端子、１０は
集積回路１及びＤＣ−ＤＣコンバータ２のグランド端子
である。2. Description of the Related Art In semiconductor integrated circuits such as microcomputers, there has conventionally been a device shown in FIG. 1 that performs two types of operations: low voltage operation (so-called HALTt731 function) and high voltage operation. In the figure, 1 is an integrated circuit (LSI)
, 2 is a DC-DC converter, 3 is a battery, 4 and 5 are diodes, 6 is a power supply control signal, 14 is an inverter, 7 is a D
(, - the control signal of the DC converter 2, 8 is the output of the DC-DC converter 2, 9 is the power supply terminal of the integrated circuit 1, and 10 is the ground terminal of the integrated circuit 1 and the DC-DC converter 2.
次に動作について説明する。Next, the operation will be explained.
まず、集積回路１が様々な処理を実行している時、ＤＣ
−ＤＣコンバーク２はオン状態であり、電源端子９に向
けて集積回路１の定格電圧が出力される。この定格電圧
値を例えば５ｖと仮定する。First, when the integrated circuit 1 is executing various processes, the DC
- The DC converter 2 is in an on state, and the rated voltage of the integrated circuit 1 is output toward the power supply terminal 9. Assume that this rated voltage value is, for example, 5V.
このように集積回路１は通常は５■で高電圧動作を行な
っているが、処理がすべて終了し、内部のデータのみを
保持したい時、集積回路１は電源制御信号６をｕ１゛に
することにより、ＤＣ，−ＤＣコンバータ制御信号７を
“０″として、ＤＣ−ＤＣコンバータ２をオフ状態とす
る。するとＤＣ−ＤＣコンバータ出力８が０■となるた
め、電源端子９には電池３からの電圧が供給され、集積
回路１は低電圧動作を実行する。この時の電池３の電圧
値は例えば１．５Ｖである。In this way, the integrated circuit 1 normally performs high voltage operation at 5■, but when all processing is completed and only the internal data is desired to be retained, the integrated circuit 1 sets the power supply control signal 6 to u1'. As a result, the DC, -DC converter control signal 7 is set to "0", and the DC-DC converter 2 is turned off. Then, since the DC-DC converter output 8 becomes 0■, the voltage from the battery 3 is supplied to the power supply terminal 9, and the integrated circuit 1 performs a low voltage operation. The voltage value of the battery 3 at this time is, for example, 1.5V.
以上のような動作はＣ−ＭＯＳマイクロコンピュータ等
で一般的な動作であり、消費電力をより低減させる目的
で上記低電圧動作への切換えを行なうものである。The operation described above is a common operation in C-MOS microcomputers and the like, and the switching to the low voltage operation is performed in order to further reduce power consumption.
次に、集積回路」が何らかの処理を・実行したいと判断
した時には、電源制御信号６を０”にすることにより、
ＤＣ−ＤＣコンバータ２をオン状態とし、この時電源端
子９には高電圧５．０Ｖが供給される。Next, when the integrated circuit determines that it wants to perform some kind of processing, it sets the power supply control signal 6 to 0.
The DC-DC converter 2 is turned on, and at this time, a high voltage of 5.0V is supplied to the power supply terminal 9.
従来の半導体集積回路装置は以上の様に構成されており
、ＤＣ−ＤＣコンバーク２より電源が供給されている時
には、負荷の大小により電源電圧の立上り速度が決る。The conventional semiconductor integrated circuit device is constructed as described above, and when power is supplied from the DC-DC converter 2, the rise speed of the power supply voltage is determined by the size of the load.
ところで、（、−ＭＯＳ Ｌｓｒ等の負荷は小さい為、
瞬時に電源電圧が立上ってしまい、ＬＳＩ内部の論理回
路の応答が追従できない場合、論理回路の誤動作を誘起
するという欠点があった。そこでこのような論理回路の
誤動作をなくするために、電源回路に抵抗や容量を付加
して電源電圧の立上り特性を充分大きくなまらせねばな
らなかった。By the way, since the load on (,-MOS Lsr, etc.) is small,
There is a drawback that if the power supply voltage rises instantaneously and the response of the logic circuit inside the LSI cannot follow it, the logic circuit may malfunction. In order to eliminate such malfunctions of logic circuits, it has been necessary to add resistance and capacitance to the power supply circuit to sufficiently blunt the rise characteristics of the power supply voltage.
この発明は上記のような従来のものの欠点を除去するた
めになされたもので、半導体集積回路が低電圧動作から
高電圧動作に移行するとき、該集積回路より出力される
電源制御信号を該集積回路内の電源立上り速度の遅い論
理回路の立上り特性に応じてオンオフ制御することによ
り、外部回路を付加することなく、電源電圧の立上り特
性を集積回路内の各論理回路が充分追従できる程度にな
まらせることができる半導体集積回路装置を提供するこ
とを目的としている。This invention was made to eliminate the drawbacks of the conventional ones as described above, and when a semiconductor integrated circuit transitions from low voltage operation to high voltage operation, the power control signal output from the integrated circuit is transferred to the integrated circuit. By controlling on/off according to the rise characteristics of logic circuits with slow power supply rise speeds in the circuit, it is possible to make the rise characteristics of the power supply voltage smooth to the extent that each logic circuit in the integrated circuit can sufficiently follow the rise characteristics of the power supply voltage without adding an external circuit. The object of the present invention is to provide a semiconductor integrated circuit device that can be used in a variety of ways.
以下、この発明の一実施例を図について説明する。第２
図において、■は集積回路（ＬＳＩ）、２はＤＣ−ＤＣ
コ７バータ、３は電池、４，５はダイオード、６は電源
制御信号、７は電池３の電圧１．５Ｖを電圧変換して５
ｖを得るＤＣ−ＤＣコンバータ２の制御信号、８はＤＣ
，−ＤＣコンバータ２の出力、９は集積回路１の電源端
子、１ｏは集積回路１及びＤＣ−ＤＣコンバータ２のグ
ランド端子である。また２０は低電圧動作から高電圧動
作への遷移時に上記集積回路１がら出力される電源制御
信号６をこの集積回路１内の応答速度の遅い論理回路の
電源立上り特性に応じて制御する電源制御信号制御回路
であり、該電源制御信号制御回路２０は、ＰチャネルＭ
Ｏ３）ランジスタ１１、該トランジスタ１１と直列接続
されたコンデンサ１３、上記ト・ランジスタ１１とコン
デンサ１３との接続点電位を電源電圧に応じて変化する
それ自身のしきい値でもって比較判定するインバータ１
４、該インバータ１４出力及び上記電源制御信号６が入
力される２人力ＮＯＲ回路１５からなる。An embodiment of the present invention will be described below with reference to the drawings. Second
In the figure, ■ is an integrated circuit (LSI), and 2 is a DC-DC
converter 7, 3 is a battery, 4 and 5 are diodes, 6 is a power supply control signal, 7 is a voltage converter of the voltage 1.5V of battery 3, and 5
Control signal of DC-DC converter 2 to obtain v, 8 is DC
, - the output of the DC converter 2, 9 is the power supply terminal of the integrated circuit 1, and 1o is the ground terminal of the integrated circuit 1 and the DC-DC converter 2. Further, 20 is a power supply control for controlling a power supply control signal 6 outputted from the integrated circuit 1 at the time of transition from low voltage operation to high voltage operation according to the power supply start-up characteristics of the logic circuit with a slow response speed within this integrated circuit 1. The power supply control signal control circuit 20 is a signal control circuit, and the power supply control signal control circuit 20 is a P-channel M
O3) A transistor 11, a capacitor 13 connected in series with the transistor 11, and an inverter 1 that compares and determines the potential at the connection point between the transistor 11 and the capacitor 13 using its own threshold value that changes according to the power supply voltage.
4. It consists of a two-man powered NOR circuit 15 into which the output of the inverter 14 and the power supply control signal 6 are input.
次に動作について説明する。Next, the operation will be explained.
集積回路１が、低電圧動作から高電圧動作に遷移する時
、まず電源制御信号６を“０”とする。When the integrated circuit 1 transitions from low voltage operation to high voltage operation, first the power supply control signal 6 is set to "0".
この時ＰチャネルＭＯ３）ランジスタ１１はゲーｌ−電
極がアース電位Ｖｓｓに接続されているのでオン状態で
あり、信号１２は“１”となる。従ってインバータ］４
の出力は０″となり、ＮＯＲ回路１５の２つの入力が共
にパ″０”であるので、ＤＣ−ＤＣコンハーク制御信号
７は“１″となり、ＤＣ−ＤＣコンバータ２はオン状態
となる。その結果築積回路１の電源端子９の電圧値が電
池電圧１．５ＶからＤＣ−ＤＣコンバータ２の出力電圧
５゜０■へと増加し、これに伴ってインバータ１４のし
きい値も上昇するが、この電源電圧の立上り特性が早く
て、ＰチャネルＭＯ３）ランジスタ１１によるコンデン
サ１３への電荷供給の速度が遅い場合、コンデンサ１３
の電圧がインバータ１４のしきい値に追いつくのが遅く
なるため、インバータ１４は信号１２を０”と判定して
その出力は１”となる。従ってＤＣ−ＤＣコンバータ制
御信号７は“０″となってＤＣ−ＤＣコンバータ２はオ
フ状態となり、電源９の電圧値はその時点で増加を停止
する。次に、このように電圧増加が停止したので、Ｐチ
ャネルＭＯＳトランジスタ１１によってコンデンサ１３
は充分充電されてインバータ１４の出力は０″となり、
ＤＣ−ＤＣコンバータ制御信号７が“１”、即ちＤ（＞
ＤＣコンバータ２はオン状態となり、電源端子９の電圧
値は再び増加する。この動作を５■迄繰り返すことによ
りＤＣ−ＤＣコンバータ２の立上り特性を、通常の急峻
な立」−り特性と異なり、ＰチャネルＭＯＳトランジス
タ１１とコンデンサ１３とで定義される充電量」二り特
性に一致させることが可能となる。At this time, the P-channel MO3) transistor 11 is in an on state because its gate electrode is connected to the ground potential Vss, and the signal 12 becomes "1". Therefore, the inverter]4
Since the output of is 0'' and the two inputs of the NOR circuit 15 are both 0, the DC-DC converter control signal 7 is 1, and the DC-DC converter 2 is turned on. The voltage value of the power supply terminal 9 of the building circuit 1 increases from the battery voltage of 1.5V to the output voltage of the DC-DC converter 2 of 5°0■, and the threshold of the inverter 14 also rises accordingly. If the rise characteristic of this power supply voltage is fast and the speed of charge supply to the capacitor 13 by the P-channel MO3) transistor 11 is slow, the capacitor 13
Since the voltage of the inverter 14 catches up with the threshold value of the inverter 14 slowly, the inverter 14 determines the signal 12 to be 0'' and its output becomes 1''. Therefore, the DC-DC converter control signal 7 becomes "0", the DC-DC converter 2 is turned off, and the voltage value of the power supply 9 stops increasing at that point. Next, since the voltage increase has stopped in this way, the capacitor 13 is
is sufficiently charged and the output of the inverter 14 becomes 0'',
The DC-DC converter control signal 7 is “1”, that is, D(>
The DC converter 2 is turned on, and the voltage value at the power supply terminal 9 increases again. By repeating this operation up to 5 times, the rise characteristic of the DC-DC converter 2 is changed from the normal steep rise characteristic to the charge amount defined by the P-channel MOS transistor 11 and the capacitor 13. It is possible to match the
このように、本実施例ではＰチャネルＭｏｓ＋・ランジ
スク１１とコンデンサ１３とによる充電回路を設け、こ
の充電回路の充電立上り特性を集積回路１内の電源応答
速度の遅い論理回路の立上り特性と同様の特性に設定し
、この充電電圧をインバータで判定するようにしたので
、集積回路の各論理動作を破壊することのない電源立上
り特性を持つ半導体集積回路装置を得ることができる。As described above, in this embodiment, a charging circuit including a P-channel Mos+ transistor 11 and a capacitor 13 is provided, and the charging start-up characteristic of this charging circuit is made similar to the start-up characteristic of a logic circuit with a slow power supply response speed in the integrated circuit 1. Since the charging voltage is determined by the inverter, it is possible to obtain a semiconductor integrated circuit device having a power supply start-up characteristic that does not destroy each logical operation of the integrated circuit.
なお、上記実施例ではコンデンサを集積回路内に内蔵し
たものについて説明したが、電源立上り特性をより大き
くする為にコンデンサを集積回路り■に外付ＬＪするよ
うにしてもよい。In the above embodiment, the capacitor is built into the integrated circuit, but the capacitor may be externally connected to the integrated circuit (LJ) in order to further improve the power supply start-up characteristics.
また、上記実施例では正電源のものを示したが、負電源
であってもよく、このときはＰチャネルＭ○Ｓ ｌラン
ジスタ１１をＮチャネルＭＯ３）ランジスタとすれば良
い。Further, in the above embodiment, a positive power source is shown, but a negative power source may be used. In this case, the P channel M○S1 transistor 11 may be replaced with an N channel MO3) transistor.
１以−にのように、本発明によれば、半導体集積回路が
低電圧動作から高電圧動作に移行するとき、該集積回路
より出力される電源制御信号を該集積回路内の電源立上
り速度の遅い論理回路の立上り特性に応して制御するよ
うにしたので、外部回路を設けることなく、電源立上り
時に安定した論理回路動作が可能となる９ＪＪ果がある
。As described above, according to the present invention, when a semiconductor integrated circuit transitions from low voltage operation to high voltage operation, the power supply control signal output from the integrated circuit is adjusted to match the power supply rise speed within the integrated circuit. Since the control is performed in accordance with the slow rise characteristics of the logic circuit, there is a 9JJ effect that allows stable logic circuit operation at power-up without providing an external circuit.
第１図は従来の半導体集積回路装置を示す回路図、第２
図は本発明の一実施例による半導体集積回路装置を示す
回路図である。
１・・・半導体集積回路、２・・・ＤＣ−ＤＣコンバー
タ、３・・・電池、４．５・・・ダイオード、６・・・
電源制御信号、７・・・ＤＣ−ＤＣコンバータ制御信号
、８・・・ＤＣ−ＤＣコンバーク出力、２０・・・電源
制御信号制御回路、１１・・・ＰチャネルＭＯ３）ラン
ジスク、１３・・・コンデンサ、１４・・・インバータ
（論理回路）、１５・・・２人力ＮＯＲ回路。
なお図中、同一符号は同−又は相当部分を示す。
代理人 大 岩 増 ｈｉＬ
第１図
５
第２図Figure 1 is a circuit diagram showing a conventional semiconductor integrated circuit device, Figure 2 is a circuit diagram showing a conventional semiconductor integrated circuit device;
The figure is a circuit diagram showing a semiconductor integrated circuit device according to an embodiment of the present invention. DESCRIPTION OF SYMBOLS 1... Semiconductor integrated circuit, 2... DC-DC converter, 3... Battery, 4.5... Diode, 6...
Power supply control signal, 7... DC-DC converter control signal, 8... DC-DC converter output, 20... Power supply control signal control circuit, 11... P channel MO3) Ranjisk, 13... Capacitor , 14... Inverter (logic circuit), 15... 2-manpower NOR circuit. In the drawings, the same reference numerals indicate the same or equivalent parts. Agent Masu Oiwa hiL Figure 1 5 Figure 2
Claims (2)
する半導体集積回路に該集積回路の動作モードに応じて
２種類の電源電圧を供給するようにしてなる半導体集積
回路装置であって、上記半導体集積回路の低電圧動作か
ら高電圧動作への遷移時に該集積回路より出力される電
源制御信号に応して低電圧動作用の電源電圧を電圧変換
して得られる高電圧動作用の電源電圧を出力するＤＣ−
ＤＣコンバータと、上記低電圧動作から高電圧動作への
遷移時に電源電圧の立上りが該集積回路内の立」−り速
度の遅い論理回路の立上り特性よりもゆるやかになるよ
う上記電源制御信号を制御する電源制御信号制御回路と
を備えたことを特徴とする半導体集積回路装置。(1) A semiconductor integrated circuit device configured to supply two types of power supply voltages to a semiconductor integrated circuit having two operating modes of low-voltage operation and high-voltage operation, depending on the operating mode of the integrated circuit, comprising: A power supply for high-voltage operation obtained by converting the power supply voltage for low-voltage operation in accordance with a power supply control signal output from the integrated circuit when the semiconductor integrated circuit transitions from low-voltage operation to high-voltage operation. DC- output voltage
The DC converter and the power supply control signal are controlled so that the rise of the power supply voltage at the time of transition from the low voltage operation to the high voltage operation is slower than the rise characteristic of the logic circuit in the integrated circuit, which has a slow rise speed. 1. A semiconductor integrated circuit device comprising: a power supply control signal control circuit.
路の電源端子とアース間に直列接続されたトランジスタ
とコンデンサからなる充電回路と、上記トランジスタと
コンデンサとの接続点電位を電源電圧に応じて変化する
それ自身のしきい値でもって比較判定するインパークと
、該インバータの出力に応じて上記電源制御信号をオン
オフ制御する２人力ＮＯＲ回路とからなるものであるこ
とを特徴とする特許請求の範囲第１項記載の半導体集積
回路装置。(2) The power supply control signal control circuit controls a charging circuit consisting of a transistor and a capacitor connected in series between the power terminal of the semiconductor integrated circuit and the ground, and a potential at a connection point between the transistor and the capacitor in accordance with the power supply voltage. The invention is characterized in that it is comprised of an impark that makes a comparative judgment using its own threshold value that changes, and a two-man NOR circuit that controls on/off the power supply control signal according to the output of the inverter. A semiconductor integrated circuit device according to scope 1.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP58216771A JPS60107121A (en) | 1983-11-15 | 1983-11-15 | Semiconductor integrated circuit device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP58216771A JPS60107121A (en) | 1983-11-15 | 1983-11-15 | Semiconductor integrated circuit device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS60107121A true JPS60107121A (en) | 1985-06-12 |
Family
ID=16693638
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP58216771A Pending JPS60107121A (en) | 1983-11-15 | 1983-11-15 | Semiconductor integrated circuit device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS60107121A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7376848B2 (en) | 1997-06-27 | 2008-05-20 | Broadcom Corporation | Battery powered device with dynamic power and performance management |
-
1983
- 1983-11-15 JP JP58216771A patent/JPS60107121A/en active Pending
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7376848B2 (en) | 1997-06-27 | 2008-05-20 | Broadcom Corporation | Battery powered device with dynamic power and performance management |
| US7900067B2 (en) | 1997-06-27 | 2011-03-01 | Broadcom Corporation | Battery powered device with dynamic and performance management |
| US8504852B2 (en) | 1997-06-27 | 2013-08-06 | Broadcom Corporation | Battery powered device with dynamic power and performance management |
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