JPS5981724A - Expanding method for address space of dma controller - Google Patents

Expanding method for address space of dma controller

Info

Publication number
JPS5981724A
JPS5981724A JP19182682A JP19182682A JPS5981724A JP S5981724 A JPS5981724 A JP S5981724A JP 19182682 A JP19182682 A JP 19182682A JP 19182682 A JP19182682 A JP 19182682A JP S5981724 A JPS5981724 A JP S5981724A
Authority
JP
Japan
Prior art keywords
address
dma
address space
bits
space
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP19182682A
Other languages
Japanese (ja)
Inventor
Masaki Usami
宇佐美　正樹
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi High Tech Corp
Original Assignee
Hitachi Electronics Engineering Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Electronics Engineering Co Ltd filed Critical Hitachi Electronics Engineering Co Ltd
Priority to JP19182682A priority Critical patent/JPS5981724A/en
Publication of JPS5981724A publication Critical patent/JPS5981724A/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
    • G06F13/28—Handling requests for interconnection or transfer for access to input/output bus using burst mode transfer, e.g. direct memory access DMA, cycle steal

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Bus Control (AREA)

Abstract

PURPOSE:To expand simply a space which is addressed by a DMA (direct memory access) system by latching the high-order bits of an address bus into an address register before the DMA is started and then delivering those bits into the address bus concurrently with actuation of a DMA controller. CONSTITUTION:An MPU1 of 16 bits performs a DMA by means of a DMA controller 3 for 8 bits of an address space 64K through an address bus 2 of 20 bits. An address 5 of high-order 4 bits set by a program is latched to an address register 4. Then the controller 3 generates an address 6 of low-order 16 bits. A system is actuated by a DMA actuation signal 7. The DMA address space can move freely within an address space of 1M of the MPU1 for each 64K in response to the contents of the register 4 set by a program.

Description

【発明の詳細な説明】 〔発明の利用分野〕 本発明は、例えば１６ビツトマイクロプロセツサに、８
ビツト用ＤＭＡ制御装置（ＤＭＡＣ）を組合わせてシス
テムを形成した場合の、ＤＭＡＣアドレス空間拡張方法
に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Application of the Invention] The present invention provides, for example, a 16-bit microprocessor with an 8
The present invention relates to a DMAC address space expansion method when a system is formed by combining bit DMA control devices (DMAC).

〔従来技術〕[Prior art]

メモリアドレス空間をＩＭＭＡト以上までもつ１６ビツ
トのマイクロプロセッサ（ＭＰＵ）を用いたシステムで
Ｄ　ＭＡを行なわせようとする場合、従来は既存の８ビ
ツト用Ｄ　Ｍ　Ａ　Ｃを利用するのが一般的方法であっ
た。しかしこれではＤＭＡ方式でアドレスする空間は最
大６４ｋに限定されて折角１Ｍ以上に拡張されたアドレ
ス空間を有効に活用していることにはならない。しかし
一方ではマイクロコンピュータでＤＭＡを行う場合、６
４にアドレスで十分という考えもある。When attempting to perform DMA in a system using a 16-bit microprocessor (MPU) with a memory address space of IMMA or more, conventionally it was common to use the existing 8-bit DMAC. It was a method. However, in this case, the address space in the DMA method is limited to a maximum of 64K, and the address space, which has been expanded to more than 1M, is not effectively utilized. However, on the other hand, when performing DMA on a microcomputer, 6
Some people think that address 4 is sufficient.

〔発明の目的〕[Purpose of the invention]

本発明の目的は、ＤＭＡＣのアドレス空間以上に大きい
アドレス空間を有するＭＰＵを用いたシステムで、ＤＭ
Ａ方式でアドレスする空間を簡庁に拡張できる方法を提
供することにある。An object of the present invention is to provide a system using an MPU having an address space larger than the address space of the DMAC.
The purpose of this invention is to provide a method by which the space addressed by method A can be expanded to a small office.

〔発明の概要〕[Summary of the invention]

上記目的を達成するために本発明においては、アドレス
バスの上位ピントをプログラムにより任意に設定し、こ
れをＤＭＡ開始に先立ちアドレスレジスタ内にラッチさ
せておいて、ＤＭＡＣ始動と同時にアドレスバス内に出
力させるようにした。In order to achieve the above object, the present invention sets the upper focus of the address bus arbitrarily by a program, latches it in the address register before starting DMA, and outputs it into the address bus at the same time as starting the DMAC. I tried to let him do it.

なお、従来もＤＭＡＣとカウンタを連動させて、ＤＭＡ
Ｃでアドレスする空間を１顯次拶動させることは行なわ
れ、ていたが、これではアドレスの自由度が少なく不便
であった。Note that in the past, the DMAC and the counter were linked, and the DMA
It was previously possible to address the space addressed by C one after another, but this was inconvenient because there was little freedom in addressing.

〔発明の実施例〕[Embodiments of the invention]

第１図は本発明一実施例のブロック図である。 FIG. 1 is a block diagram of one embodiment of the present invention.

図中、１は１６ビツトＭＰＵ、２は２０ビツトアドレス
バス、３はアドレス空間６４にの８ビット用Ｄ＾ｉＣ，
４はアドレスレジスタ、５はプログラムにより設定され
た上位４ビットのアドレス、６はＤＭＡＣ５が発生させ
る下位１６ビツトのアドレス、７はＤＭＡ作動信号であ
る。この様にすれば、プログラムにより設定されるアド
レスレジスタの内容に応じてＤＭＡアドレス空間は６４
に単位で、ＩＭのアドレス空間内を自由に移動できる。In the figure, 1 is a 16-bit MPU, 2 is a 20-bit address bus, 3 is an 8-bit D^iC in the address space 64,
4 is an address register, 5 is an address of the upper 4 bits set by the program, 6 is an address of lower 16 bits generated by the DMAC 5, and 7 is a DMA activation signal. In this way, the DMA address space will be 64 depending on the contents of the address register set by the program.
can be freely moved within the IM address space.

〔発明の効果〕 以上説明したように本発明によれば、ＤＭＡＣのアドレ
ス空間以上に大きいＭＰＵのアドレス空間を、極めて簡
単な付加手段によって有効活用することができる。[Effects of the Invention] As described above, according to the present invention, the address space of the MPU, which is larger than the address space of the DMAC, can be effectively utilized by extremely simple addition means.

【図面の簡単な説明】[Brief explanation of drawings]

第１図は本発明一実施例のブロック図である。 １・・・ＭＰＵ、２・・・アドレスバス、３・・・ＤＭ
ＡＣ。 ４・・・アドレスレジスタ、５・・・上位アドレス、６
・・・下位アドレス。 代理人　弁理士　　縣　　　武　雄FIG. 1 is a block diagram of one embodiment of the present invention. 1...MPU, 2...Address bus, 3...DM
A.C. 4...Address register, 5...Upper address, 6
...lower address. Agent: Takeo Agata, patent attorney

Claims (1)

【特許請求の範囲】[Claims] ＤＭＡ制御装置固有のアドレス空間よりも大きいアドレ
ス空間を有するマイクロプロセッサを用いたシステムに
おいて、アドレスノ（スの上位ビットをプログラム制御
することにより、Ｄ　Ｍ　Ａ制御装置のアドレス空間を
、前記大きいアドレス空間内で任意に移動させるように
したことを特徴とするＤＭＡ制御装置アドレス空間の拡
張方法。In a system using a microprocessor that has an address space larger than the address space specific to the DMA control device, the address space of the DMA control device can be changed to the larger address space by program-controlling the upper bits of the address number. 1. A method for expanding a DMA control device address space, characterized in that the address space of a DMA control device is moved arbitrarily within the DMA control device address space.
JP19182682A 1982-11-02 1982-11-02 Expanding method for address space of dma controller Pending JPS5981724A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP19182682A JPS5981724A (en) 1982-11-02 1982-11-02 Expanding method for address space of dma controller

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP19182682A JPS5981724A (en) 1982-11-02 1982-11-02 Expanding method for address space of dma controller

Publications (1)

Publication Number Publication Date
JPS5981724A true JPS5981724A (en) 1984-05-11

Family

ID=16281159

Family Applications (1)

Application Number Title Priority Date Filing Date
JP19182682A Pending JPS5981724A (en) 1982-11-02 1982-11-02 Expanding method for address space of dma controller

Country Status (1)

Country Link
JP (1) JPS5981724A (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61269760A (en) * 1985-05-24 1986-11-29 Fujitsu Ltd Direct memory access control system
WO2011160721A1 (en) 2010-06-23 2011-12-29 International Business Machines Corporation Resizing address spaces concurrent to accessing the address spaces
US9626298B2 (en) 2010-06-23 2017-04-18 International Business Machines Corporation Translation of input/output addresses to memory addresses
US11326742B2 (en) 2017-07-31 2022-05-10 Fujikin Incorporated Valve

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS49122232A (en) * 1973-03-22 1974-11-22
JPS5358731A (en) * 1976-11-08 1978-05-26 Mitsubishi Electric Corp Memory address extension method

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS49122232A (en) * 1973-03-22 1974-11-22
JPS5358731A (en) * 1976-11-08 1978-05-26 Mitsubishi Electric Corp Memory address extension method

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61269760A (en) * 1985-05-24 1986-11-29 Fujitsu Ltd Direct memory access control system
WO2011160721A1 (en) 2010-06-23 2011-12-29 International Business Machines Corporation Resizing address spaces concurrent to accessing the address spaces
US9626298B2 (en) 2010-06-23 2017-04-18 International Business Machines Corporation Translation of input/output addresses to memory addresses
US11326742B2 (en) 2017-07-31 2022-05-10 Fujikin Incorporated Valve

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