JPS5960645A - System for processing instruction execution of processor - Google Patents

Abstract

PURPOSE:To inhibit an undesired interruption when a series of instructions are executed, by installing a control bit capable of set and reset which executes next instruction in ignoring the existence of a stop or interruption designation, and a processor sequence controlling section. CONSTITUTION:Microinstructions, to which a control bit is installed by one bit, on a control memory 5 are successively fetched by a processor sequence controlling section 2. When, for example, an instruction 2 is fetched by an instruction register 4 in the course of the fetching, the processor sequence controlling section 2 fetches the next instruction 2 without checking on designations, such as interruption designation, etc., because the control bit (C bit) is one (C=1). Since the control bit of the instruction 3 is also one (C=1), next instruction 4 is fetched immediately after the instruction 3 is executed. Since the control bit of the instruction 4 is zero (C=0), the processor sequence controlling section 2 checkes on designations, etc., after executing the instruction 4, and, when no designation exists, fetches next instruction 5.

Description

DETAILED DESCRIPTION OF THE INVENTION 4. Technical Field of the Invention The present invention provides an instruction chain function corresponding to a command chain in a channel in a processor instruction execution processing system, particularly a stored program system processor, and provides an instruction chain function corresponding to a command chain in a channel. The present invention relates to a processor instruction execution processing method that allows instructions and interrupt instructions to be ignored by hardware processing.

However, technical background and problems Conventionally, when an interrupt-7A request is issued while processing is being executed in a stored program type processor, the processor will not respond to the request if the interrupt request has a high priority. A transition is made to processing corresponding to the interrupt.

Although the present invention is not limited thereto, in a microprogram-controlled processor, for example, by executing a series of a plurality of microinstructions, a flag is set, the flag is set, and the next processing is performed. Processing such as executing a process is performed.

When debugging such processing, if the interrupt request occurs during the execution of the series of microinstructions, there is a problem that the debugging becomes difficult. For this reason, it is desirable to disable interrupts until the execution of the series of microinstructions described above is completed, and the interrupt level may be temporarily increased by software for the execution of the series of microinstructions described above. It is also possible to consider 17I1. I can pass. However, in the case of microprogram control, it is not desirable to respond to each interrupt request.

(C) Purpose and structure of the invention The purpose of the present invention is to solve the above-mentioned problems, and its purpose is to prevent the above-mentioned interrupts etc. by hardware when executing the above-mentioned series of instructions. It is said that

Therefore, the processor instruction execution processing method of the present invention is provided with an instruction storage section in which instructions are stored, and the processor sequence control section sequentially fetches instructions from the instruction storage section and uses the instruction execution circuit section to execute the instructions. In response to the execution of the instruction, the system checks the separately given stop instruction and/or interrupt instruction, and as soon as the instruction is given, the process corresponding to the instruction is executed. In a stored program type processor configured to be executed, the control bit is used to indicate that the presence of the above-mentioned stop instruction and/or interrupt instruction is ignored and the next instruction is executed. Piratra sets and / in response to the execution of the above command.
or resettable K11l, and when the control bit exists, the processor sequence control section ignores the presence of the instruction and causes the instruction execution circuit section I to execute the next instruction. It is characterized by being designed to allow The explanation will be given below with reference to the drawings.

Embodiment of the Invention FIGS. 1 and 2 each show the configuration of an embodiment of the present invention, and FIG. 3 shows a flowchart of an embodiment for explaining the operation of the present invention.

In FIG. 1, l is a processor, 2 is a processor or sequence control section, 3 is an instruction execution circuit section, 4 is an instruction register, 5 is a control memory, 6-1. . . . each represents a microinstruction. Further, the C bit shown in the figure corresponds to the control flyer according to the present invention.

In the case of the configuration shown in FIG. 1, the control bits referred to in the present invention are prepared by providing bits on the microcontroller stored in the control memory 5. Needless to say, in the processor 1, the processor sequence control unit 2:
The micro requests 6-1 on the control memory 5 are sequentially fetched. Then, the processor sequence control unit 2 checks whether or not a stop instruction and/or an interrupt instruction has been given, for example, at the point when the instruction has been executed for a long time, and, for example, the interrupt level of the interrupt instruction is If the level is higher than the process currently being executed, the process corresponding to the interrupt instruction is started.

In the case shown in FIG. 1, a control bit is given in the microinstruction, and for example, in the case of C-1, the processor sequence control unit 2 does not check the above-mentioned stop instruction and/or interrupt instruction. The next instruction is fetched and the instruction execution circuit section 3 is made to execute the next instruction. That is, if the instruction ■ shown in the diagram of the younger brother 1 is fetched into the instruction register 4, the control bit is C=
1, the processor sequence control unit 2 fetches the next instruction (2) without checking instructions such as the above-mentioned interrupt instruction.

Also in the instruction (2), the control bit is C=1, and immediately after the instruction (2) is executed, the instruction (7) is etched and executed. In the case of the instruction ■, the control bit is C20, so the processor sequence control unit 2 checks the above-mentioned instructions after the instruction ■ is executed, and if no instructions exist, the next instruction ■'? Have near sex.

The operation during this time is clarified by the chart 70 shown in FIG.

FIG. 2 shows another embodiment, in which reference numerals 1°2, 3.
5.6 corresponds to FIG. 1 and 7 represents the control bit register. In the illustrated embodiment, any instruction example sets the control bit C=1 on the control bit register 7 by the instruction ■, and resets the control bit Yc=o on the register 7 by the instruction ■. The set/reset is performed by an instruction as follows.

By doing this, the illustrated command ■ or command ■
Until this is executed, the processor sequence control unit 2 works to ignore instructions such as the above interrupt instruction (
. The embodiment shown in FIG. 2 has the advantage that the bit width of the instruction is small.

(E) As described in detail, according to the present invention, a series of instructions are chained together as a single group of instructions, and undesired interrupts are prevented from being caused by a node. It is now possible to ban the following.

[Brief explanation of drawings]

1 and 2 each show the configuration of an embodiment of the present invention, and FIG. 3 shows a flowchart of an embodiment for explaining the operation according to the present invention. In the figure, 1 is a processor, 2 is a processor sequence control unit, 3 is an instruction execution circuit unit, 4 is an instruction register, 5 is a control memory, 6 is a microinstruction, 7 is a control bit Φ register, and C is a control bit. . tp! J Patent Attorney Patent Attorney for Applicant Shitsu Co., Ltd. Hiroshi Mori 1) Hiroshi (1 other person)? sE

Claims (1)

[Claims] The processor has an instruction storage section in which instructions are stored, and is configured such that the processor sequence control section sequentially fetches the instructions from the instruction storage section and causes the instruction execution circuit section to execute the instructions, so as to correspond to the execution of the previous instruction. The stored program system is configured to check the separately given stop instruction and/or interrupt instruction, and as soon as the instruction is given, the processing corresponding to the instruction is performed. In the processor, the above stop instruction Syopi/
Alternatively, a control bit is prepared to execute the next instruction in response to the presence of an interrupt instruction, and the control bit is configured to be set and/or reset in response to the execution of the above instruction. , the upper Ma processor sequence control unit ignores the presence of the instruction and causes the instruction execution circuit unit to execute the next instruction when the control bit exists. A characteristic processor instruction execution processing method.