JPS58135667A - Semiconductor device - Google Patents

Abstract

PURPOSE:To expand the space between the electrode end and the fusion point of a dielectric thin film and thus obtain an FET with high gate counter withstand voltage, by using two kinds of dielectric thin film and utilizing the difference of the etching speeds thereof. CONSTITUTION:An SiO2 film 12 and an Si3N4 film 13 are grown on a wafer having an N type GaAs active layer 11 on a semi-insulating GaAs substrate 10, and the Si3N4 13 and the SiO2 12 are etched using a photo resist 14. Next, the Si3N4 13 and the SiO2 12 are etched in a transverse direction using a buffered etchant, and accordingly worked into a form wherein the upper part is narrow and the lower part is wide. By removing the photo resist 14, then evaporating a Schottky forming metal over the wafer entire surface, and finally forming a gate 15 using a photo resist 16, the space between the Schottky metal end A and the fusion point B of the dielectric thin film 12 can be expanded.

Description

[Detailed description of the invention]

The present invention relates to the formation of electrodes for semiconductor devices, and particularly to the formation of electrodes for field effect transistors using gallium arsenide as a semiconductor material. Traveling wave tubes have been the mainstay of high-frequency, high-output amplification elements, but they offer high reliability for communication systems, small size,
As weight reduction is required. Bipolar transistors have been developed for frequencies below 1 Glz, and gallium arsenide field effect transistors have been developed and put into practical use as three-terminal amplification elements for frequencies above that. One way to improve the output per standard gate width of a gallium arsenide field effect transistor is to increase the reverse breakdown voltage of the gate. The reverse breakdown voltage is greatly influenced by the method of forming the key metal (gate protection). How to form a gate zot key gold sn @1
There is a 7-to-7 method that uses the photoresist shown in the figure. That is, a dielectric thin film 2 on an active layer of gallium arsenide is coated with a photoresist 3, and holes are formed in the photoresist 3.

[See Figure 1 for over-etching the dielectric thin film.
ml), Gold w44\It was evaporated from vertically upward for 7 steps to create the Toky gate 4't (Figure (b)), and after L, the P photoresist 3 was removed along with the metal 4 above it by lift-off. (Figure (C)). However, in this lift-off gate formation method using a photoresist tube, the gold@4 must be deposited with the photoresist 3 attached, which limits processing and heating before deposition, and also prevents the gold@4 from being deposited. 7 otore resist 3 while wearing
There is a possibility that gas may come out and contaminate the surface of the gallium arsenide sea urchin/S, and the cage with reverse pressure resistance tends to become unstable. In addition, in another conventional method shown in Fig. @2, an opening r is provided in the dielectric thin film 2 on the gallium arsenide active layer 1 using a photoresist 3 (Fig. 2(a)), and the photoresist 3 is After removing the photoresist (Fig. 2(b)), apply the metal layer 4 to the entire surface to form a glue bond (Fig. 2(b)).
The gate 4' is formed by processing gold 14w using
Figure 2 (C)). In this method, since there is no photoresist attached to the sea urchin/S when metal is deposited, the treatment method before metal deposition can be freely selected. There is no element that makes the reverse breakdown voltage Ik of the gate switch metal 4' unstable, as there is no substance that emits gas at the edge of the metal 4 (point A and Since the breaking points (8 points) of the dielectric thin film 112, which is subject to a single strain, coincide or are very close to each other, the reverse breakdown voltage of the 9-gate 4 formed by the 9-method shown in Figure @2 is low. It is an object of the present invention to provide an aP4 body device having an electrode structure in which the electrode and the end of the dielectric thin film do not come into contact without using the lift-off method. An object of the present invention is to provide a field effect transistor having a high gate reverse breakdown voltage and free from wafer contamination and breakdown voltage instability. In particular, the disadvantage that the cage of p1 reverse voltage becomes unstable is eliminated, and by using two types of cast electric thin film 1[v and taking advantage of the difference in etching speed between them, it is possible to remove the edge of the electrode and the dielectric thin film. It is characterized by widening the distance between the break points.Next, the present invention will be explained in detail using the drawings in an actual row. It is a sectional view showing a manufacturing process 1111 of a gallium arsenide field effect transistor according to an actual example.First, as shown in [@3-), a NWi gallium arsenide active layer is formed on a semi-insulating gallium arsenide substrate 10. Silicon oxide film (8i0.) on the wafer
12 and silicon nitride 11 (SisN4) 13? are each grown to a thickness of 200 OA.Next, in the same figure (as shown in BL, photoresist 14 is used and dry etching is performed using CF4 gas). 8i
sN413(!: sto, t 2 k-!-y?:
//su:b. Next rc, palIN, 1B and 8io with buffer etching solution (hydrofluoric acid: ammonium heptadide - 1 = 6),
12￥It is etched in the horizontal direction. 81. N413
is 8i0 when this buffer art etching solution is used.
, 12, the etching speed is more than two orders of magnitude lower, and as a result, the upper part is narrower and the lower part is wider, as shown in Figure 3 (C) K. Next, the 7 photoresist 14 is removed, and the gold lIi sea urchin I-- layer forming the 7 keys is deposited on the entire surface, and the photoresist 1
6t- is used to form the gate 15.
The basic structure of a gallium arsenide field effect transistor is completed by forming the source 16 and drain 17 ohmic electrodes on both sides of the gate as shown in 6). Gallium Arsenide Field Effect Transistor Co., Ltd. has such a configuration. Since it becomes possible to widen the gate electrode 15, the reverse breakdown voltage of the gate increases, and the output per unit gate width can be improved.Also, since the gate electrode 15 is not used when forming the gate electrode 15, Contamination of the wafer and instability of withstand voltage are also prevented.
Although I, N, and 8i021 were used, any combination of etching speeds that differ by nearly one order of magnitude with respect to an appropriate etching solution can be applied to the present invention. Furthermore, the semiconductor material need not be limited to gallium arsenide either.

[Brief explanation of drawings]

! Figures 1 and 11!2 are cross-sectional views of manufacturing process 1 showing a conventional method for manufacturing a gallium arsenide field effect transistor, and Figure 3 is a cross-sectional view of manufacturing process 1 of a gallium arsenide field effect transistor according to one embodiment of the present invention. It is a sectional view showing J[K. 1...Gallium arsenide active layer, 2...Dielectric thin film, 3.5...Photoresist, 4...
...Gate metal, 4'...Gate electrode,
10... Semi-insulating substrate, 11... Gallium arsenide active layer, 12... SiO, l[, 13
...S'sNa Wls 14-16...
...Photoresist. 15...Gate electrode, 16...Source electrode, 17...Drain electrode. (Ku 2 (a) 1 figure A3 β 7 colors ¥ 2 relationship 3 figures

Claims (1)

[Claims] Two types of dielectric thin films are provided on the semiconductor layer, each dielectric thin film has an opening, the opening provided in the lower dielectric thin film is larger than the opening provided in the upper dielectric thin film, A semiconductor device characterized in that an electrode layer is deposited on a portion of the semiconductor layer exposed through an opening provided in the upper dielectric thin film.