JPS58130494A - Multiport d-randum access memory - Google Patents

Abstract

PURPOSE:To convert a titled RAM to high density, by providing plural transistors, word lines and bit lines on the same storage cell, and providing a means for executing write and read-out simultaneously for plural accesses. CONSTITUTION:A multiport D-RAM has 2 access means of ''0'' and ''1'' port sides, and has word line decoders 10, 10a, word line driving circuits 11, 11a, sense amplifiers 20, 20a and bit line decoders 21, 21a, of ''0'' and ''1'', respectively. When the decoder 10 and the decoder 10a select a word line 40 and a word line 41a, respectively, by plural different accesses, a comparator 30 obtains each bit output as a repeater. When both the decoders execute the same access, the repeater 30 inhibits either one of inputs to obtain a multi-access memory having a small number of input/output connecting lines and a small storage cell area.

Description

DETAILED DESCRIPTION OF THE INVENTION (a) Technical Field of the Invention The present invention relates to a multi-baud D-RAM constructed from semiconductor elements and having a plurality of input/output functions in the same memory cell.

(b) Background of the Technology In ordinary memory circuits, each group has only one set of address means for accessing each address of a memory cell, and even if an attempt is made to simultaneously access different memory areas in the same memory circuit in one group, multiple address means access each address of a memory cell. 7 for each part of the address
11, there was no other option but to wait for the next access until the previous access operation was completed.

(c) Prior Art and Problems This multi-baud RAM, which has a plurality of access means to the same memory circuit, has been conventionally realized as a static RAM.

For example, for the basic circuit of the static RAM shown in FIG. 1(a), the two-bottom static RA shown in FIG. 1(b)
It is configured like M. Static RAM is basically composed of six elements, such as MOS transistors, and has a large number of elements, so the area of each memory cell is large, and there are many word lines, sense lines, power supply lines, ground lines, and input/output connection lines. Therefore, when making this into a multi-port type, it is necessary to add another gate transistor Q3a, Q4a, which increases the area of one memory cell including the number of input/output connection lines, which hinders high density and causes problems. It had some drawbacks.

(d) Object of the Invention The object of the present invention is to eliminate the above-mentioned drawbacks by providing a means for realizing a high-density, multi-board, large-capacity memory using a D-RAM that has a small area per memory cell and a small number of input/output connection lines. This is what we are trying to provide.

(e) Structure and object of the invention The present invention has a dynamic random access memory (D-RAM) that stores information depending on the presence or absence of charge stored in the capacity of the storage cell, in which a plurality of gate transistors and the gate transistors are connected to the same storage cell. It has a word line and a bit line corresponding to the transistor,
This can be achieved by providing a multi-baud D-RAM characterized in that writing and reading are performed simultaneously on different word lines selected by a plurality of word line decoders.

(f) Embodiment of the Invention An embodiment of the present invention will be described below with reference to the drawings. Figure 2 shows multi-baud)D in one embodiment of the present invention.
- Shows a block diagram of RAM. In Figure 2, 10 is 0
Word line decoder +10a is 1 word line decoder, 11
is a 0-word line drive circuit.

Port 4 is a 1-word line drive circuit, 20 is an O sense amplifier, 2
0a is 1 sense amplifier, 21 is O bit line decoder, 2
1a is a 1-bit line decoder, and 30 is a comparator.

31 is a group of 1 bit line selection circuits, 40.41... are 0 word lines H40a+, 41a... are 1 word lines, 50.
51... is a 0 bit line, 50a, 51a are 1 bit m
, QIO0,100a.

101.101a-QIIo, 110a, 111.11
11=G3-C100 constitutes one memory cell. Usually decoder 10
．． 1.0a is the drive circuit 11.0a according to the input address. lla, drive the corresponding word lines 40, 41, . . . and word lines 40a, 41a, one valley at a time, and turn on the gate of the MOS connected to the word line.
The potential stored in the capacitor in each bit line is read out. When the addresses of the word lines are different, for example, when the decoder 10 selects the word line 40 and the decoder 10a selects the word line 41a, the comparator 30 operates as a mere repeater, and the signal of the decoder 10a is sent to the & The data stored in the capacitors Cl00.101, . and the predetermined pit output is obtained.
On the other hand, the capacity C110a.

The i-memory data of 1°lla... is on the bit line 50a,
0 is input to the bit line selection circuit group 31 via 51a... (Beep because no switching signal is output) #50a, 5
The signals 1a, . . . pass through the P/M selection circuit group 31, are amplified by the sense amplifier 20a, and are input to the decoder 21a, where a predetermined pit output is obtained in the same way as on the 0 port side.

- When the Manryo decoder 10.10a selects the same address, for example, the decoder 10 selects the word line 41,
When the decoder 41a is selected, the comparator 30 which has received both outputs prohibits input to the drive circuit 11a and sends a switching signal to the bit line selection circuit group 31. Therefore, the word line 41 is driven by the drive circuit 11, but the drive circuit 11 does not operate, and the bit line selection circuit group 31 selects the bit line 50a.

51a... are input to the sense amplifier 20a from the bit line 50a to the bit line 50, and from the bit line 50 to the bit line 50, respectively.
Since the switching connection is made from 1a... to the bit lines 50, 51... and 151..., the input signals from the bit lines 50a and 51a are not generated on the 1-board side, and the input signals from the bit lines 50, 51... and p are input from the bit lines 50, 51... Sense amplifier 20a that received the signal + decoder 21a
Only the engine operates and pit output is obtained. Even if the cells are accessed in this way, two gate transistors for the same cell will never turn on. Above is 0 and 1 baud) $
Although the explanation has been made using two sets of access means 111, it is also possible to configure a circuit using three or more sets of access means. Further, the bit lines are switched by the bit line selection circuit group 31, but the bit lines 50a and 51a are changed to the bit lines 50.
A similar effect can be obtained by means of cutting off the input to the sense amplifier 20a without connecting it to the sense amplifier 20a.

(g) As described in detail, according to the present invention, a memory circuit having a plurality of address means for each address of a memory cell has a small area for one memory cell and has a small number of input/output connection lines. D-RAM allows implementation of high-density, multi-port, large-capacity memory.

[Brief explanation of drawings]

FIG. 1(a) is a basic circuit of a conventional static RAM, FIG. 1(b) is a basic circuit of a conventional two-vote static RAIVI, and FIG. 2 is a block diagram of a D-RAM according to an embodiment of the present invention. It is. In FIG. 2, 10 and 10a are word line decoders. 11, l1m is a word line drive circuit, 20.20a is a sense amplifier, 21゜21a is a pin DI decoder, 30 digit comparator, 31 is a bit line selection circuit + Q 100 g 1
00 a. 101.101a, 110,110a, 111,1ll
a, MOS transistor O and Cl00.101,1
10,111 is the capacity. 7- Figure 11- (σ) [8 8- Figure 2 words
1 word decoder
Tekokpa 2' jOσ 0 '° 0bi, 21 line de-goo---2
0k'' application sense amplifier 11
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gIQl Do 4 mouths
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4fQ st look
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OQllf: Route I Ql/HQ flfa l F1. Engineering C,,,1 :; ・: :1 --- 50ctl l 3f1
Bit line 7th birthday selection f&1 move

Claims (1)

[Claims] (1) Dynamic random access memory that stores p information depending on the presence or absence of charge stored in the capacity of the memory cell! J (D
- RAM) has a plurality of gate transistors and word lines and bit lines corresponding to the gate transistors for the same memory cell, and simultaneously performs writing and reading using different word lines selected by a plurality of word line decoders. Multi-boat D featuring
-'RAM0 (2) When the same decoder signal is detected by the decoder signal comparison circuit when accessing by multiple word line decoders in the above D-RAM, input to the lower word line drive circuit is prohibited and the upper Operate only the word line drive circuit, and switch the bit line input to the lower sense amplifier circuit from the 1st bit line to the upper bit line. The multi-board D- according to claim 1, characterized in that the signal on one bit line Lfjl is shared during simultaneous accesses in which η-Vτk'' repr is also sufficient.
RAIV! t.